1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35/* 82571EB Gigabit Ethernet Controller 36 * 82571EB Gigabit Ethernet Controller (Copper) 37 * 82571EB Gigabit Ethernet Controller (Fiber) 38 * 82571EB Dual Port Gigabit Mezzanine Adapter 39 * 82571EB Quad Port Gigabit Mezzanine Adapter 40 * 82571PT Gigabit PT Quad Port Server ExpressModule 41 * 82572EI Gigabit Ethernet Controller (Copper) 42 * 82572EI Gigabit Ethernet Controller (Fiber) 43 * 82572EI Gigabit Ethernet Controller 44 * 82573V Gigabit Ethernet Controller (Copper) 45 * 82573E Gigabit Ethernet Controller (Copper) 46 * 82573L Gigabit Ethernet Controller 47 * 82574L Gigabit Network Connection 48 * 82583V Gigabit Network Connection 49 */ 50 51#include "e1000_api.h" 52 53static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 54static void e1000_release_nvm_82571(struct e1000_hw *hw); 55static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 56 u16 words, u16 *data); 57static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 58static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 59static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 60static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 61 bool active); 62static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 63static s32 e1000_init_hw_82571(struct e1000_hw *hw); 64static void e1000_clear_vfta_82571(struct e1000_hw *hw); 65static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 66static s32 e1000_led_on_82574(struct e1000_hw *hw); 67static s32 e1000_setup_link_82571(struct e1000_hw *hw); 68static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 69static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 70static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 71static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 72static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 73static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 74static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 75static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 76static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 77static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 78static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 79static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 80static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, 81 bool active); 82static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, 83 bool active); 84static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 85static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 86 u16 words, u16 *data); 87static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 88static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 89 90/** 91 * e1000_init_phy_params_82571 - Init PHY func ptrs. 92 * @hw: pointer to the HW structure 93 **/ 94static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 95{ 96 struct e1000_phy_info *phy = &hw->phy; 97 s32 ret_val; 98 99 DEBUGFUNC("e1000_init_phy_params_82571"); 100 101 if (hw->phy.media_type != e1000_media_type_copper) { 102 phy->type = e1000_phy_none; 103 return E1000_SUCCESS; 104 } 105 106 phy->addr = 1; 107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 108 phy->reset_delay_us = 100; 109 110 phy->ops.check_reset_block = e1000_check_reset_block_generic; 111 phy->ops.reset = e1000_phy_hw_reset_generic; 112 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 113 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 114 phy->ops.power_up = e1000_power_up_phy_copper; 115 phy->ops.power_down = e1000_power_down_phy_copper_82571; 116 117 switch (hw->mac.type) { 118 case e1000_82571: 119 case e1000_82572: 120 phy->type = e1000_phy_igp_2; 121 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 122 phy->ops.get_info = e1000_get_phy_info_igp; 123 phy->ops.check_polarity = e1000_check_polarity_igp; 124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 125 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 126 phy->ops.read_reg = e1000_read_phy_reg_igp; 127 phy->ops.write_reg = e1000_write_phy_reg_igp; 128 phy->ops.acquire = e1000_get_hw_semaphore_82571; 129 phy->ops.release = e1000_put_hw_semaphore_82571; 130 break; 131 case e1000_82573: 132 phy->type = e1000_phy_m88; 133 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 134 phy->ops.get_info = e1000_get_phy_info_m88; 135 phy->ops.check_polarity = e1000_check_polarity_m88; 136 phy->ops.commit = e1000_phy_sw_reset_generic; 137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 138 phy->ops.get_cable_length = e1000_get_cable_length_m88; 139 phy->ops.read_reg = e1000_read_phy_reg_m88; 140 phy->ops.write_reg = e1000_write_phy_reg_m88; 141 phy->ops.acquire = e1000_get_hw_semaphore_82571; 142 phy->ops.release = e1000_put_hw_semaphore_82571; 143 break; 144 case e1000_82574: 145 case e1000_82583: 146 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex); 147 148 phy->type = e1000_phy_bm; 149 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 150 phy->ops.get_info = e1000_get_phy_info_m88; 151 phy->ops.check_polarity = e1000_check_polarity_m88; 152 phy->ops.commit = e1000_phy_sw_reset_generic; 153 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 154 phy->ops.get_cable_length = e1000_get_cable_length_m88; 155 phy->ops.read_reg = e1000_read_phy_reg_bm2; 156 phy->ops.write_reg = e1000_write_phy_reg_bm2; 157 phy->ops.acquire = e1000_get_hw_semaphore_82574; 158 phy->ops.release = e1000_put_hw_semaphore_82574; 159 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 160 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 161 break; 162 default: 163 return -E1000_ERR_PHY; 164 break; 165 } 166 167 /* This can only be done after all function pointers are setup. */ 168 ret_val = e1000_get_phy_id_82571(hw); 169 if (ret_val) { 170 DEBUGOUT("Error getting PHY ID\n"); 171 return ret_val; 172 } 173 174 /* Verify phy id */ 175 switch (hw->mac.type) { 176 case e1000_82571: 177 case e1000_82572: 178 if (phy->id != IGP01E1000_I_PHY_ID) 179 ret_val = -E1000_ERR_PHY; 180 break; 181 case e1000_82573: 182 if (phy->id != M88E1111_I_PHY_ID) 183 ret_val = -E1000_ERR_PHY; 184 break; 185 case e1000_82574: 186 case e1000_82583: 187 if (phy->id != BME1000_E_PHY_ID_R2) 188 ret_val = -E1000_ERR_PHY; 189 break; 190 default: 191 ret_val = -E1000_ERR_PHY; 192 break; 193 } 194 195 if (ret_val) 196 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 197 198 return ret_val; 199} 200 201/** 202 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 203 * @hw: pointer to the HW structure 204 **/ 205static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 206{ 207 struct e1000_nvm_info *nvm = &hw->nvm; 208 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 209 u16 size; 210 211 DEBUGFUNC("e1000_init_nvm_params_82571"); 212 213 nvm->opcode_bits = 8; 214 nvm->delay_usec = 1; 215 switch (nvm->override) { 216 case e1000_nvm_override_spi_large: 217 nvm->page_size = 32; 218 nvm->address_bits = 16; 219 break; 220 case e1000_nvm_override_spi_small: 221 nvm->page_size = 8; 222 nvm->address_bits = 8; 223 break; 224 default: 225 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 226 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 227 break; 228 } 229 230 switch (hw->mac.type) { 231 case e1000_82573: 232 case e1000_82574: 233 case e1000_82583: 234 if (((eecd >> 15) & 0x3) == 0x3) { 235 nvm->type = e1000_nvm_flash_hw; 236 nvm->word_size = 2048; 237 /* Autonomous Flash update bit must be cleared due 238 * to Flash update issue. 239 */ 240 eecd &= ~E1000_EECD_AUPDEN; 241 E1000_WRITE_REG(hw, E1000_EECD, eecd); 242 break; 243 } 244 /* Fall Through */ 245 default: 246 nvm->type = e1000_nvm_eeprom_spi; 247 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 248 E1000_EECD_SIZE_EX_SHIFT); 249 /* Added to a constant, "size" becomes the left-shift value 250 * for setting word_size. 251 */ 252 size += NVM_WORD_SIZE_BASE_SHIFT; 253 254 /* EEPROM access above 16k is unsupported */ 255 if (size > 14) 256 size = 14; 257 nvm->word_size = 1 << size; 258 break; 259 } 260 261 /* Function Pointers */ 262 switch (hw->mac.type) { 263 case e1000_82574: 264 case e1000_82583: 265 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 266 nvm->ops.release = e1000_put_hw_semaphore_82574; 267 break; 268 default: 269 nvm->ops.acquire = e1000_acquire_nvm_82571; 270 nvm->ops.release = e1000_release_nvm_82571; 271 break; 272 } 273 nvm->ops.read = e1000_read_nvm_eerd; 274 nvm->ops.update = e1000_update_nvm_checksum_82571; 275 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 276 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 277 nvm->ops.write = e1000_write_nvm_82571; 278 279 return E1000_SUCCESS; 280} 281 282/** 283 * e1000_init_mac_params_82571 - Init MAC func ptrs. 284 * @hw: pointer to the HW structure 285 **/ 286static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 287{ 288 struct e1000_mac_info *mac = &hw->mac; 289 u32 swsm = 0; 290 u32 swsm2 = 0; 291 bool force_clear_smbi = FALSE; 292 293 DEBUGFUNC("e1000_init_mac_params_82571"); 294 295 /* Set media type and media-dependent function pointers */ 296 switch (hw->device_id) { 297 case E1000_DEV_ID_82571EB_FIBER: 298 case E1000_DEV_ID_82572EI_FIBER: 299 case E1000_DEV_ID_82571EB_QUAD_FIBER: 300 hw->phy.media_type = e1000_media_type_fiber; 301 mac->ops.setup_physical_interface = 302 e1000_setup_fiber_serdes_link_82571; 303 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 304 mac->ops.get_link_up_info = 305 e1000_get_speed_and_duplex_fiber_serdes_generic; 306 break; 307 case E1000_DEV_ID_82571EB_SERDES: 308 case E1000_DEV_ID_82571EB_SERDES_DUAL: 309 case E1000_DEV_ID_82571EB_SERDES_QUAD: 310 case E1000_DEV_ID_82572EI_SERDES: 311 hw->phy.media_type = e1000_media_type_internal_serdes; 312 mac->ops.setup_physical_interface = 313 e1000_setup_fiber_serdes_link_82571; 314 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 315 mac->ops.get_link_up_info = 316 e1000_get_speed_and_duplex_fiber_serdes_generic; 317 break; 318 default: 319 hw->phy.media_type = e1000_media_type_copper; 320 mac->ops.setup_physical_interface = 321 e1000_setup_copper_link_82571; 322 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 323 mac->ops.get_link_up_info = 324 e1000_get_speed_and_duplex_copper_generic; 325 break; 326 } 327 328 /* Set mta register count */ 329 mac->mta_reg_count = 128; 330 /* Set rar entry count */ 331 mac->rar_entry_count = E1000_RAR_ENTRIES; 332 /* Set if part includes ASF firmware */ 333 mac->asf_firmware_present = TRUE; 334 /* Adaptive IFS supported */ 335 mac->adaptive_ifs = TRUE; 336 337 /* Function pointers */ 338 339 /* bus type/speed/width */ 340 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 341 /* reset */ 342 mac->ops.reset_hw = e1000_reset_hw_82571; 343 /* hw initialization */ 344 mac->ops.init_hw = e1000_init_hw_82571; 345 /* link setup */ 346 mac->ops.setup_link = e1000_setup_link_82571; 347 /* multicast address update */ 348 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 349 /* writing VFTA */ 350 mac->ops.write_vfta = e1000_write_vfta_generic; 351 /* clearing VFTA */ 352 mac->ops.clear_vfta = e1000_clear_vfta_82571; 353 /* read mac address */ 354 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 355 /* ID LED init */ 356 mac->ops.id_led_init = e1000_id_led_init_generic; 357 /* setup LED */ 358 mac->ops.setup_led = e1000_setup_led_generic; 359 /* cleanup LED */ 360 mac->ops.cleanup_led = e1000_cleanup_led_generic; 361 /* turn off LED */ 362 mac->ops.led_off = e1000_led_off_generic; 363 /* clear hardware counters */ 364 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 365 366 /* MAC-specific function pointers */ 367 switch (hw->mac.type) { 368 case e1000_82573: 369 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 370 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 371 mac->ops.led_on = e1000_led_on_generic; 372 mac->ops.blink_led = e1000_blink_led_generic; 373 374 /* FWSM register */ 375 mac->has_fwsm = TRUE; 376 /* ARC supported; valid only if manageability features are 377 * enabled. 378 */ 379 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 380 E1000_FWSM_MODE_MASK); 381 break; 382 case e1000_82574: 383 case e1000_82583: 384 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 385 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 386 mac->ops.led_on = e1000_led_on_82574; 387 break; 388 default: 389 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 390 mac->ops.led_on = e1000_led_on_generic; 391 mac->ops.blink_led = e1000_blink_led_generic; 392 393 /* FWSM register */ 394 mac->has_fwsm = TRUE; 395 break; 396 } 397 398 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before 399 * first NVM or PHY access. This should be done for single-port 400 * devices, and for one port only on dual-port devices so that 401 * for those devices we can still use the SMBI lock to synchronize 402 * inter-port accesses to the PHY & NVM. 403 */ 404 switch (hw->mac.type) { 405 case e1000_82571: 406 case e1000_82572: 407 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 408 409 if (!(swsm2 & E1000_SWSM2_LOCK)) { 410 /* Only do this for the first interface on this card */ 411 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | 412 E1000_SWSM2_LOCK); 413 force_clear_smbi = TRUE; 414 } else { 415 force_clear_smbi = FALSE; 416 } 417 break; 418 default: 419 force_clear_smbi = TRUE; 420 break; 421 } 422 423 if (force_clear_smbi) { 424 /* Make sure SWSM.SMBI is clear */ 425 swsm = E1000_READ_REG(hw, E1000_SWSM); 426 if (swsm & E1000_SWSM_SMBI) { 427 /* This bit should not be set on a first interface, and 428 * indicates that the bootagent or EFI code has 429 * improperly left this bit enabled 430 */ 431 DEBUGOUT("Please update your 82571 Bootagent\n"); 432 } 433 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 434 } 435 436 /* Initialze device specific counter of SMBI acquisition timeouts. */ 437 hw->dev_spec._82571.smb_counter = 0; 438 439 return E1000_SUCCESS; 440} 441 442/** 443 * e1000_init_function_pointers_82571 - Init func ptrs. 444 * @hw: pointer to the HW structure 445 * 446 * Called to initialize all function pointers and parameters. 447 **/ 448void e1000_init_function_pointers_82571(struct e1000_hw *hw) 449{ 450 DEBUGFUNC("e1000_init_function_pointers_82571"); 451 452 hw->mac.ops.init_params = e1000_init_mac_params_82571; 453 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 454 hw->phy.ops.init_params = e1000_init_phy_params_82571; 455} 456 457/** 458 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 459 * @hw: pointer to the HW structure 460 * 461 * Reads the PHY registers and stores the PHY ID and possibly the PHY 462 * revision in the hardware structure. 463 **/ 464static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 465{ 466 struct e1000_phy_info *phy = &hw->phy; 467 s32 ret_val; 468 u16 phy_id = 0; 469 470 DEBUGFUNC("e1000_get_phy_id_82571"); 471 472 switch (hw->mac.type) { 473 case e1000_82571: 474 case e1000_82572: 475 /* The 82571 firmware may still be configuring the PHY. 476 * In this case, we cannot access the PHY until the 477 * configuration is done. So we explicitly set the 478 * PHY ID. 479 */ 480 phy->id = IGP01E1000_I_PHY_ID; 481 break; 482 case e1000_82573: 483 return e1000_get_phy_id(hw); 484 break; 485 case e1000_82574: 486 case e1000_82583: 487 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 488 if (ret_val) 489 return ret_val; 490 491 phy->id = (u32)(phy_id << 16); 492 usec_delay(20); 493 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 494 if (ret_val) 495 return ret_val; 496 497 phy->id |= (u32)(phy_id); 498 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 499 break; 500 default: 501 return -E1000_ERR_PHY; 502 break; 503 } 504 505 return E1000_SUCCESS; 506} 507 508/** 509 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 510 * @hw: pointer to the HW structure 511 * 512 * Acquire the HW semaphore to access the PHY or NVM 513 **/ 514static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 515{ 516 u32 swsm; 517 s32 sw_timeout = hw->nvm.word_size + 1; 518 s32 fw_timeout = hw->nvm.word_size + 1; 519 s32 i = 0; 520 521 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 522 523 /* If we have timedout 3 times on trying to acquire 524 * the inter-port SMBI semaphore, there is old code 525 * operating on the other port, and it is not 526 * releasing SMBI. Modify the number of times that 527 * we try for the semaphore to interwork with this 528 * older code. 529 */ 530 if (hw->dev_spec._82571.smb_counter > 2) 531 sw_timeout = 1; 532 533 /* Get the SW semaphore */ 534 while (i < sw_timeout) { 535 swsm = E1000_READ_REG(hw, E1000_SWSM); 536 if (!(swsm & E1000_SWSM_SMBI)) 537 break; 538 539 usec_delay(50); 540 i++; 541 } 542 543 if (i == sw_timeout) { 544 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 545 hw->dev_spec._82571.smb_counter++; 546 } 547 /* Get the FW semaphore. */ 548 for (i = 0; i < fw_timeout; i++) { 549 swsm = E1000_READ_REG(hw, E1000_SWSM); 550 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 551 552 /* Semaphore acquired if bit latched */ 553 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 554 break; 555 556 usec_delay(50); 557 } 558 559 if (i == fw_timeout) { 560 /* Release semaphores */ 561 e1000_put_hw_semaphore_82571(hw); 562 DEBUGOUT("Driver can't access the NVM\n"); 563 return -E1000_ERR_NVM; 564 } 565 566 return E1000_SUCCESS; 567} 568 569/** 570 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 571 * @hw: pointer to the HW structure 572 * 573 * Release hardware semaphore used to access the PHY or NVM 574 **/ 575static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 576{ 577 u32 swsm; 578 579 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 580 581 swsm = E1000_READ_REG(hw, E1000_SWSM); 582 583 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 584 585 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 586} 587 588/** 589 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 590 * @hw: pointer to the HW structure 591 * 592 * Acquire the HW semaphore during reset. 593 * 594 **/ 595static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 596{ 597 u32 extcnf_ctrl; 598 s32 i = 0; 599 600 DEBUGFUNC("e1000_get_hw_semaphore_82573"); 601 602 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 603 do { 604 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 605 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 606 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 607 608 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 609 break; 610 611 msec_delay(2); 612 i++; 613 } while (i < MDIO_OWNERSHIP_TIMEOUT); 614 615 if (i == MDIO_OWNERSHIP_TIMEOUT) { 616 /* Release semaphores */ 617 e1000_put_hw_semaphore_82573(hw); 618 DEBUGOUT("Driver can't access the PHY\n"); 619 return -E1000_ERR_PHY; 620 } 621 622 return E1000_SUCCESS; 623} 624 625/** 626 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 627 * @hw: pointer to the HW structure 628 * 629 * Release hardware semaphore used during reset. 630 * 631 **/ 632static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 633{ 634 u32 extcnf_ctrl; 635 636 DEBUGFUNC("e1000_put_hw_semaphore_82573"); 637 638 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 639 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 640 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 641} 642 643/** 644 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 645 * @hw: pointer to the HW structure 646 * 647 * Acquire the HW semaphore to access the PHY or NVM. 648 * 649 **/ 650static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 651{ 652 s32 ret_val; 653 654 DEBUGFUNC("e1000_get_hw_semaphore_82574"); 655 656 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex); 657 ret_val = e1000_get_hw_semaphore_82573(hw); 658 if (ret_val) 659 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 660 return ret_val; 661} 662 663/** 664 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 665 * @hw: pointer to the HW structure 666 * 667 * Release hardware semaphore used to access the PHY or NVM 668 * 669 **/ 670static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 671{ 672 DEBUGFUNC("e1000_put_hw_semaphore_82574"); 673 674 e1000_put_hw_semaphore_82573(hw); 675 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex); 676} 677 678/** 679 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 680 * @hw: pointer to the HW structure 681 * @active: TRUE to enable LPLU, FALSE to disable 682 * 683 * Sets the LPLU D0 state according to the active flag. 684 * LPLU will not be activated unless the 685 * device autonegotiation advertisement meets standards of 686 * either 10 or 10/100 or 10/100/1000 at all duplexes. 687 * This is a function pointer entry point only called by 688 * PHY setup routines. 689 **/ 690static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 691{ 692 u32 data = E1000_READ_REG(hw, E1000_POEMB); 693 694 DEBUGFUNC("e1000_set_d0_lplu_state_82574"); 695 696 if (active) 697 data |= E1000_PHY_CTRL_D0A_LPLU; 698 else 699 data &= ~E1000_PHY_CTRL_D0A_LPLU; 700 701 E1000_WRITE_REG(hw, E1000_POEMB, data); 702 return E1000_SUCCESS; 703} 704 705/** 706 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 707 * @hw: pointer to the HW structure 708 * @active: boolean used to enable/disable lplu 709 * 710 * The low power link up (lplu) state is set to the power management level D3 711 * when active is TRUE, else clear lplu for D3. LPLU 712 * is used during Dx states where the power conservation is most important. 713 * During driver activity, SmartSpeed should be enabled so performance is 714 * maintained. 715 **/ 716static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 717{ 718 u32 data = E1000_READ_REG(hw, E1000_POEMB); 719 720 DEBUGFUNC("e1000_set_d3_lplu_state_82574"); 721 722 if (!active) { 723 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 724 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 725 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 726 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 727 data |= E1000_PHY_CTRL_NOND0A_LPLU; 728 } 729 730 E1000_WRITE_REG(hw, E1000_POEMB, data); 731 return E1000_SUCCESS; 732} 733 734/** 735 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 736 * @hw: pointer to the HW structure 737 * 738 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 739 * Then for non-82573 hardware, set the EEPROM access request bit and wait 740 * for EEPROM access grant bit. If the access grant bit is not set, release 741 * hardware semaphore. 742 **/ 743static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 744{ 745 s32 ret_val; 746 747 DEBUGFUNC("e1000_acquire_nvm_82571"); 748 749 ret_val = e1000_get_hw_semaphore_82571(hw); 750 if (ret_val) 751 return ret_val; 752 753 switch (hw->mac.type) { 754 case e1000_82573: 755 break; 756 default: 757 ret_val = e1000_acquire_nvm_generic(hw); 758 break; 759 } 760 761 if (ret_val) 762 e1000_put_hw_semaphore_82571(hw); 763 764 return ret_val; 765} 766 767/** 768 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 769 * @hw: pointer to the HW structure 770 * 771 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 772 **/ 773static void e1000_release_nvm_82571(struct e1000_hw *hw) 774{ 775 DEBUGFUNC("e1000_release_nvm_82571"); 776 777 e1000_release_nvm_generic(hw); 778 e1000_put_hw_semaphore_82571(hw); 779} 780 781/** 782 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 783 * @hw: pointer to the HW structure 784 * @offset: offset within the EEPROM to be written to 785 * @words: number of words to write 786 * @data: 16 bit word(s) to be written to the EEPROM 787 * 788 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 789 * 790 * If e1000_update_nvm_checksum is not called after this function, the 791 * EEPROM will most likely contain an invalid checksum. 792 **/ 793static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 794 u16 *data) 795{ 796 s32 ret_val; 797 798 DEBUGFUNC("e1000_write_nvm_82571"); 799 800 switch (hw->mac.type) { 801 case e1000_82573: 802 case e1000_82574: 803 case e1000_82583: 804 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 805 break; 806 case e1000_82571: 807 case e1000_82572: 808 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 809 break; 810 default: 811 ret_val = -E1000_ERR_NVM; 812 break; 813 } 814 815 return ret_val; 816} 817 818/** 819 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 820 * @hw: pointer to the HW structure 821 * 822 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 823 * up to the checksum. Then calculates the EEPROM checksum and writes the 824 * value to the EEPROM. 825 **/ 826static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 827{ 828 u32 eecd; 829 s32 ret_val; 830 u16 i; 831 832 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 833 834 ret_val = e1000_update_nvm_checksum_generic(hw); 835 if (ret_val) 836 return ret_val; 837 838 /* If our nvm is an EEPROM, then we're done 839 * otherwise, commit the checksum to the flash NVM. 840 */ 841 if (hw->nvm.type != e1000_nvm_flash_hw) 842 return E1000_SUCCESS; 843 844 /* Check for pending operations. */ 845 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 846 msec_delay(1); 847 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) 848 break; 849 } 850 851 if (i == E1000_FLASH_UPDATES) 852 return -E1000_ERR_NVM; 853 854 /* Reset the firmware if using STM opcode. */ 855 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 856 /* The enabling of and the actual reset must be done 857 * in two write cycles. 858 */ 859 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 860 E1000_WRITE_FLUSH(hw); 861 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 862 } 863 864 /* Commit the write to flash */ 865 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 866 E1000_WRITE_REG(hw, E1000_EECD, eecd); 867 868 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 869 msec_delay(1); 870 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) 871 break; 872 } 873 874 if (i == E1000_FLASH_UPDATES) 875 return -E1000_ERR_NVM; 876 877 return E1000_SUCCESS; 878} 879 880/** 881 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 882 * @hw: pointer to the HW structure 883 * 884 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 885 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 886 **/ 887static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 888{ 889 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 890 891 if (hw->nvm.type == e1000_nvm_flash_hw) 892 e1000_fix_nvm_checksum_82571(hw); 893 894 return e1000_validate_nvm_checksum_generic(hw); 895} 896 897/** 898 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 899 * @hw: pointer to the HW structure 900 * @offset: offset within the EEPROM to be written to 901 * @words: number of words to write 902 * @data: 16 bit word(s) to be written to the EEPROM 903 * 904 * After checking for invalid values, poll the EEPROM to ensure the previous 905 * command has completed before trying to write the next word. After write 906 * poll for completion. 907 * 908 * If e1000_update_nvm_checksum is not called after this function, the 909 * EEPROM will most likely contain an invalid checksum. 910 **/ 911static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 912 u16 words, u16 *data) 913{ 914 struct e1000_nvm_info *nvm = &hw->nvm; 915 u32 i, eewr = 0; 916 s32 ret_val = E1000_SUCCESS; 917 918 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 919 920 /* A check for invalid values: offset too large, too many words, 921 * and not enough words. 922 */ 923 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 924 (words == 0)) { 925 DEBUGOUT("nvm parameter(s) out of bounds\n"); 926 return -E1000_ERR_NVM; 927 } 928 929 for (i = 0; i < words; i++) { 930 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) | 931 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | 932 E1000_NVM_RW_REG_START); 933 934 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 935 if (ret_val) 936 break; 937 938 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 939 940 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 941 if (ret_val) 942 break; 943 } 944 945 return ret_val; 946} 947 948/** 949 * e1000_get_cfg_done_82571 - Poll for configuration done 950 * @hw: pointer to the HW structure 951 * 952 * Reads the management control register for the config done bit to be set. 953 **/ 954static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 955{ 956 s32 timeout = PHY_CFG_TIMEOUT; 957 958 DEBUGFUNC("e1000_get_cfg_done_82571"); 959 960 while (timeout) { 961 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 962 E1000_NVM_CFG_DONE_PORT_0) 963 break; 964 msec_delay(1); 965 timeout--; 966 } 967 if (!timeout) { 968 DEBUGOUT("MNG configuration cycle has not completed.\n"); 969 return -E1000_ERR_RESET; 970 } 971 972 return E1000_SUCCESS; 973} 974 975/** 976 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 977 * @hw: pointer to the HW structure 978 * @active: TRUE to enable LPLU, FALSE to disable 979 * 980 * Sets the LPLU D0 state according to the active flag. When activating LPLU 981 * this function also disables smart speed and vice versa. LPLU will not be 982 * activated unless the device autonegotiation advertisement meets standards 983 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 984 * pointer entry point only called by PHY setup routines. 985 **/ 986static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 987{ 988 struct e1000_phy_info *phy = &hw->phy; 989 s32 ret_val; 990 u16 data; 991 992 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 993 994 if (!(phy->ops.read_reg)) 995 return E1000_SUCCESS; 996 997 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 998 if (ret_val) 999 return ret_val; 1000 1001 if (active) { 1002 data |= IGP02E1000_PM_D0_LPLU; 1003 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1004 data); 1005 if (ret_val) 1006 return ret_val; 1007 1008 /* When LPLU is enabled, we should disable SmartSpeed */ 1009 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1010 &data); 1011 if (ret_val) 1012 return ret_val; 1013 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1015 data); 1016 if (ret_val) 1017 return ret_val; 1018 } else { 1019 data &= ~IGP02E1000_PM_D0_LPLU; 1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1021 data); 1022 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1023 * during Dx states where the power conservation is most 1024 * important. During driver activity we should enable 1025 * SmartSpeed, so performance is maintained. 1026 */ 1027 if (phy->smart_speed == e1000_smart_speed_on) { 1028 ret_val = phy->ops.read_reg(hw, 1029 IGP01E1000_PHY_PORT_CONFIG, 1030 &data); 1031 if (ret_val) 1032 return ret_val; 1033 1034 data |= IGP01E1000_PSCFR_SMART_SPEED; 1035 ret_val = phy->ops.write_reg(hw, 1036 IGP01E1000_PHY_PORT_CONFIG, 1037 data); 1038 if (ret_val) 1039 return ret_val; 1040 } else if (phy->smart_speed == e1000_smart_speed_off) { 1041 ret_val = phy->ops.read_reg(hw, 1042 IGP01E1000_PHY_PORT_CONFIG, 1043 &data); 1044 if (ret_val) 1045 return ret_val; 1046 1047 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1048 ret_val = phy->ops.write_reg(hw, 1049 IGP01E1000_PHY_PORT_CONFIG, 1050 data); 1051 if (ret_val) 1052 return ret_val; 1053 } 1054 } 1055 1056 return E1000_SUCCESS; 1057} 1058 1059/** 1060 * e1000_reset_hw_82571 - Reset hardware 1061 * @hw: pointer to the HW structure 1062 * 1063 * This resets the hardware into a known state. 1064 **/ 1065static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 1066{ 1067 u32 ctrl, ctrl_ext, eecd, tctl; 1068 s32 ret_val; 1069 1070 DEBUGFUNC("e1000_reset_hw_82571"); 1071 1072 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1073 * on the last TLP read/write transaction when MAC is reset. 1074 */ 1075 ret_val = e1000_disable_pcie_master_generic(hw); 1076 if (ret_val) 1077 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1078 1079 DEBUGOUT("Masking off all interrupts\n"); 1080 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1081 1082 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1083 tctl = E1000_READ_REG(hw, E1000_TCTL); 1084 tctl &= ~E1000_TCTL_EN; 1085 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1086 E1000_WRITE_FLUSH(hw); 1087 1088 msec_delay(10); 1089 1090 /* Must acquire the MDIO ownership before MAC reset. 1091 * Ownership defaults to firmware after a reset. 1092 */ 1093 switch (hw->mac.type) { 1094 case e1000_82573: 1095 ret_val = e1000_get_hw_semaphore_82573(hw); 1096 break; 1097 case e1000_82574: 1098 case e1000_82583: 1099 ret_val = e1000_get_hw_semaphore_82574(hw); 1100 break; 1101 default: 1102 break; 1103 } 1104 1105 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1106 1107 DEBUGOUT("Issuing a global reset to MAC\n"); 1108 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1109 1110 /* Must release MDIO ownership and mutex after MAC reset. */ 1111 switch (hw->mac.type) { 1112 case e1000_82573: 1113 /* Release mutex only if the hw semaphore is acquired */ 1114 if (!ret_val) 1115 e1000_put_hw_semaphore_82573(hw); 1116 break; 1117 case e1000_82574: 1118 case e1000_82583: 1119 /* Release mutex only if the hw semaphore is acquired */ 1120 if (!ret_val) 1121 e1000_put_hw_semaphore_82574(hw); 1122 break; 1123 default: 1124 break; 1125 } 1126 1127 if (hw->nvm.type == e1000_nvm_flash_hw) { 1128 usec_delay(10); 1129 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1130 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1131 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1132 E1000_WRITE_FLUSH(hw); 1133 } 1134 1135 ret_val = e1000_get_auto_rd_done_generic(hw); 1136 if (ret_val) 1137 /* We don't want to continue accessing MAC registers. */ 1138 return ret_val; 1139 1140 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1141 * Need to wait for Phy configuration completion before accessing 1142 * NVM and Phy. 1143 */ 1144 1145 switch (hw->mac.type) { 1146 case e1000_82571: 1147 case e1000_82572: 1148 /* REQ and GNT bits need to be cleared when using AUTO_RD 1149 * to access the EEPROM. 1150 */ 1151 eecd = E1000_READ_REG(hw, E1000_EECD); 1152 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); 1153 E1000_WRITE_REG(hw, E1000_EECD, eecd); 1154 break; 1155 case e1000_82573: 1156 case e1000_82574: 1157 case e1000_82583: 1158 msec_delay(25); 1159 break; 1160 default: 1161 break; 1162 } 1163 1164 /* Clear any pending interrupt events. */ 1165 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1166 E1000_READ_REG(hw, E1000_ICR); 1167 1168 if (hw->mac.type == e1000_82571) { 1169 /* Install any alternate MAC address into RAR0 */ 1170 ret_val = e1000_check_alt_mac_addr_generic(hw); 1171 if (ret_val) 1172 return ret_val; 1173 1174 e1000_set_laa_state_82571(hw, TRUE); 1175 } 1176 1177 /* Reinitialize the 82571 serdes link state machine */ 1178 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1179 hw->mac.serdes_link_state = e1000_serdes_link_down; 1180 1181 return E1000_SUCCESS; 1182} 1183 1184/** 1185 * e1000_init_hw_82571 - Initialize hardware 1186 * @hw: pointer to the HW structure 1187 * 1188 * This inits the hardware readying it for operation. 1189 **/ 1190static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1191{ 1192 struct e1000_mac_info *mac = &hw->mac; 1193 u32 reg_data; 1194 s32 ret_val; 1195 u16 i, rar_count = mac->rar_entry_count; 1196 1197 DEBUGFUNC("e1000_init_hw_82571"); 1198 1199 e1000_initialize_hw_bits_82571(hw); 1200 1201 /* Initialize identification LED */ 1202 ret_val = mac->ops.id_led_init(hw); 1203 /* An error is not fatal and we should not stop init due to this */ 1204 if (ret_val) 1205 DEBUGOUT("Error initializing identification LED\n"); 1206 1207 /* Disabling VLAN filtering */ 1208 DEBUGOUT("Initializing the IEEE VLAN\n"); 1209 mac->ops.clear_vfta(hw); 1210 1211 /* Setup the receive address. 1212 * If, however, a locally administered address was assigned to the 1213 * 82571, we must reserve a RAR for it to work around an issue where 1214 * resetting one port will reload the MAC on the other port. 1215 */ 1216 if (e1000_get_laa_state_82571(hw)) 1217 rar_count--; 1218 e1000_init_rx_addrs_generic(hw, rar_count); 1219 1220 /* Zero out the Multicast HASH table */ 1221 DEBUGOUT("Zeroing the MTA\n"); 1222 for (i = 0; i < mac->mta_reg_count; i++) 1223 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1224 1225 /* Setup link and flow control */ 1226 ret_val = mac->ops.setup_link(hw); 1227 1228 /* Set the transmit descriptor write-back policy */ 1229 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1230 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1231 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 1232 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1233 1234 /* ...for both queues. */ 1235 switch (mac->type) { 1236 case e1000_82573: 1237 e1000_enable_tx_pkt_filtering_generic(hw); 1238 /* fall through */ 1239 case e1000_82574: 1240 case e1000_82583: 1241 reg_data = E1000_READ_REG(hw, E1000_GCR); 1242 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1243 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1244 break; 1245 default: 1246 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1247 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1248 E1000_TXDCTL_FULL_TX_DESC_WB | 1249 E1000_TXDCTL_COUNT_DESC); 1250 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1251 break; 1252 } 1253 1254 /* Clear all of the statistics registers (clear on read). It is 1255 * important that we do this after we have tried to establish link 1256 * because the symbol error count will increment wildly if there 1257 * is no link. 1258 */ 1259 e1000_clear_hw_cntrs_82571(hw); 1260 1261 return ret_val; 1262} 1263 1264/** 1265 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1266 * @hw: pointer to the HW structure 1267 * 1268 * Initializes required hardware-dependent bits needed for normal operation. 1269 **/ 1270static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1271{ 1272 u32 reg; 1273 1274 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1275 1276 /* Transmit Descriptor Control 0 */ 1277 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1278 reg |= (1 << 22); 1279 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1280 1281 /* Transmit Descriptor Control 1 */ 1282 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1283 reg |= (1 << 22); 1284 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1285 1286 /* Transmit Arbitration Control 0 */ 1287 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1288 reg &= ~(0xF << 27); /* 30:27 */ 1289 switch (hw->mac.type) { 1290 case e1000_82571: 1291 case e1000_82572: 1292 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1293 break; 1294 case e1000_82574: 1295 case e1000_82583: 1296 reg |= (1 << 26); 1297 break; 1298 default: 1299 break; 1300 } 1301 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1302 1303 /* Transmit Arbitration Control 1 */ 1304 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1305 switch (hw->mac.type) { 1306 case e1000_82571: 1307 case e1000_82572: 1308 reg &= ~((1 << 29) | (1 << 30)); 1309 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1310 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1311 reg &= ~(1 << 28); 1312 else 1313 reg |= (1 << 28); 1314 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1315 break; 1316 default: 1317 break; 1318 } 1319 1320 /* Device Control */ 1321 switch (hw->mac.type) { 1322 case e1000_82573: 1323 case e1000_82574: 1324 case e1000_82583: 1325 reg = E1000_READ_REG(hw, E1000_CTRL); 1326 reg &= ~(1 << 29); 1327 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1328 break; 1329 default: 1330 break; 1331 } 1332 1333 /* Extended Device Control */ 1334 switch (hw->mac.type) { 1335 case e1000_82573: 1336 case e1000_82574: 1337 case e1000_82583: 1338 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1339 reg &= ~(1 << 23); 1340 reg |= (1 << 22); 1341 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1342 break; 1343 default: 1344 break; 1345 } 1346 1347 if (hw->mac.type == e1000_82571) { 1348 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1349 reg |= E1000_PBA_ECC_CORR_EN; 1350 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1351 } 1352 1353 /* Workaround for hardware errata. 1354 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1355 */ 1356 if ((hw->mac.type == e1000_82571) || 1357 (hw->mac.type == e1000_82572)) { 1358 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1359 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1360 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1361 } 1362 1363 /* Disable IPv6 extension header parsing because some malformed 1364 * IPv6 headers can hang the Rx. 1365 */ 1366 if (hw->mac.type <= e1000_82573) { 1367 reg = E1000_READ_REG(hw, E1000_RFCTL); 1368 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1369 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1370 } 1371 1372 /* PCI-Ex Control Registers */ 1373 switch (hw->mac.type) { 1374 case e1000_82574: 1375 case e1000_82583: 1376 reg = E1000_READ_REG(hw, E1000_GCR); 1377 reg |= (1 << 22); 1378 E1000_WRITE_REG(hw, E1000_GCR, reg); 1379 1380 /* Workaround for hardware errata. 1381 * apply workaround for hardware errata documented in errata 1382 * docs Fixes issue where some error prone or unreliable PCIe 1383 * completions are occurring, particularly with ASPM enabled. 1384 * Without fix, issue can cause Tx timeouts. 1385 */ 1386 reg = E1000_READ_REG(hw, E1000_GCR2); 1387 reg |= 1; 1388 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1389 break; 1390 default: 1391 break; 1392 } 1393 1394 return; 1395} 1396 1397/** 1398 * e1000_clear_vfta_82571 - Clear VLAN filter table 1399 * @hw: pointer to the HW structure 1400 * 1401 * Clears the register array which contains the VLAN filter table by 1402 * setting all the values to 0. 1403 **/ 1404static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1405{ 1406 u32 offset; 1407 u32 vfta_value = 0; 1408 u32 vfta_offset = 0; 1409 u32 vfta_bit_in_reg = 0; 1410 1411 DEBUGFUNC("e1000_clear_vfta_82571"); 1412 1413 switch (hw->mac.type) { 1414 case e1000_82573: 1415 case e1000_82574: 1416 case e1000_82583: 1417 if (hw->mng_cookie.vlan_id != 0) { 1418 /* The VFTA is a 4096b bit-field, each identifying 1419 * a single VLAN ID. The following operations 1420 * determine which 32b entry (i.e. offset) into the 1421 * array we want to set the VLAN ID (i.e. bit) of 1422 * the manageability unit. 1423 */ 1424 vfta_offset = (hw->mng_cookie.vlan_id >> 1425 E1000_VFTA_ENTRY_SHIFT) & 1426 E1000_VFTA_ENTRY_MASK; 1427 vfta_bit_in_reg = 1428 1 << (hw->mng_cookie.vlan_id & 1429 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1430 } 1431 break; 1432 default: 1433 break; 1434 } 1435 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1436 /* If the offset we want to clear is the same offset of the 1437 * manageability VLAN ID, then clear all bits except that of 1438 * the manageability unit. 1439 */ 1440 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1441 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1442 E1000_WRITE_FLUSH(hw); 1443 } 1444} 1445 1446/** 1447 * e1000_check_mng_mode_82574 - Check manageability is enabled 1448 * @hw: pointer to the HW structure 1449 * 1450 * Reads the NVM Initialization Control Word 2 and returns TRUE 1451 * (>0) if any manageability is enabled, else FALSE (0). 1452 **/ 1453static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1454{ 1455 u16 data; 1456 s32 ret_val; 1457 1458 DEBUGFUNC("e1000_check_mng_mode_82574"); 1459 1460 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1461 if (ret_val) 1462 return FALSE; 1463 1464 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1465} 1466 1467/** 1468 * e1000_led_on_82574 - Turn LED on 1469 * @hw: pointer to the HW structure 1470 * 1471 * Turn LED on. 1472 **/ 1473static s32 e1000_led_on_82574(struct e1000_hw *hw) 1474{ 1475 u32 ctrl; 1476 u32 i; 1477 1478 DEBUGFUNC("e1000_led_on_82574"); 1479 1480 ctrl = hw->mac.ledctl_mode2; 1481 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1482 /* If no link, then turn LED on by setting the invert bit 1483 * for each LED that's "on" (0x0E) in ledctl_mode2. 1484 */ 1485 for (i = 0; i < 4; i++) 1486 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1487 E1000_LEDCTL_MODE_LED_ON) 1488 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1489 } 1490 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1491 1492 return E1000_SUCCESS; 1493} 1494 1495/** 1496 * e1000_check_phy_82574 - check 82574 phy hung state 1497 * @hw: pointer to the HW structure 1498 * 1499 * Returns whether phy is hung or not 1500 **/ 1501bool e1000_check_phy_82574(struct e1000_hw *hw) 1502{ 1503 u16 status_1kbt = 0; 1504 u16 receive_errors = 0; 1505 s32 ret_val; 1506 1507 DEBUGFUNC("e1000_check_phy_82574"); 1508 1509 /* Read PHY Receive Error counter first, if its is max - all F's then 1510 * read the Base1000T status register If both are max then PHY is hung. 1511 */ 1512 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, 1513 &receive_errors); 1514 if (ret_val) 1515 return FALSE; 1516 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1517 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, 1518 &status_1kbt); 1519 if (ret_val) 1520 return FALSE; 1521 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1522 E1000_IDLE_ERROR_COUNT_MASK) 1523 return TRUE; 1524 } 1525 1526 return FALSE; 1527} 1528 1529 1530/** 1531 * e1000_setup_link_82571 - Setup flow control and link settings 1532 * @hw: pointer to the HW structure 1533 * 1534 * Determines which flow control settings to use, then configures flow 1535 * control. Calls the appropriate media-specific link configuration 1536 * function. Assuming the adapter has a valid link partner, a valid link 1537 * should be established. Assumes the hardware has previously been reset 1538 * and the transmitter and receiver are not enabled. 1539 **/ 1540static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1541{ 1542 DEBUGFUNC("e1000_setup_link_82571"); 1543 1544 /* 82573 does not have a word in the NVM to determine 1545 * the default flow control setting, so we explicitly 1546 * set it to full. 1547 */ 1548 switch (hw->mac.type) { 1549 case e1000_82573: 1550 case e1000_82574: 1551 case e1000_82583: 1552 if (hw->fc.requested_mode == e1000_fc_default) 1553 hw->fc.requested_mode = e1000_fc_full; 1554 break; 1555 default: 1556 break; 1557 } 1558 1559 return e1000_setup_link_generic(hw); 1560} 1561 1562/** 1563 * e1000_setup_copper_link_82571 - Configure copper link settings 1564 * @hw: pointer to the HW structure 1565 * 1566 * Configures the link for auto-neg or forced speed and duplex. Then we check 1567 * for link, once link is established calls to configure collision distance 1568 * and flow control are called. 1569 **/ 1570static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1571{ 1572 u32 ctrl; 1573 s32 ret_val; 1574 1575 DEBUGFUNC("e1000_setup_copper_link_82571"); 1576 1577 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1578 ctrl |= E1000_CTRL_SLU; 1579 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1580 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1581 1582 switch (hw->phy.type) { 1583 case e1000_phy_m88: 1584 case e1000_phy_bm: 1585 ret_val = e1000_copper_link_setup_m88(hw); 1586 break; 1587 case e1000_phy_igp_2: 1588 ret_val = e1000_copper_link_setup_igp(hw); 1589 break; 1590 default: 1591 return -E1000_ERR_PHY; 1592 break; 1593 } 1594 1595 if (ret_val) 1596 return ret_val; 1597 1598 return e1000_setup_copper_link_generic(hw); 1599} 1600 1601/** 1602 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1603 * @hw: pointer to the HW structure 1604 * 1605 * Configures collision distance and flow control for fiber and serdes links. 1606 * Upon successful setup, poll for link. 1607 **/ 1608static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1609{ 1610 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1611 1612 switch (hw->mac.type) { 1613 case e1000_82571: 1614 case e1000_82572: 1615 /* If SerDes loopback mode is entered, there is no form 1616 * of reset to take the adapter out of that mode. So we 1617 * have to explicitly take the adapter out of loopback 1618 * mode. This prevents drivers from twiddling their thumbs 1619 * if another tool failed to take it out of loopback mode. 1620 */ 1621 E1000_WRITE_REG(hw, E1000_SCTL, 1622 E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1623 break; 1624 default: 1625 break; 1626 } 1627 1628 return e1000_setup_fiber_serdes_link_generic(hw); 1629} 1630 1631/** 1632 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1633 * @hw: pointer to the HW structure 1634 * 1635 * Reports the link state as up or down. 1636 * 1637 * If autonegotiation is supported by the link partner, the link state is 1638 * determined by the result of autonegotiation. This is the most likely case. 1639 * If autonegotiation is not supported by the link partner, and the link 1640 * has a valid signal, force the link up. 1641 * 1642 * The link state is represented internally here by 4 states: 1643 * 1644 * 1) down 1645 * 2) autoneg_progress 1646 * 3) autoneg_complete (the link successfully autonegotiated) 1647 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1648 * 1649 **/ 1650static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1651{ 1652 struct e1000_mac_info *mac = &hw->mac; 1653 u32 rxcw; 1654 u32 ctrl; 1655 u32 status; 1656 u32 txcw; 1657 u32 i; 1658 s32 ret_val = E1000_SUCCESS; 1659 1660 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1661 1662 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1663 status = E1000_READ_REG(hw, E1000_STATUS); 1664 E1000_READ_REG(hw, E1000_RXCW); 1665 /* SYNCH bit and IV bit are sticky */ 1666 usec_delay(10); 1667 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1668 1669 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1670 /* Receiver is synchronized with no invalid bits. */ 1671 switch (mac->serdes_link_state) { 1672 case e1000_serdes_link_autoneg_complete: 1673 if (!(status & E1000_STATUS_LU)) { 1674 /* We have lost link, retry autoneg before 1675 * reporting link failure 1676 */ 1677 mac->serdes_link_state = 1678 e1000_serdes_link_autoneg_progress; 1679 mac->serdes_has_link = FALSE; 1680 DEBUGOUT("AN_UP -> AN_PROG\n"); 1681 } else { 1682 mac->serdes_has_link = TRUE; 1683 } 1684 break; 1685 1686 case e1000_serdes_link_forced_up: 1687 /* If we are receiving /C/ ordered sets, re-enable 1688 * auto-negotiation in the TXCW register and disable 1689 * forced link in the Device Control register in an 1690 * attempt to auto-negotiate with our link partner. 1691 */ 1692 if (rxcw & E1000_RXCW_C) { 1693 /* Enable autoneg, and unforce link up */ 1694 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1695 E1000_WRITE_REG(hw, E1000_CTRL, 1696 (ctrl & ~E1000_CTRL_SLU)); 1697 mac->serdes_link_state = 1698 e1000_serdes_link_autoneg_progress; 1699 mac->serdes_has_link = FALSE; 1700 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1701 } else { 1702 mac->serdes_has_link = TRUE; 1703 } 1704 break; 1705 1706 case e1000_serdes_link_autoneg_progress: 1707 if (rxcw & E1000_RXCW_C) { 1708 /* We received /C/ ordered sets, meaning the 1709 * link partner has autonegotiated, and we can 1710 * trust the Link Up (LU) status bit. 1711 */ 1712 if (status & E1000_STATUS_LU) { 1713 mac->serdes_link_state = 1714 e1000_serdes_link_autoneg_complete; 1715 DEBUGOUT("AN_PROG -> AN_UP\n"); 1716 mac->serdes_has_link = TRUE; 1717 } else { 1718 /* Autoneg completed, but failed. */ 1719 mac->serdes_link_state = 1720 e1000_serdes_link_down; 1721 DEBUGOUT("AN_PROG -> DOWN\n"); 1722 } 1723 } else { 1724 /* The link partner did not autoneg. 1725 * Force link up and full duplex, and change 1726 * state to forced. 1727 */ 1728 E1000_WRITE_REG(hw, E1000_TXCW, 1729 (mac->txcw & ~E1000_TXCW_ANE)); 1730 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1731 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1732 1733 /* Configure Flow Control after link up. */ 1734 ret_val = 1735 e1000_config_fc_after_link_up_generic(hw); 1736 if (ret_val) { 1737 DEBUGOUT("Error config flow control\n"); 1738 break; 1739 } 1740 mac->serdes_link_state = 1741 e1000_serdes_link_forced_up; 1742 mac->serdes_has_link = TRUE; 1743 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1744 } 1745 break; 1746 1747 case e1000_serdes_link_down: 1748 default: 1749 /* The link was down but the receiver has now gained 1750 * valid sync, so lets see if we can bring the link 1751 * up. 1752 */ 1753 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1754 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & 1755 ~E1000_CTRL_SLU)); 1756 mac->serdes_link_state = 1757 e1000_serdes_link_autoneg_progress; 1758 mac->serdes_has_link = FALSE; 1759 DEBUGOUT("DOWN -> AN_PROG\n"); 1760 break; 1761 } 1762 } else { 1763 if (!(rxcw & E1000_RXCW_SYNCH)) { 1764 mac->serdes_has_link = FALSE; 1765 mac->serdes_link_state = e1000_serdes_link_down; 1766 DEBUGOUT("ANYSTATE -> DOWN\n"); 1767 } else { 1768 /* Check several times, if SYNCH bit and CONFIG 1769 * bit both are consistently 1 then simply ignore 1770 * the IV bit and restart Autoneg 1771 */ 1772 for (i = 0; i < AN_RETRY_COUNT; i++) { 1773 usec_delay(10); 1774 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1775 if ((rxcw & E1000_RXCW_SYNCH) && 1776 (rxcw & E1000_RXCW_C)) 1777 continue; 1778 1779 if (rxcw & E1000_RXCW_IV) { 1780 mac->serdes_has_link = FALSE; 1781 mac->serdes_link_state = 1782 e1000_serdes_link_down; 1783 DEBUGOUT("ANYSTATE -> DOWN\n"); 1784 break; 1785 } 1786 } 1787 1788 if (i == AN_RETRY_COUNT) { 1789 txcw = E1000_READ_REG(hw, E1000_TXCW); 1790 txcw |= E1000_TXCW_ANE; 1791 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1792 mac->serdes_link_state = 1793 e1000_serdes_link_autoneg_progress; 1794 mac->serdes_has_link = FALSE; 1795 DEBUGOUT("ANYSTATE -> AN_PROG\n"); 1796 } 1797 } 1798 } 1799 1800 return ret_val; 1801} 1802 1803/** 1804 * e1000_valid_led_default_82571 - Verify a valid default LED config 1805 * @hw: pointer to the HW structure 1806 * @data: pointer to the NVM (EEPROM) 1807 * 1808 * Read the EEPROM for the current default LED configuration. If the 1809 * LED configuration is not valid, set to a valid LED configuration. 1810 **/ 1811static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1812{ 1813 s32 ret_val; 1814 1815 DEBUGFUNC("e1000_valid_led_default_82571"); 1816 1817 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1818 if (ret_val) { 1819 DEBUGOUT("NVM Read Error\n"); 1820 return ret_val; 1821 } 1822 1823 switch (hw->mac.type) { 1824 case e1000_82573: 1825 case e1000_82574: 1826 case e1000_82583: 1827 if (*data == ID_LED_RESERVED_F746) 1828 *data = ID_LED_DEFAULT_82573; 1829 break; 1830 default: 1831 if (*data == ID_LED_RESERVED_0000 || 1832 *data == ID_LED_RESERVED_FFFF) 1833 *data = ID_LED_DEFAULT; 1834 break; 1835 } 1836 1837 return E1000_SUCCESS; 1838} 1839 1840/** 1841 * e1000_get_laa_state_82571 - Get locally administered address state 1842 * @hw: pointer to the HW structure 1843 * 1844 * Retrieve and return the current locally administered address state. 1845 **/ 1846bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1847{ 1848 DEBUGFUNC("e1000_get_laa_state_82571"); 1849 1850 if (hw->mac.type != e1000_82571) 1851 return FALSE; 1852 1853 return hw->dev_spec._82571.laa_is_present; 1854} 1855 1856/** 1857 * e1000_set_laa_state_82571 - Set locally administered address state 1858 * @hw: pointer to the HW structure 1859 * @state: enable/disable locally administered address 1860 * 1861 * Enable/Disable the current locally administered address state. 1862 **/ 1863void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1864{ 1865 DEBUGFUNC("e1000_set_laa_state_82571"); 1866 1867 if (hw->mac.type != e1000_82571) 1868 return; 1869 1870 hw->dev_spec._82571.laa_is_present = state; 1871 1872 /* If workaround is activated... */ 1873 if (state) 1874 /* Hold a copy of the LAA in RAR[14] This is done so that 1875 * between the time RAR[0] gets clobbered and the time it 1876 * gets fixed, the actual LAA is in one of the RARs and no 1877 * incoming packets directed to this port are dropped. 1878 * Eventually the LAA will be in RAR[0] and RAR[14]. 1879 */ 1880 hw->mac.ops.rar_set(hw, hw->mac.addr, 1881 hw->mac.rar_entry_count - 1); 1882 return; 1883} 1884 1885/** 1886 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1887 * @hw: pointer to the HW structure 1888 * 1889 * Verifies that the EEPROM has completed the update. After updating the 1890 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1891 * the checksum fix is not implemented, we need to set the bit and update 1892 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1893 * we need to return bad checksum. 1894 **/ 1895static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1896{ 1897 struct e1000_nvm_info *nvm = &hw->nvm; 1898 s32 ret_val; 1899 u16 data; 1900 1901 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1902 1903 if (nvm->type != e1000_nvm_flash_hw) 1904 return E1000_SUCCESS; 1905 1906 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1907 * 10h-12h. Checksum may need to be fixed. 1908 */ 1909 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1910 if (ret_val) 1911 return ret_val; 1912 1913 if (!(data & 0x10)) { 1914 /* Read 0x23 and check bit 15. This bit is a 1 1915 * when the checksum has already been fixed. If 1916 * the checksum is still wrong and this bit is a 1917 * 1, we need to return bad checksum. Otherwise, 1918 * we need to set this bit to a 1 and update the 1919 * checksum. 1920 */ 1921 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1922 if (ret_val) 1923 return ret_val; 1924 1925 if (!(data & 0x8000)) { 1926 data |= 0x8000; 1927 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1928 if (ret_val) 1929 return ret_val; 1930 ret_val = nvm->ops.update(hw); 1931 if (ret_val) 1932 return ret_val; 1933 } 1934 } 1935 1936 return E1000_SUCCESS; 1937} 1938 1939 1940/** 1941 * e1000_read_mac_addr_82571 - Read device MAC address 1942 * @hw: pointer to the HW structure 1943 **/ 1944static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1945{ 1946 DEBUGFUNC("e1000_read_mac_addr_82571"); 1947 1948 if (hw->mac.type == e1000_82571) { 1949 s32 ret_val; 1950 1951 /* If there's an alternate MAC address place it in RAR0 1952 * so that it will override the Si installed default perm 1953 * address. 1954 */ 1955 ret_val = e1000_check_alt_mac_addr_generic(hw); 1956 if (ret_val) 1957 return ret_val; 1958 } 1959 1960 return e1000_read_mac_addr_generic(hw); 1961} 1962 1963/** 1964 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1965 * @hw: pointer to the HW structure 1966 * 1967 * In the case of a PHY power down to save power, or to turn off link during a 1968 * driver unload, or wake on lan is not enabled, remove the link. 1969 **/ 1970static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1971{ 1972 struct e1000_phy_info *phy = &hw->phy; 1973 struct e1000_mac_info *mac = &hw->mac; 1974 1975 if (!phy->ops.check_reset_block) 1976 return; 1977 1978 /* If the management interface is not enabled, then power down */ 1979 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1980 e1000_power_down_phy_copper(hw); 1981 1982 return; 1983} 1984 1985/** 1986 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1987 * @hw: pointer to the HW structure 1988 * 1989 * Clears the hardware counters by reading the counter registers. 1990 **/ 1991static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1992{ 1993 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1994 1995 e1000_clear_hw_cntrs_base_generic(hw); 1996 1997 E1000_READ_REG(hw, E1000_PRC64); 1998 E1000_READ_REG(hw, E1000_PRC127); 1999 E1000_READ_REG(hw, E1000_PRC255); 2000 E1000_READ_REG(hw, E1000_PRC511); 2001 E1000_READ_REG(hw, E1000_PRC1023); 2002 E1000_READ_REG(hw, E1000_PRC1522); 2003 E1000_READ_REG(hw, E1000_PTC64); 2004 E1000_READ_REG(hw, E1000_PTC127); 2005 E1000_READ_REG(hw, E1000_PTC255); 2006 E1000_READ_REG(hw, E1000_PTC511); 2007 E1000_READ_REG(hw, E1000_PTC1023); 2008 E1000_READ_REG(hw, E1000_PTC1522); 2009 2010 E1000_READ_REG(hw, E1000_ALGNERRC); 2011 E1000_READ_REG(hw, E1000_RXERRC); 2012 E1000_READ_REG(hw, E1000_TNCRS); 2013 E1000_READ_REG(hw, E1000_CEXTERR); 2014 E1000_READ_REG(hw, E1000_TSCTC); 2015 E1000_READ_REG(hw, E1000_TSCTFC); 2016 2017 E1000_READ_REG(hw, E1000_MGTPRC); 2018 E1000_READ_REG(hw, E1000_MGTPDC); 2019 E1000_READ_REG(hw, E1000_MGTPTC); 2020 2021 E1000_READ_REG(hw, E1000_IAC); 2022 E1000_READ_REG(hw, E1000_ICRXOC); 2023 2024 E1000_READ_REG(hw, E1000_ICRXPTC); 2025 E1000_READ_REG(hw, E1000_ICRXATC); 2026 E1000_READ_REG(hw, E1000_ICTXPTC); 2027 E1000_READ_REG(hw, E1000_ICTXATC); 2028 E1000_READ_REG(hw, E1000_ICTXQEC); 2029 E1000_READ_REG(hw, E1000_ICTXQMTC); 2030 E1000_READ_REG(hw, E1000_ICRXDMTC); 2031} 2032