if_athvar.h revision 241170
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 241170 2012-10-03 23:23:45Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHVAR_H 36116743Ssam#define _DEV_ATH_ATHVAR_H 37116743Ssam 38185522Ssam#include <dev/ath/ath_hal/ah.h> 39185522Ssam#include <dev/ath/ath_hal/ah_desc.h> 40119783Ssam#include <net80211/ieee80211_radiotap.h> 41116743Ssam#include <dev/ath/if_athioctl.h> 42138570Ssam#include <dev/ath/if_athrate.h> 43116743Ssam 44116743Ssam#define ATH_TIMEOUT 1000 45116743Ssam 46220033Sadrian/* 47237000Sadrian * There is a separate TX ath_buf pool for management frames. 48237000Sadrian * This ensures that management frames such as probe responses 49237000Sadrian * and BAR frames can be transmitted during periods of high 50237000Sadrian * TX activity. 51237000Sadrian */ 52237000Sadrian#define ATH_MGMT_TXBUF 32 53237000Sadrian 54237000Sadrian/* 55220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU. 56220033Sadrian */ 57220053Sadrian#ifdef ATH_ENABLE_11N 58235804Sadrian#define ATH_TXBUF 512 59220033Sadrian#define ATH_RXBUF 512 60220033Sadrian#endif 61220033Sadrian 62155481Ssam#ifndef ATH_RXBUF 63116743Ssam#define ATH_RXBUF 40 /* number of RX buffers */ 64155481Ssam#endif 65155481Ssam#ifndef ATH_TXBUF 66170530Ssam#define ATH_TXBUF 200 /* number of TX buffers */ 67155481Ssam#endif 68178354Ssam#define ATH_BCBUF 4 /* number of beacon buffers */ 69178354Ssam 70140438Ssam#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71138570Ssam#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72155480Ssam#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73138570Ssam#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74116743Ssam 75225818Sadrian#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76147067Ssam#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77147067Ssam#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78147067Ssam 79147057Ssam/* 80147057Ssam * The key cache is used for h/w cipher state and also for 81147057Ssam * tracking station state such as the current tx antenna. 82147057Ssam * We also setup a mapping table between key cache slot indices 83147057Ssam * and station state to short-circuit node lookups on rx. 84147057Ssam * Different parts have different size key caches. We handle 85147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state). 86147057Ssam */ 87147057Ssam#define ATH_KEYMAX 128 /* max key cache size we handle */ 88147057Ssam#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89147057Ssam 90170530Ssamstruct taskqueue; 91170530Ssamstruct kthread; 92170530Ssamstruct ath_buf; 93170530Ssam 94227328Sadrian#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95227328Sadrian 96227328Sadrian/* 97227328Sadrian * Per-TID state 98227328Sadrian * 99227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100227328Sadrian */ 101227328Sadrianstruct ath_tid { 102227328Sadrian TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103227328Sadrian u_int axq_depth; /* SW queue depth */ 104227328Sadrian char axq_name[48]; /* lock name */ 105227328Sadrian struct ath_node *an; /* pointer to parent */ 106227328Sadrian int tid; /* tid */ 107227328Sadrian int ac; /* which AC gets this trafic */ 108227328Sadrian int hwq_depth; /* how many buffers are on HW */ 109227328Sadrian 110240585Sadrian struct { 111240585Sadrian TAILQ_HEAD(,ath_buf) axq_q; /* filtered queue */ 112240585Sadrian u_int axq_depth; /* SW queue depth */ 113240585Sadrian char axq_name[48]; /* lock name */ 114240585Sadrian } filtq; 115240585Sadrian 116227328Sadrian /* 117227328Sadrian * Entry on the ath_txq; when there's traffic 118227328Sadrian * to send 119227328Sadrian */ 120227328Sadrian TAILQ_ENTRY(ath_tid) axq_qelem; 121227328Sadrian int sched; 122227328Sadrian int paused; /* >0 if the TID has been paused */ 123240585Sadrian 124240585Sadrian /* 125240585Sadrian * These are flags - perhaps later collapse 126240585Sadrian * down to a single uint32_t ? 127240585Sadrian */ 128235774Sadrian int addba_tx_pending; /* TX ADDBA pending */ 129233908Sadrian int bar_wait; /* waiting for BAR */ 130233908Sadrian int bar_tx; /* BAR TXed */ 131240585Sadrian int isfiltered; /* is this node currently filtered */ 132240585Sadrian int clrdmask; /* has clrdmask been set */ 133227328Sadrian 134227328Sadrian /* 135227328Sadrian * Is the TID being cleaned up after a transition 136227328Sadrian * from aggregation to non-aggregation? 137227328Sadrian * When this is set to 1, this TID will be paused 138227328Sadrian * and no further traffic will be queued until all 139227328Sadrian * the hardware packets pending for this TID have been 140227328Sadrian * TXed/completed; at which point (non-aggregation) 141227328Sadrian * traffic will resume being TXed. 142227328Sadrian */ 143227328Sadrian int cleanup_inprogress; 144227328Sadrian /* 145227328Sadrian * How many hardware-queued packets are 146227328Sadrian * waiting to be cleaned up. 147227328Sadrian * This is only valid if cleanup_inprogress is 1. 148227328Sadrian */ 149227328Sadrian int incomp; 150227328Sadrian 151227328Sadrian /* 152227328Sadrian * The following implements a ring representing 153227328Sadrian * the frames in the current BAW. 154227328Sadrian * To avoid copying the array content each time 155227328Sadrian * the BAW is moved, the baw_head/baw_tail point 156227328Sadrian * to the current BAW begin/end; when the BAW is 157227328Sadrian * shifted the head/tail of the array are also 158227328Sadrian * appropriately shifted. 159227328Sadrian */ 160227328Sadrian /* active tx buffers, beginning at current BAW */ 161227328Sadrian struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 162227328Sadrian /* where the baw head is in the array */ 163227328Sadrian int baw_head; 164227328Sadrian /* where the BAW tail is in the array */ 165227328Sadrian int baw_tail; 166227328Sadrian}; 167227328Sadrian 168138570Ssam/* driver-specific node state */ 169116743Ssamstruct ath_node { 170119150Ssam struct ieee80211_node an_node; /* base class */ 171178354Ssam u_int8_t an_mgmtrix; /* min h/w rate index */ 172178354Ssam u_int8_t an_mcastrix; /* mcast h/w rate index */ 173241170Sadrian uint32_t an_is_powersave; /* node is sleeping */ 174170530Ssam struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 175227328Sadrian struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 176227328Sadrian char an_name[32]; /* eg "wlan0_a1" */ 177227328Sadrian struct mtx an_mtx; /* protecting the ath_node state */ 178138570Ssam /* variable-length rate control state follows */ 179116743Ssam}; 180138570Ssam#define ATH_NODE(ni) ((struct ath_node *)(ni)) 181138570Ssam#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 182116743Ssam 183138570Ssam#define ATH_RSSI_LPF_LEN 10 184138570Ssam#define ATH_RSSI_DUMMY_MARKER 0x127 185138570Ssam#define ATH_EP_MUL(x, mul) ((x) * (mul)) 186138570Ssam#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 187138570Ssam#define ATH_LPF_RSSI(x, y, len) \ 188138570Ssam ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 189138570Ssam#define ATH_RSSI_LPF(x, y) do { \ 190138570Ssam if ((y) >= -20) \ 191138570Ssam x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 192138570Ssam} while (0) 193184358Ssam#define ATH_EP_RND(x,mul) \ 194184358Ssam ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 195184358Ssam#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 196138570Ssam 197237000Sadriantypedef enum { 198237000Sadrian ATH_BUFTYPE_NORMAL = 0, 199237000Sadrian ATH_BUFTYPE_MGMT = 1, 200237000Sadrian} ath_buf_type_t; 201237000Sadrian 202116743Ssamstruct ath_buf { 203227344Sadrian TAILQ_ENTRY(ath_buf) bf_list; 204227328Sadrian struct ath_buf * bf_next; /* next buffer in the aggregate */ 205116743Ssam int bf_nseg; 206238436Sadrian HAL_STATUS bf_rxstatus; 207186904Ssam uint16_t bf_flags; /* status flags (below) */ 208239282Sadrian uint16_t bf_descid; /* 16 bit descriptor ID */ 209116743Ssam struct ath_desc *bf_desc; /* virtual addr of desc */ 210165185Ssam struct ath_desc_status bf_status; /* tx/rx status */ 211116743Ssam bus_addr_t bf_daddr; /* physical addr of desc */ 212138570Ssam bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 213116743Ssam struct mbuf *bf_m; /* mbuf for buf */ 214116743Ssam struct ieee80211_node *bf_node; /* pointer to the node */ 215227328Sadrian struct ath_desc *bf_lastds; /* last descriptor for comp status */ 216227328Sadrian struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 217116743Ssam bus_size_t bf_mapsize; 218140438Ssam#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 219116743Ssam bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 220227328Sadrian 221227328Sadrian /* Completion function to call on TX complete (fail or not) */ 222227328Sadrian /* 223227328Sadrian * "fail" here is set to 1 if the queue entries were removed 224227328Sadrian * through a call to ath_tx_draintxq(). 225227328Sadrian */ 226227328Sadrian void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 227227328Sadrian 228227328Sadrian /* This state is kept to support software retries and aggregation */ 229227328Sadrian struct { 230237046Sadrian uint16_t bfs_seqno; /* sequence number of this packet */ 231227328Sadrian uint16_t bfs_ndelim; /* number of delims for padding */ 232227328Sadrian 233237046Sadrian uint8_t bfs_retries; /* retry count */ 234237046Sadrian uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 235237046Sadrian uint8_t bfs_nframes; /* number of frames in aggregate */ 236237046Sadrian uint8_t bfs_pri; /* packet AC priority */ 237237046Sadrian 238237046Sadrian struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 239237046Sadrian 240234109Sadrian u_int32_t bfs_aggr:1, /* part of aggregate? */ 241234109Sadrian bfs_aggrburst:1, /* part of aggregate burst? */ 242234109Sadrian bfs_isretried:1, /* retried frame? */ 243234109Sadrian bfs_dobaw:1, /* actually check against BAW? */ 244234109Sadrian bfs_addedbaw:1, /* has been added to the BAW */ 245234109Sadrian bfs_shpream:1, /* use short preamble */ 246234109Sadrian bfs_istxfrag:1, /* is fragmented */ 247234109Sadrian bfs_ismrr:1, /* do multi-rate TX retry */ 248234109Sadrian bfs_doprot:1, /* do RTS/CTS based protection */ 249236872Sadrian bfs_doratelookup:1; /* do rate lookup before each TX */ 250234109Sadrian 251227328Sadrian /* 252227328Sadrian * These fields are passed into the 253227328Sadrian * descriptor setup functions. 254227328Sadrian */ 255237153Sadrian 256237153Sadrian /* Make this an 8 bit value? */ 257227328Sadrian HAL_PKT_TYPE bfs_atype; /* packet type */ 258237153Sadrian 259237153Sadrian uint32_t bfs_pktlen; /* length of this packet */ 260237153Sadrian 261237153Sadrian uint16_t bfs_hdrlen; /* length of this packet header */ 262227328Sadrian uint16_t bfs_al; /* length of aggregate */ 263237153Sadrian 264237153Sadrian uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 265237153Sadrian uint8_t bfs_txrate0; /* first TX rate */ 266237153Sadrian uint8_t bfs_try0; /* first try count */ 267237153Sadrian 268237153Sadrian uint16_t bfs_txpower; /* tx power */ 269227328Sadrian uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 270237153Sadrian uint8_t bfs_ctsrate; /* CTS rate */ 271237153Sadrian 272237153Sadrian /* 16 bit? */ 273237153Sadrian int32_t bfs_keyix; /* crypto key index */ 274237153Sadrian int32_t bfs_txantenna; /* TX antenna config */ 275237153Sadrian 276237153Sadrian /* Make this an 8 bit value? */ 277227328Sadrian enum ieee80211_protmode bfs_protmode; 278237153Sadrian 279237153Sadrian /* 16 bit? */ 280237153Sadrian uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 281227328Sadrian struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 282227328Sadrian } bf_state; 283116743Ssam}; 284227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 285116743Ssam 286237000Sadrian#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 287186904Ssam#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 288186904Ssam 289138570Ssam/* 290138570Ssam * DMA state for tx/rx descriptors. 291138570Ssam */ 292138570Ssamstruct ath_descdma { 293138570Ssam const char* dd_name; 294138570Ssam struct ath_desc *dd_desc; /* descriptors */ 295238708Sadrian int dd_descsize; /* size of single descriptor */ 296138570Ssam bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 297158298Ssam bus_size_t dd_desc_len; /* size of dd_desc */ 298138570Ssam bus_dma_segment_t dd_dseg; 299138570Ssam bus_dma_tag_t dd_dmat; /* bus DMA tag */ 300138570Ssam bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 301138570Ssam struct ath_buf *dd_bufptr; /* associated buffers */ 302138570Ssam}; 303138570Ssam 304138570Ssam/* 305138570Ssam * Data transmit queue state. One of these exists for each 306138570Ssam * hardware transmit queue. Packets sent to us from above 307138570Ssam * are assigned to queues based on their priority. Not all 308138570Ssam * devices support a complete set of hardware transmit queues. 309138570Ssam * For those devices the array sc_ac2q will map multiple 310138570Ssam * priorities to fewer hardware queues (typically all to one 311138570Ssam * hardware queue). 312138570Ssam */ 313138570Ssamstruct ath_txq { 314227328Sadrian struct ath_softc *axq_softc; /* Needed for scheduling */ 315138570Ssam u_int axq_qnum; /* hardware q number */ 316178354Ssam#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 317190579Ssam u_int axq_ac; /* WME AC */ 318186904Ssam u_int axq_flags; 319186904Ssam#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 320156073Ssam u_int axq_depth; /* queue depth (stat only) */ 321227328Sadrian u_int axq_aggr_depth; /* how many aggregates are queued */ 322239197Sadrian u_int axq_fifo_depth; /* depth of FIFO frames */ 323138570Ssam u_int axq_intrcnt; /* interrupt count */ 324138570Ssam u_int32_t *axq_link; /* link ptr in last TX desc */ 325227344Sadrian TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 326138570Ssam struct mtx axq_lock; /* lock on q and link */ 327155482Ssam char axq_name[12]; /* e.g. "ath0_txq4" */ 328227344Sadrian 329227328Sadrian /* Per-TID traffic queue for software -> hardware TX */ 330227328Sadrian TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 331138570Ssam}; 332138570Ssam 333227328Sadrian#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 334227328Sadrian#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 335227328Sadrian#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 336241170Sadrian#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 337241170Sadrian MA_NOTOWNED) 338227328Sadrian 339155482Ssam#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 340155482Ssam snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 341155482Ssam device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 342167252Ssam mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 343161425Simp} while (0) 344138570Ssam#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 345138570Ssam#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 346138570Ssam#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 347239261Sadrian#define ATH_TXQ_LOCK_ASSERT(_tq) \ 348239261Sadrian mtx_assert(&(_tq)->axq_lock, MA_OWNED) 349239261Sadrian#define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 350239261Sadrian mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 351227328Sadrian#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 352138570Ssam 353236873Sadrian#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 354236873Sadrian ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 355240585Sadrian#define ATH_TID_UNLOCK_ASSERT(_sc, _tid) \ 356240585Sadrian ATH_TXQ_UNLOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 357236873Sadrian 358227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 359227344Sadrian TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 360227344Sadrian (_tq)->axq_depth++; \ 361227344Sadrian} while (0) 362138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 363227344Sadrian TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 364138570Ssam (_tq)->axq_depth++; \ 365138570Ssam} while (0) 366227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 367227344Sadrian TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 368138570Ssam (_tq)->axq_depth--; \ 369138570Ssam} while (0) 370239197Sadrian#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 371227344Sadrian#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 372138570Ssam 373178354Ssamstruct ath_vap { 374178354Ssam struct ieee80211vap av_vap; /* base class */ 375178354Ssam int av_bslot; /* beacon slot index */ 376178354Ssam struct ath_buf *av_bcbuf; /* beacon buffer */ 377178354Ssam struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 378178354Ssam struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 379178354Ssam 380178354Ssam void (*av_recv_mgmt)(struct ieee80211_node *, 381192468Ssam struct mbuf *, int, int, int); 382178354Ssam int (*av_newstate)(struct ieee80211vap *, 383178354Ssam enum ieee80211_state, int); 384178354Ssam void (*av_bmiss)(struct ieee80211vap *); 385241170Sadrian void (*av_node_ps)(struct ieee80211_node *, int); 386178354Ssam}; 387178354Ssam#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 388178354Ssam 389155491Ssamstruct taskqueue; 390155486Ssamstruct ath_tx99; 391155486Ssam 392227328Sadrian/* 393227328Sadrian * Whether to reset the TX/RX queue with or without 394227328Sadrian * a queue flush. 395227328Sadrian */ 396227328Sadriantypedef enum { 397227328Sadrian ATH_RESET_DEFAULT = 0, 398227328Sadrian ATH_RESET_NOLOSS = 1, 399227328Sadrian ATH_RESET_FULL = 2, 400227328Sadrian} ATH_RESET_TYPE; 401227328Sadrian 402238055Sadrianstruct ath_rx_methods { 403238055Sadrian void (*recv_stop)(struct ath_softc *sc, int dodelay); 404238055Sadrian int (*recv_start)(struct ath_softc *sc); 405238055Sadrian void (*recv_flush)(struct ath_softc *sc); 406238055Sadrian void (*recv_tasklet)(void *arg, int npending); 407238055Sadrian int (*recv_rxbuf_init)(struct ath_softc *sc, 408238055Sadrian struct ath_buf *bf); 409238284Sadrian int (*recv_setup)(struct ath_softc *sc); 410238284Sadrian int (*recv_teardown)(struct ath_softc *sc); 411238055Sadrian}; 412238055Sadrian 413238284Sadrian/* 414238284Sadrian * Represent the current state of the RX FIFO. 415238284Sadrian */ 416238284Sadrianstruct ath_rx_edma { 417238284Sadrian struct ath_buf **m_fifo; 418238284Sadrian int m_fifolen; 419238284Sadrian int m_fifo_head; 420238284Sadrian int m_fifo_tail; 421238284Sadrian int m_fifo_depth; 422238284Sadrian struct mbuf *m_rxpending; 423238284Sadrian}; 424238284Sadrian 425238855Sadrianstruct ath_tx_edma_fifo { 426238855Sadrian struct ath_buf **m_fifo; 427238855Sadrian int m_fifolen; 428238855Sadrian int m_fifo_head; 429238855Sadrian int m_fifo_tail; 430238855Sadrian int m_fifo_depth; 431238855Sadrian}; 432238855Sadrian 433238710Sadrianstruct ath_tx_methods { 434238710Sadrian int (*xmit_setup)(struct ath_softc *sc); 435238710Sadrian int (*xmit_teardown)(struct ath_softc *sc); 436238931Sadrian void (*xmit_attach_comp_func)(struct ath_softc *sc); 437238931Sadrian 438238931Sadrian void (*xmit_dma_restart)(struct ath_softc *sc, 439238931Sadrian struct ath_txq *txq); 440238931Sadrian void (*xmit_handoff)(struct ath_softc *sc, 441238931Sadrian struct ath_txq *txq, struct ath_buf *bf); 442239204Sadrian void (*xmit_drain)(struct ath_softc *sc, 443239204Sadrian ATH_RESET_TYPE reset_type); 444238710Sadrian}; 445238710Sadrian 446116743Ssamstruct ath_softc { 447147256Sbrooks struct ifnet *sc_ifp; /* interface common */ 448138570Ssam struct ath_stats sc_stats; /* interface statistics */ 449227328Sadrian struct ath_tx_aggr_stats sc_aggr_stats; 450234090Sadrian struct ath_intr_stats sc_intr_stats; 451235491Sadrian uint64_t sc_debug; 452240899Sadrian uint64_t sc_ktrdebug; 453178354Ssam int sc_nvaps; /* # vaps */ 454178354Ssam int sc_nstavaps; /* # station vaps */ 455195807Ssam int sc_nmeshvaps; /* # mbss vaps */ 456178354Ssam u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 457178354Ssam u_int8_t sc_nbssid0; /* # vap's using base mac */ 458178354Ssam uint32_t sc_bssidmask; /* bssid mask */ 459178354Ssam 460238055Sadrian struct ath_rx_methods sc_rx; 461238608Sadrian struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 462238710Sadrian struct ath_tx_methods sc_tx; 463238855Sadrian struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 464238710Sadrian 465238284Sadrian int sc_rx_statuslen; 466238284Sadrian int sc_tx_desclen; 467238284Sadrian int sc_tx_statuslen; 468238284Sadrian int sc_tx_nmaps; /* Number of TX maps */ 469238284Sadrian int sc_edma_bufsize; 470238055Sadrian 471227328Sadrian void (*sc_node_cleanup)(struct ieee80211_node *); 472138570Ssam void (*sc_node_free)(struct ieee80211_node *); 473116743Ssam device_t sc_dev; 474159290Ssam HAL_BUS_TAG sc_st; /* bus space tag */ 475159290Ssam HAL_BUS_HANDLE sc_sh; /* bus space handle */ 476116743Ssam bus_dma_tag_t sc_dmat; /* bus DMA tag */ 477116743Ssam struct mtx sc_mtx; /* master lock (recursive) */ 478227328Sadrian struct mtx sc_pcu_mtx; /* PCU access mutex */ 479227328Sadrian char sc_pcu_mtx_name[32]; 480238433Sadrian struct mtx sc_rx_mtx; /* RX access mutex */ 481238433Sadrian char sc_rx_mtx_name[32]; 482155491Ssam struct taskqueue *sc_tq; /* private task queue */ 483116743Ssam struct ath_hal *sc_ah; /* Atheros HAL */ 484138570Ssam struct ath_ratectrl *sc_rc; /* tx rate control support */ 485155486Ssam struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 486138570Ssam void (*sc_setdefantenna)(struct ath_softc *, u_int); 487178354Ssam unsigned int sc_invalid : 1,/* disable hardware accesses */ 488178354Ssam sc_mrretry : 1,/* multi-rate retry support */ 489238961Sadrian sc_mrrprot : 1,/* MRR + protection support */ 490178354Ssam sc_softled : 1,/* enable LED gpio status */ 491228891Sadrian sc_hardled : 1,/* enable MAC LED status */ 492178354Ssam sc_splitmic : 1,/* split TKIP MIC keys */ 493178354Ssam sc_needmib : 1,/* enable MIB stats intr */ 494178354Ssam sc_diversity: 1,/* enable rx diversity */ 495178354Ssam sc_hasveol : 1,/* tx VEOL support */ 496178354Ssam sc_ledstate : 1,/* LED on/off state */ 497178354Ssam sc_blinking : 1,/* LED blink operation active */ 498178354Ssam sc_mcastkey : 1,/* mcast key cache search */ 499178354Ssam sc_scanning : 1,/* scanning active */ 500155496Ssam sc_syncbeacon:1,/* sync/resync beacon timers */ 501178354Ssam sc_hasclrkey: 1,/* CLR key supported */ 502165571Ssam sc_xchanmode: 1,/* extended channel mode */ 503170530Ssam sc_outdoor : 1,/* outdoor operation */ 504178354Ssam sc_dturbo : 1,/* dynamic turbo in use */ 505178354Ssam sc_hasbmask : 1,/* bssid mask support */ 506195618Srpaulo sc_hasbmatch: 1,/* bssid match disable support*/ 507178354Ssam sc_hastsfadd: 1,/* tsf adjust support */ 508178354Ssam sc_beacons : 1,/* beacons running */ 509178354Ssam sc_swbmiss : 1,/* sta mode using sw bmiss */ 510178354Ssam sc_stagbeacons:1,/* use staggered beacons */ 511179401Ssam sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 512185744Ssam sc_resume_up: 1,/* on resume, start all vaps */ 513186904Ssam sc_tdma : 1,/* TDMA in use */ 514189380Ssam sc_setcca : 1,/* set/clr CCA with TDMA */ 515220324Sadrian sc_resetcal : 1,/* reset cal state next trip */ 516224588Sadrian sc_rxslink : 1,/* do self-linked final descriptor */ 517238284Sadrian sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 518238284Sadrian sc_isedma : 1;/* supports EDMA */ 519178751Ssam uint32_t sc_eerd; /* regdomain from EEPROM */ 520178751Ssam uint32_t sc_eecc; /* country code from EEPROM */ 521116743Ssam /* rate tables */ 522188783Ssam const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 523116743Ssam const HAL_RATE_TABLE *sc_currates; /* current rate table */ 524116743Ssam enum ieee80211_phymode sc_curmode; /* current phy mode */ 525155490Ssam HAL_OPMODE sc_opmode; /* current operating mode */ 526138570Ssam u_int16_t sc_curtxpow; /* current tx power limit */ 527170530Ssam u_int16_t sc_curaid; /* current association id */ 528187831Ssam struct ieee80211_channel *sc_curchan; /* current installed channel */ 529170530Ssam u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 530116743Ssam u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 531140432Ssam struct { 532140432Ssam u_int8_t ieeerate; /* IEEE rate */ 533140761Ssam u_int8_t rxflags; /* radiotap rx flags */ 534140761Ssam u_int8_t txflags; /* radiotap tx flags */ 535140432Ssam u_int16_t ledon; /* softled on time */ 536140432Ssam u_int16_t ledoff; /* softled off time */ 537140432Ssam } sc_hwmap[32]; /* h/w rate ix mappings */ 538138570Ssam u_int8_t sc_protrix; /* protection rate index */ 539170530Ssam u_int8_t sc_lastdatarix; /* last data frame rate index */ 540155483Ssam u_int sc_mcastrate; /* ieee rate for mcastrateix */ 541170530Ssam u_int sc_fftxqmin; /* min frames before staging */ 542170530Ssam u_int sc_fftxqmax; /* max frames before drop */ 543138570Ssam u_int sc_txantenna; /* tx antenna (fixed or auto) */ 544227346Sadrian 545116743Ssam HAL_INT sc_imask; /* interrupt mask copy */ 546227651Sadrian 547227346Sadrian /* 548227346Sadrian * These are modified in the interrupt handler as well as 549227346Sadrian * the task queues and other contexts. Thus these must be 550227346Sadrian * protected by a mutex, or they could clash. 551227346Sadrian * 552227346Sadrian * For now, access to these is behind the ATH_LOCK, 553227346Sadrian * just to save time. 554227346Sadrian */ 555227346Sadrian uint32_t sc_txq_active; /* bitmap of active TXQs */ 556227346Sadrian uint32_t sc_kickpcu; /* whether to kick the PCU */ 557227651Sadrian uint32_t sc_rxproc_cnt; /* In RX processing */ 558227651Sadrian uint32_t sc_txproc_cnt; /* In TX processing */ 559227651Sadrian uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 560227651Sadrian uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 561227651Sadrian uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 562227651Sadrian uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 563227346Sadrian 564138570Ssam u_int sc_keymax; /* size of key cache */ 565147057Ssam u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 566116743Ssam 567228891Sadrian /* 568228891Sadrian * Software based LED blinking 569228891Sadrian */ 570140432Ssam u_int sc_ledpin; /* GPIO pin for driving LED */ 571140432Ssam u_int sc_ledon; /* pin setting for LED on */ 572140432Ssam u_int sc_ledidle; /* idle polling interval */ 573140432Ssam int sc_ledevent; /* time of last LED event */ 574184368Ssam u_int8_t sc_txrix; /* current tx rate for LED */ 575140432Ssam u_int16_t sc_ledoff; /* off time for current blink */ 576140432Ssam struct callout sc_ledtimer; /* led off timer */ 577138570Ssam 578228891Sadrian /* 579228891Sadrian * Hardware based LED blinking 580228891Sadrian */ 581228891Sadrian int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 582228891Sadrian int sc_led_net_pin; /* MAC network LED GPIO pin */ 583228891Sadrian 584155515Ssam u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 585155515Ssam u_int sc_rfsilentpol; /* pin setting for rfkill on */ 586155515Ssam 587178354Ssam struct ath_descdma sc_rxdma; /* RX descriptors */ 588138570Ssam ath_bufhead sc_rxbuf; /* receive buffer */ 589116743Ssam u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 590116743Ssam struct task sc_rxtask; /* rx int processing */ 591138570Ssam u_int8_t sc_defant; /* current default antenna */ 592138570Ssam u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 593155492Ssam u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 594192468Ssam struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 595192468Ssam struct ath_rx_radiotap_header sc_rx_th; 596192468Ssam int sc_rx_th_len; 597192468Ssam u_int sc_monpass; /* frames to pass in mon.mode */ 598116743Ssam 599138570Ssam struct ath_descdma sc_txdma; /* TX descriptors */ 600239282Sadrian uint16_t sc_txbuf_descid; 601138570Ssam ath_bufhead sc_txbuf; /* transmit buffer */ 602237038Sadrian int sc_txbuf_cnt; /* how many buffers avail */ 603237000Sadrian struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 604237000Sadrian ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 605238836Sadrian struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 606138570Ssam struct mtx sc_txbuflock; /* txbuf lock */ 607155482Ssam char sc_txname[12]; /* e.g. "ath0_buf" */ 608138570Ssam u_int sc_txqsetup; /* h/w queues setup */ 609138570Ssam u_int sc_txintrperiod;/* tx interrupt batching */ 610138570Ssam struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 611138570Ssam struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 612116743Ssam struct task sc_txtask; /* tx int processing */ 613233673Sadrian struct task sc_txqtask; /* tx proc processing */ 614238709Sadrian 615238709Sadrian struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 616238709Sadrian struct mtx sc_txcomplock; /* TX EDMA completion lock */ 617238709Sadrian char sc_txcompname[12]; /* eg ath0_txcomp */ 618238709Sadrian 619189605Ssam int sc_wd_timer; /* count down for wd timer */ 620189605Ssam struct callout sc_wd_ch; /* tx watchdog timer */ 621192468Ssam struct ath_tx_radiotap_header sc_tx_th; 622192468Ssam int sc_tx_th_len; 623116743Ssam 624138570Ssam struct ath_descdma sc_bdma; /* beacon descriptors */ 625138570Ssam ath_bufhead sc_bbuf; /* beacon buffers */ 626116743Ssam u_int sc_bhalq; /* HAL q for outgoing beacons */ 627138570Ssam u_int sc_bmisscount; /* missed beacon transmits */ 628138570Ssam u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 629138570Ssam struct ath_txq *sc_cabq; /* tx q for cab frames */ 630116743Ssam struct task sc_bmisstask; /* bmiss int processing */ 631138570Ssam struct task sc_bstucktask; /* stuck beacon processing */ 632232163Sadrian struct task sc_resettask; /* interface reset task */ 633234369Sadrian struct task sc_fataltask; /* fatal task */ 634138570Ssam enum { 635138570Ssam OK, /* no change needed */ 636138570Ssam UPDATE, /* update pending */ 637138570Ssam COMMIT /* beacon sent, commit change */ 638138570Ssam } sc_updateslot; /* slot time update fsm */ 639178354Ssam int sc_slotupdate; /* slot to advance fsm */ 640178354Ssam struct ieee80211vap *sc_bslot[ATH_BCBUF]; 641178354Ssam int sc_nbcnvaps; /* # vaps with beacons */ 642116743Ssam 643116743Ssam struct callout sc_cal_ch; /* callout handle for cals */ 644185744Ssam int sc_lastlongcal; /* last long cal completed */ 645185744Ssam int sc_lastcalreset;/* last cal reset done */ 646217684Sadrian int sc_lastani; /* last ANI poll */ 647217684Sadrian int sc_lastshortcal; /* last short calibration */ 648217684Sadrian HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 649155485Ssam HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 650186904Ssam u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 651186904Ssam u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 652186904Ssam u_int sc_tdmaswba; /* TDMA SWBA counter */ 653186904Ssam u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 654186904Ssam u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 655186904Ssam u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 656186904Ssam u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 657186904Ssam u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 658217624Sadrian uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 659218151Sadrian int sc_txchainmask; /* currently configured TX chainmask */ 660218151Sadrian int sc_rxchainmask; /* currently configured RX chainmask */ 661233967Sadrian int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 662222585Sadrian 663232764Sadrian /* Queue limits */ 664232764Sadrian 665227328Sadrian /* 666232764Sadrian * To avoid queue starvation in congested conditions, 667232764Sadrian * these parameters tune the maximum number of frames 668232764Sadrian * queued to the data/mcastq before they're dropped. 669232764Sadrian * 670232764Sadrian * This is to prevent: 671232764Sadrian * + a single destination overwhelming everything, including 672232764Sadrian * management/multicast frames; 673232764Sadrian * + multicast frames overwhelming everything (when the 674232764Sadrian * air is sufficiently busy that cabq can't drain.) 675232764Sadrian * 676232764Sadrian * These implement: 677232764Sadrian * + data_minfree is the maximum number of free buffers 678232764Sadrian * overall to successfully allow a data frame. 679232764Sadrian * 680232794Sadrian * + mcastq_maxdepth is the maximum depth allowed of the cabq. 681232764Sadrian */ 682232764Sadrian int sc_txq_data_minfree; 683232764Sadrian int sc_txq_mcastq_maxdepth; 684232764Sadrian 685232764Sadrian /* 686227328Sadrian * Aggregation twiddles 687227328Sadrian * 688227328Sadrian * hwq_limit: how busy to keep the hardware queue - don't schedule 689227328Sadrian * further packets to the hardware, regardless of the TID 690227328Sadrian * tid_hwq_lo: how low the per-TID hwq count has to be before the 691227328Sadrian * TID will be scheduled again 692227328Sadrian * tid_hwq_hi: how many frames to queue to the HWQ before the TID 693227328Sadrian * stops being scheduled. 694227328Sadrian */ 695227328Sadrian int sc_hwq_limit; 696227328Sadrian int sc_tid_hwq_lo; 697227328Sadrian int sc_tid_hwq_hi; 698227328Sadrian 699222585Sadrian /* DFS related state */ 700222585Sadrian void *sc_dfs; /* Used by an optional DFS module */ 701222668Sadrian int sc_dodfs; /* Whether to enable DFS rx filter bits */ 702222585Sadrian struct task sc_dfstask; /* DFS processing task */ 703227328Sadrian 704227328Sadrian /* TX AMPDU handling */ 705227328Sadrian int (*sc_addba_request)(struct ieee80211_node *, 706227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 707227328Sadrian int (*sc_addba_response)(struct ieee80211_node *, 708227328Sadrian struct ieee80211_tx_ampdu *, int, int, int); 709227328Sadrian void (*sc_addba_stop)(struct ieee80211_node *, 710227328Sadrian struct ieee80211_tx_ampdu *); 711227328Sadrian void (*sc_addba_response_timeout) 712227328Sadrian (struct ieee80211_node *, 713227328Sadrian struct ieee80211_tx_ampdu *); 714227328Sadrian void (*sc_bar_response)(struct ieee80211_node *ni, 715227328Sadrian struct ieee80211_tx_ampdu *tap, 716227328Sadrian int status); 717116743Ssam}; 718116743Ssam 719121100Ssam#define ATH_LOCK_INIT(_sc) \ 720121100Ssam mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 721167252Ssam NULL, MTX_DEF | MTX_RECURSE) 722121100Ssam#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 723121100Ssam#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 724121100Ssam#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 725121100Ssam#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 726227651Sadrian#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 727121100Ssam 728227328Sadrian/* 729227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock. 730227328Sadrian * Although currently the interrupt code is run in netisr context and 731227328Sadrian * doesn't require this, this may change in the future. 732227328Sadrian * Please keep this in mind when protecting certain code paths 733227328Sadrian * with the PCU lock. 734227328Sadrian * 735227328Sadrian * The PCU lock is used to serialise access to the PCU so things such 736227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates 737227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash. 738227328Sadrian * 739227328Sadrian * Although the current single-thread taskqueue mechanism protects the 740227328Sadrian * majority of these situations by simply serialising them, there are 741227328Sadrian * a few others which occur at the same time. These include the TX path 742227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list), 743227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more. 744227328Sadrian */ 745227328Sadrian#define ATH_PCU_LOCK_INIT(_sc) do {\ 746227328Sadrian snprintf((_sc)->sc_pcu_mtx_name, \ 747227328Sadrian sizeof((_sc)->sc_pcu_mtx_name), \ 748227328Sadrian "%s PCU lock", \ 749227328Sadrian device_get_nameunit((_sc)->sc_dev)); \ 750227328Sadrian mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 751227328Sadrian NULL, MTX_DEF); \ 752227328Sadrian } while (0) 753227328Sadrian#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 754227328Sadrian#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 755227328Sadrian#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 756227328Sadrian#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 757227328Sadrian MA_OWNED) 758227651Sadrian#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 759227651Sadrian MA_NOTOWNED) 760227328Sadrian 761238433Sadrian/* 762238433Sadrian * The RX lock is primarily a(nother) workaround to ensure that the 763238433Sadrian * RX FIFO/list isn't modified by various execution paths. 764238433Sadrian * Even though RX occurs in a single context (the ath taskqueue), the 765238433Sadrian * RX path can be executed via various reset/channel change paths. 766238433Sadrian */ 767238433Sadrian#define ATH_RX_LOCK_INIT(_sc) do {\ 768238433Sadrian snprintf((_sc)->sc_rx_mtx_name, \ 769238433Sadrian sizeof((_sc)->sc_rx_mtx_name), \ 770238433Sadrian "%s RX lock", \ 771238433Sadrian device_get_nameunit((_sc)->sc_dev)); \ 772238433Sadrian mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 773238433Sadrian NULL, MTX_DEF); \ 774238433Sadrian } while (0) 775238433Sadrian#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 776238433Sadrian#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 777238433Sadrian#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 778238433Sadrian#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 779238433Sadrian MA_OWNED) 780238433Sadrian#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 781238433Sadrian MA_NOTOWNED) 782238433Sadrian 783138570Ssam#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 784138570Ssam 785155482Ssam#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 786155482Ssam snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 787155482Ssam device_get_nameunit((_sc)->sc_dev)); \ 788167252Ssam mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 789155482Ssam} while (0) 790121100Ssam#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 791121100Ssam#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 792121100Ssam#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 793121100Ssam#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 794121100Ssam mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 795121100Ssam 796238709Sadrian#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 797238709Sadrian snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 798238709Sadrian "%s_buf", \ 799238709Sadrian device_get_nameunit((_sc)->sc_dev)); \ 800238709Sadrian mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 801238709Sadrian MTX_DEF); \ 802238709Sadrian} while (0) 803238709Sadrian#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 804238709Sadrian#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 805238709Sadrian#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 806238709Sadrian#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 807238709Sadrian mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 808238709Sadrian 809116743Ssamint ath_attach(u_int16_t, struct ath_softc *); 810116743Ssamint ath_detach(struct ath_softc *); 811116743Ssamvoid ath_resume(struct ath_softc *); 812116743Ssamvoid ath_suspend(struct ath_softc *); 813116743Ssamvoid ath_shutdown(struct ath_softc *); 814116743Ssamvoid ath_intr(void *); 815116743Ssam 816116743Ssam/* 817116743Ssam * HAL definitions to comply with local coding convention. 818116743Ssam */ 819138570Ssam#define ath_hal_detach(_ah) \ 820138570Ssam ((*(_ah)->ah_detach)((_ah))) 821116743Ssam#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 822116743Ssam ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 823186904Ssam#define ath_hal_macversion(_ah) \ 824186904Ssam (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 825116743Ssam#define ath_hal_getratetable(_ah, _mode) \ 826116743Ssam ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 827116743Ssam#define ath_hal_getmac(_ah, _mac) \ 828116743Ssam ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 829138570Ssam#define ath_hal_setmac(_ah, _mac) \ 830138570Ssam ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 831178354Ssam#define ath_hal_getbssidmask(_ah, _mask) \ 832178354Ssam ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 833178354Ssam#define ath_hal_setbssidmask(_ah, _mask) \ 834178354Ssam ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 835116743Ssam#define ath_hal_intrset(_ah, _mask) \ 836116743Ssam ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 837116743Ssam#define ath_hal_intrget(_ah) \ 838116743Ssam ((*(_ah)->ah_getInterrupts)((_ah))) 839116743Ssam#define ath_hal_intrpend(_ah) \ 840116743Ssam ((*(_ah)->ah_isInterruptPending)((_ah))) 841116743Ssam#define ath_hal_getisr(_ah, _pmask) \ 842116743Ssam ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 843116743Ssam#define ath_hal_updatetxtriglevel(_ah, _inc) \ 844116743Ssam ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 845155515Ssam#define ath_hal_setpower(_ah, _mode) \ 846155515Ssam ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 847138570Ssam#define ath_hal_keycachesize(_ah) \ 848138570Ssam ((*(_ah)->ah_getKeyCacheSize)((_ah))) 849116743Ssam#define ath_hal_keyreset(_ah, _ix) \ 850116743Ssam ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 851138570Ssam#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 852138570Ssam ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 853116743Ssam#define ath_hal_keyisvalid(_ah, _ix) \ 854116743Ssam (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 855116743Ssam#define ath_hal_keysetmac(_ah, _ix, _mac) \ 856116743Ssam ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 857116743Ssam#define ath_hal_getrxfilter(_ah) \ 858116743Ssam ((*(_ah)->ah_getRxFilter)((_ah))) 859116743Ssam#define ath_hal_setrxfilter(_ah, _filter) \ 860116743Ssam ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 861116743Ssam#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 862116743Ssam ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 863116743Ssam#define ath_hal_waitforbeacon(_ah, _bf) \ 864116743Ssam ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 865238278Sadrian#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 866238278Sadrian ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 867186904Ssam/* NB: common across all chips */ 868186904Ssam#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 869116743Ssam#define ath_hal_gettsf32(_ah) \ 870186904Ssam OS_REG_READ(_ah, AR_TSF_L32) 871116743Ssam#define ath_hal_gettsf64(_ah) \ 872116743Ssam ((*(_ah)->ah_getTsf64)((_ah))) 873116743Ssam#define ath_hal_resettsf(_ah) \ 874116743Ssam ((*(_ah)->ah_resetTsf)((_ah))) 875116743Ssam#define ath_hal_rxena(_ah) \ 876116743Ssam ((*(_ah)->ah_enableReceive)((_ah))) 877116743Ssam#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 878116743Ssam ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 879116743Ssam#define ath_hal_gettxbuf(_ah, _q) \ 880116743Ssam ((*(_ah)->ah_getTxDP)((_ah), (_q))) 881138570Ssam#define ath_hal_numtxpending(_ah, _q) \ 882138570Ssam ((*(_ah)->ah_numTxPending)((_ah), (_q))) 883238278Sadrian#define ath_hal_getrxbuf(_ah, _rxq) \ 884238278Sadrian ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 885116743Ssam#define ath_hal_txstart(_ah, _q) \ 886116743Ssam ((*(_ah)->ah_startTxDma)((_ah), (_q))) 887116743Ssam#define ath_hal_setchannel(_ah, _chan) \ 888116743Ssam ((*(_ah)->ah_setChannel)((_ah), (_chan))) 889155515Ssam#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 890155515Ssam ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 891185744Ssam#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 892185744Ssam ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 893185744Ssam#define ath_hal_calreset(_ah, _chan) \ 894185744Ssam ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 895116743Ssam#define ath_hal_setledstate(_ah, _state) \ 896116743Ssam ((*(_ah)->ah_setLedState)((_ah), (_state))) 897138570Ssam#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 898138570Ssam ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 899116743Ssam#define ath_hal_beaconreset(_ah) \ 900116743Ssam ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 901186904Ssam#define ath_hal_beaconsettimers(_ah, _bt) \ 902186904Ssam ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 903138570Ssam#define ath_hal_beacontimers(_ah, _bs) \ 904138570Ssam ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 905225444Sadrian#define ath_hal_getnexttbtt(_ah) \ 906225444Sadrian ((*(_ah)->ah_getNextTBTT)((_ah))) 907116743Ssam#define ath_hal_setassocid(_ah, _bss, _associd) \ 908138570Ssam ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 909138570Ssam#define ath_hal_phydisable(_ah) \ 910138570Ssam ((*(_ah)->ah_phyDisable)((_ah))) 911138570Ssam#define ath_hal_setopmode(_ah) \ 912138570Ssam ((*(_ah)->ah_setPCUConfig)((_ah))) 913116743Ssam#define ath_hal_stoptxdma(_ah, _qnum) \ 914116743Ssam ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 915116743Ssam#define ath_hal_stoppcurecv(_ah) \ 916116743Ssam ((*(_ah)->ah_stopPcuReceive)((_ah))) 917116743Ssam#define ath_hal_startpcurecv(_ah) \ 918116743Ssam ((*(_ah)->ah_startPcuReceive)((_ah))) 919116743Ssam#define ath_hal_stopdmarecv(_ah) \ 920116743Ssam ((*(_ah)->ah_stopDmaReceive)((_ah))) 921138570Ssam#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 922138570Ssam ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 923138570Ssam (_indata), (_insize), (_outdata), (_outsize))) 924155732Ssam#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 925170530Ssam ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 926116743Ssam#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 927116743Ssam ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 928116743Ssam#define ath_hal_resettxqueue(_ah, _q) \ 929116743Ssam ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 930116743Ssam#define ath_hal_releasetxqueue(_ah, _q) \ 931116743Ssam ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 932138570Ssam#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 933138570Ssam ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 934138570Ssam#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 935138570Ssam ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 936186904Ssam/* NB: common across all chips */ 937186904Ssam#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 938186904Ssam#define ath_hal_txqenabled(_ah, _qnum) \ 939186904Ssam (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 940116743Ssam#define ath_hal_getrfgain(_ah) \ 941116743Ssam ((*(_ah)->ah_getRfGain)((_ah))) 942138570Ssam#define ath_hal_getdefantenna(_ah) \ 943138570Ssam ((*(_ah)->ah_getDefAntenna)((_ah))) 944138570Ssam#define ath_hal_setdefantenna(_ah, _ant) \ 945138570Ssam ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 946155515Ssam#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 947155515Ssam ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 948217684Sadrian#define ath_hal_ani_poll(_ah, _chan) \ 949217684Sadrian ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 950138570Ssam#define ath_hal_mibevent(_ah, _stats) \ 951138570Ssam ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 952138570Ssam#define ath_hal_setslottime(_ah, _us) \ 953138570Ssam ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 954138570Ssam#define ath_hal_getslottime(_ah) \ 955138570Ssam ((*(_ah)->ah_getSlotTime)((_ah))) 956138570Ssam#define ath_hal_setacktimeout(_ah, _us) \ 957138570Ssam ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 958138570Ssam#define ath_hal_getacktimeout(_ah) \ 959138570Ssam ((*(_ah)->ah_getAckTimeout)((_ah))) 960138570Ssam#define ath_hal_setctstimeout(_ah, _us) \ 961138570Ssam ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 962138570Ssam#define ath_hal_getctstimeout(_ah) \ 963138570Ssam ((*(_ah)->ah_getCTSTimeout)((_ah))) 964138570Ssam#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 965138570Ssam ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 966138570Ssam#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 967138570Ssam ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 968138570Ssam#define ath_hal_ciphersupported(_ah, _cipher) \ 969138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 970138570Ssam#define ath_hal_getregdomain(_ah, _prd) \ 971155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 972155489Ssam#define ath_hal_setregdomain(_ah, _rd) \ 973184369Ssam ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 974138570Ssam#define ath_hal_getcountrycode(_ah, _pcc) \ 975138570Ssam (*(_pcc) = (_ah)->ah_countryCode) 976178354Ssam#define ath_hal_gettkipmic(_ah) \ 977178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 978178354Ssam#define ath_hal_settkipmic(_ah, _v) \ 979178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 980162410Ssam#define ath_hal_hastkipsplit(_ah) \ 981138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 982162410Ssam#define ath_hal_gettkipsplit(_ah) \ 983162410Ssam (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 984162410Ssam#define ath_hal_settkipsplit(_ah, _v) \ 985162410Ssam ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 986178354Ssam#define ath_hal_haswmetkipmic(_ah) \ 987178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 988138570Ssam#define ath_hal_hwphycounters(_ah) \ 989138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 990138570Ssam#define ath_hal_hasdiversity(_ah) \ 991138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 992138570Ssam#define ath_hal_getdiversity(_ah) \ 993138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 994138570Ssam#define ath_hal_setdiversity(_ah, _v) \ 995138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 996166954Ssam#define ath_hal_getantennaswitch(_ah) \ 997166954Ssam ((*(_ah)->ah_getAntennaSwitch)((_ah))) 998166954Ssam#define ath_hal_setantennaswitch(_ah, _v) \ 999166954Ssam ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1000138570Ssam#define ath_hal_getdiag(_ah, _pv) \ 1001138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1002138570Ssam#define ath_hal_setdiag(_ah, _v) \ 1003138570Ssam ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1004138570Ssam#define ath_hal_getnumtxqueues(_ah, _pv) \ 1005138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1006138570Ssam#define ath_hal_hasveol(_ah) \ 1007138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1008138570Ssam#define ath_hal_hastxpowlimit(_ah) \ 1009138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1010138570Ssam#define ath_hal_settxpowlimit(_ah, _pow) \ 1011138570Ssam ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1012138570Ssam#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1013138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1014138570Ssam#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1015138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1016138570Ssam#define ath_hal_gettpscale(_ah, _scale) \ 1017138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1018138570Ssam#define ath_hal_settpscale(_ah, _v) \ 1019138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1020138570Ssam#define ath_hal_hastpc(_ah) \ 1021138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1022138570Ssam#define ath_hal_gettpc(_ah) \ 1023138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1024138570Ssam#define ath_hal_settpc(_ah, _v) \ 1025138570Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1026138570Ssam#define ath_hal_hasbursting(_ah) \ 1027138570Ssam (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1028203683Srpaulo#define ath_hal_setmcastkeysearch(_ah, _v) \ 1029203683Srpaulo ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1030147057Ssam#define ath_hal_hasmcastkeysearch(_ah) \ 1031147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1032147057Ssam#define ath_hal_getmcastkeysearch(_ah) \ 1033147057Ssam (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1034170530Ssam#define ath_hal_hasfastframes(_ah) \ 1035170530Ssam (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1036178354Ssam#define ath_hal_hasbssidmask(_ah) \ 1037178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1038195114Ssam#define ath_hal_hasbssidmatch(_ah) \ 1039195114Ssam (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1040178354Ssam#define ath_hal_hastsfadjust(_ah) \ 1041178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1042178354Ssam#define ath_hal_gettsfadjust(_ah) \ 1043178354Ssam (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1044178354Ssam#define ath_hal_settsfadjust(_ah, _onoff) \ 1045178354Ssam ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1046155515Ssam#define ath_hal_hasrfsilent(_ah) \ 1047155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1048155515Ssam#define ath_hal_getrfkill(_ah) \ 1049155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1050155515Ssam#define ath_hal_setrfkill(_ah, _onoff) \ 1051155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1052155515Ssam#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1053155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1054155515Ssam#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1055155515Ssam ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1056155515Ssam#define ath_hal_gettpack(_ah, _ptpack) \ 1057155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1058155515Ssam#define ath_hal_settpack(_ah, _tpack) \ 1059155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1060155515Ssam#define ath_hal_gettpcts(_ah, _ptpcts) \ 1061155515Ssam (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1062155515Ssam#define ath_hal_settpcts(_ah, _tpcts) \ 1063155515Ssam ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1064184354Ssam#define ath_hal_hasintmit(_ah) \ 1065230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1066230493Sadrian HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1067184354Ssam#define ath_hal_getintmit(_ah) \ 1068230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1069230493Sadrian HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1070184354Ssam#define ath_hal_setintmit(_ah, _v) \ 1071230493Sadrian ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1072230493Sadrian HAL_CAP_INTMIT_ENABLE, _v, NULL) 1073238280Sadrian 1074238280Sadrian/* EDMA definitions */ 1075237953Sadrian#define ath_hal_hasedma(_ah) \ 1076237953Sadrian (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1077237953Sadrian 0, NULL) == HAL_OK) 1078238280Sadrian#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1079238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1080238280Sadrian == HAL_OK) 1081238280Sadrian#define ath_hal_getntxmaps(_ah, _req) \ 1082238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1083238280Sadrian == HAL_OK) 1084238280Sadrian#define ath_hal_gettxdesclen(_ah, _req) \ 1085238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1086238280Sadrian == HAL_OK) 1087238280Sadrian#define ath_hal_gettxstatuslen(_ah, _req) \ 1088238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1089238280Sadrian == HAL_OK) 1090238280Sadrian#define ath_hal_getrxstatuslen(_ah, _req) \ 1091238280Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1092238280Sadrian == HAL_OK) 1093238280Sadrian#define ath_hal_setrxbufsize(_ah, _req) \ 1094238280Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1095238280Sadrian == HAL_OK) 1096238280Sadrian 1097154140Ssam#define ath_hal_getchannoise(_ah, _c) \ 1098154140Ssam ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1099238280Sadrian 1100238280Sadrian/* 802.11n HAL methods */ 1101218151Sadrian#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1102218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1103218151Sadrian#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1104218151Sadrian (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1105231369Sadrian#define ath_hal_setrxchainmask(_ah, _rx) \ 1106231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1107231369Sadrian#define ath_hal_settxchainmask(_ah, _tx) \ 1108231369Sadrian (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1109218490Sadrian#define ath_hal_split4ktrans(_ah) \ 1110230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1111230493Sadrian 0, NULL) == HAL_OK) 1112220324Sadrian#define ath_hal_self_linked_final_rxdesc(_ah) \ 1113230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1114230493Sadrian 0, NULL) == HAL_OK) 1115220772Sadrian#define ath_hal_gtxto_supported(_ah) \ 1116220772Sadrian (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1117225444Sadrian#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1118230493Sadrian (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1119230493Sadrian 0, NULL) == HAL_OK) 1120116743Ssam#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1121116743Ssam ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1122165185Ssam#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1123165185Ssam ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1124116743Ssam#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1125116743Ssam _txr0, _txtr0, _keyix, _ant, _flags, \ 1126116743Ssam _rtsrate, _rtsdura) \ 1127116743Ssam ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1128116743Ssam (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1129155515Ssam (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1130138570Ssam#define ath_hal_setupxtxdesc(_ah, _ds, \ 1131116743Ssam _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1132138570Ssam ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1133116743Ssam (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1134239051Sadrian#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1135239051Sadrian ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1136239051Sadrian (_first), (_last), (_ds0))) 1137165185Ssam#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1138165185Ssam ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1139155515Ssam#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1140155515Ssam ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1141217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1142217627Sadrian ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1143238607Sadrian#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1144238607Sadrian ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1145238607Sadrian#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1146238607Sadrian ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1147238607Sadrian#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1148238607Sadrian ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1149238731Sadrian#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1150238731Sadrian ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1151238731Sadrian (_size))) 1152116743Ssam 1153218066Sadrian#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1154218066Sadrian _txr0, _txtr0, _antm, _rcr, _rcd) \ 1155218066Sadrian ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1156218066Sadrian (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1157239053Sadrian#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1158239053Sadrian _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1159239053Sadrian ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1160239053Sadrian (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1161233895Sadrian (_first), (_last), (_lastaggr))) 1162218066Sadrian#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1163218066Sadrian ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1164227328Sadrian 1165218067Sadrian#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1166218066Sadrian ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1167218067Sadrian (_series), (_ns), (_flags))) 1168227328Sadrian 1169227328Sadrian#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1170238838Sadrian ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1171218066Sadrian#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1172227328Sadrian ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1173227328Sadrian#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1174227328Sadrian ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1175227328Sadrian 1176218066Sadrian#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1177218066Sadrian ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1178227328Sadrian#define ath_hal_clr11n_aggr(_ah, _ds) \ 1179227328Sadrian ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1180218066Sadrian 1181230493Sadrian#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1182230493Sadrian ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1183230493Sadrian#define ath_hal_gpioset(_ah, _gpio, _b) \ 1184230493Sadrian ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1185230493Sadrian#define ath_hal_gpioget(_ah, _gpio) \ 1186230493Sadrian ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1187230493Sadrian#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1188230493Sadrian ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1189230493Sadrian 1190222585Sadrian/* 1191235957Sadrian * PCIe suspend/resume/poweron/poweroff related macros 1192235957Sadrian */ 1193235972Sadrian#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1194235972Sadrian ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1195235957Sadrian#define ath_hal_disablepcie(_ah) \ 1196235957Sadrian ((*(_ah)->ah_disablePCIE)((_ah))) 1197235957Sadrian 1198235957Sadrian/* 1199222585Sadrian * This is badly-named; you need to set the correct parameters 1200222585Sadrian * to begin to receive useful radar events; and even then 1201222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1202222585Sadrian * more information. 1203222585Sadrian */ 1204222585Sadrian#define ath_hal_enabledfs(_ah, _param) \ 1205222585Sadrian ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1206222585Sadrian#define ath_hal_getdfsthresh(_ah, _param) \ 1207222585Sadrian ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1208239656Sadrian#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1209239656Sadrian ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1210222815Sadrian#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1211230493Sadrian ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1212230493Sadrian (_buf), (_event))) 1213224714Sadrian#define ath_hal_is_fast_clock_enabled(_ah) \ 1214224720Sadrian ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1215230493Sadrian#define ath_hal_radar_wait(_ah, _chan) \ 1216155515Ssam ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1217234873Sadrian#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1218234873Sadrian ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1219230493Sadrian#define ath_hal_get_chan_ext_busy(_ah) \ 1220230492Sadrian ((*(_ah)->ah_get11nExtBusy)((_ah))) 1221155515Ssam 1222116743Ssam#endif /* _DEV_ATH_ATHVAR_H */ 1223