if_athvar.h revision 241170
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 241170 2012-10-03 23:23:45Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * There is a separate TX ath_buf pool for management frames. 48 * This ensures that management frames such as probe responses 49 * and BAR frames can be transmitted during periods of high 50 * TX activity. 51 */ 52#define ATH_MGMT_TXBUF 32 53 54/* 55 * 802.11n requires more TX and RX buffers to do AMPDU. 56 */ 57#ifdef ATH_ENABLE_11N 58#define ATH_TXBUF 512 59#define ATH_RXBUF 512 60#endif 61 62#ifndef ATH_RXBUF 63#define ATH_RXBUF 40 /* number of RX buffers */ 64#endif 65#ifndef ATH_TXBUF 66#define ATH_TXBUF 200 /* number of TX buffers */ 67#endif 68#define ATH_BCBUF 4 /* number of beacon buffers */ 69 70#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74 75#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78 79/* 80 * The key cache is used for h/w cipher state and also for 81 * tracking station state such as the current tx antenna. 82 * We also setup a mapping table between key cache slot indices 83 * and station state to short-circuit node lookups on rx. 84 * Different parts have different size key caches. We handle 85 * up to ATH_KEYMAX entries (could dynamically allocate state). 86 */ 87#define ATH_KEYMAX 128 /* max key cache size we handle */ 88#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89 90struct taskqueue; 91struct kthread; 92struct ath_buf; 93 94#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95 96/* 97 * Per-TID state 98 * 99 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100 */ 101struct ath_tid { 102 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103 u_int axq_depth; /* SW queue depth */ 104 char axq_name[48]; /* lock name */ 105 struct ath_node *an; /* pointer to parent */ 106 int tid; /* tid */ 107 int ac; /* which AC gets this trafic */ 108 int hwq_depth; /* how many buffers are on HW */ 109 110 struct { 111 TAILQ_HEAD(,ath_buf) axq_q; /* filtered queue */ 112 u_int axq_depth; /* SW queue depth */ 113 char axq_name[48]; /* lock name */ 114 } filtq; 115 116 /* 117 * Entry on the ath_txq; when there's traffic 118 * to send 119 */ 120 TAILQ_ENTRY(ath_tid) axq_qelem; 121 int sched; 122 int paused; /* >0 if the TID has been paused */ 123 124 /* 125 * These are flags - perhaps later collapse 126 * down to a single uint32_t ? 127 */ 128 int addba_tx_pending; /* TX ADDBA pending */ 129 int bar_wait; /* waiting for BAR */ 130 int bar_tx; /* BAR TXed */ 131 int isfiltered; /* is this node currently filtered */ 132 int clrdmask; /* has clrdmask been set */ 133 134 /* 135 * Is the TID being cleaned up after a transition 136 * from aggregation to non-aggregation? 137 * When this is set to 1, this TID will be paused 138 * and no further traffic will be queued until all 139 * the hardware packets pending for this TID have been 140 * TXed/completed; at which point (non-aggregation) 141 * traffic will resume being TXed. 142 */ 143 int cleanup_inprogress; 144 /* 145 * How many hardware-queued packets are 146 * waiting to be cleaned up. 147 * This is only valid if cleanup_inprogress is 1. 148 */ 149 int incomp; 150 151 /* 152 * The following implements a ring representing 153 * the frames in the current BAW. 154 * To avoid copying the array content each time 155 * the BAW is moved, the baw_head/baw_tail point 156 * to the current BAW begin/end; when the BAW is 157 * shifted the head/tail of the array are also 158 * appropriately shifted. 159 */ 160 /* active tx buffers, beginning at current BAW */ 161 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 162 /* where the baw head is in the array */ 163 int baw_head; 164 /* where the BAW tail is in the array */ 165 int baw_tail; 166}; 167 168/* driver-specific node state */ 169struct ath_node { 170 struct ieee80211_node an_node; /* base class */ 171 u_int8_t an_mgmtrix; /* min h/w rate index */ 172 u_int8_t an_mcastrix; /* mcast h/w rate index */ 173 uint32_t an_is_powersave; /* node is sleeping */ 174 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 175 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 176 char an_name[32]; /* eg "wlan0_a1" */ 177 struct mtx an_mtx; /* protecting the ath_node state */ 178 /* variable-length rate control state follows */ 179}; 180#define ATH_NODE(ni) ((struct ath_node *)(ni)) 181#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 182 183#define ATH_RSSI_LPF_LEN 10 184#define ATH_RSSI_DUMMY_MARKER 0x127 185#define ATH_EP_MUL(x, mul) ((x) * (mul)) 186#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 187#define ATH_LPF_RSSI(x, y, len) \ 188 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 189#define ATH_RSSI_LPF(x, y) do { \ 190 if ((y) >= -20) \ 191 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 192} while (0) 193#define ATH_EP_RND(x,mul) \ 194 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 195#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 196 197typedef enum { 198 ATH_BUFTYPE_NORMAL = 0, 199 ATH_BUFTYPE_MGMT = 1, 200} ath_buf_type_t; 201 202struct ath_buf { 203 TAILQ_ENTRY(ath_buf) bf_list; 204 struct ath_buf * bf_next; /* next buffer in the aggregate */ 205 int bf_nseg; 206 HAL_STATUS bf_rxstatus; 207 uint16_t bf_flags; /* status flags (below) */ 208 uint16_t bf_descid; /* 16 bit descriptor ID */ 209 struct ath_desc *bf_desc; /* virtual addr of desc */ 210 struct ath_desc_status bf_status; /* tx/rx status */ 211 bus_addr_t bf_daddr; /* physical addr of desc */ 212 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 213 struct mbuf *bf_m; /* mbuf for buf */ 214 struct ieee80211_node *bf_node; /* pointer to the node */ 215 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 216 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 217 bus_size_t bf_mapsize; 218#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 219 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 220 221 /* Completion function to call on TX complete (fail or not) */ 222 /* 223 * "fail" here is set to 1 if the queue entries were removed 224 * through a call to ath_tx_draintxq(). 225 */ 226 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 227 228 /* This state is kept to support software retries and aggregation */ 229 struct { 230 uint16_t bfs_seqno; /* sequence number of this packet */ 231 uint16_t bfs_ndelim; /* number of delims for padding */ 232 233 uint8_t bfs_retries; /* retry count */ 234 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 235 uint8_t bfs_nframes; /* number of frames in aggregate */ 236 uint8_t bfs_pri; /* packet AC priority */ 237 238 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 239 240 u_int32_t bfs_aggr:1, /* part of aggregate? */ 241 bfs_aggrburst:1, /* part of aggregate burst? */ 242 bfs_isretried:1, /* retried frame? */ 243 bfs_dobaw:1, /* actually check against BAW? */ 244 bfs_addedbaw:1, /* has been added to the BAW */ 245 bfs_shpream:1, /* use short preamble */ 246 bfs_istxfrag:1, /* is fragmented */ 247 bfs_ismrr:1, /* do multi-rate TX retry */ 248 bfs_doprot:1, /* do RTS/CTS based protection */ 249 bfs_doratelookup:1; /* do rate lookup before each TX */ 250 251 /* 252 * These fields are passed into the 253 * descriptor setup functions. 254 */ 255 256 /* Make this an 8 bit value? */ 257 HAL_PKT_TYPE bfs_atype; /* packet type */ 258 259 uint32_t bfs_pktlen; /* length of this packet */ 260 261 uint16_t bfs_hdrlen; /* length of this packet header */ 262 uint16_t bfs_al; /* length of aggregate */ 263 264 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 265 uint8_t bfs_txrate0; /* first TX rate */ 266 uint8_t bfs_try0; /* first try count */ 267 268 uint16_t bfs_txpower; /* tx power */ 269 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 270 uint8_t bfs_ctsrate; /* CTS rate */ 271 272 /* 16 bit? */ 273 int32_t bfs_keyix; /* crypto key index */ 274 int32_t bfs_txantenna; /* TX antenna config */ 275 276 /* Make this an 8 bit value? */ 277 enum ieee80211_protmode bfs_protmode; 278 279 /* 16 bit? */ 280 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 281 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 282 } bf_state; 283}; 284typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 285 286#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 287#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 288 289/* 290 * DMA state for tx/rx descriptors. 291 */ 292struct ath_descdma { 293 const char* dd_name; 294 struct ath_desc *dd_desc; /* descriptors */ 295 int dd_descsize; /* size of single descriptor */ 296 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 297 bus_size_t dd_desc_len; /* size of dd_desc */ 298 bus_dma_segment_t dd_dseg; 299 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 300 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 301 struct ath_buf *dd_bufptr; /* associated buffers */ 302}; 303 304/* 305 * Data transmit queue state. One of these exists for each 306 * hardware transmit queue. Packets sent to us from above 307 * are assigned to queues based on their priority. Not all 308 * devices support a complete set of hardware transmit queues. 309 * For those devices the array sc_ac2q will map multiple 310 * priorities to fewer hardware queues (typically all to one 311 * hardware queue). 312 */ 313struct ath_txq { 314 struct ath_softc *axq_softc; /* Needed for scheduling */ 315 u_int axq_qnum; /* hardware q number */ 316#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 317 u_int axq_ac; /* WME AC */ 318 u_int axq_flags; 319#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 320 u_int axq_depth; /* queue depth (stat only) */ 321 u_int axq_aggr_depth; /* how many aggregates are queued */ 322 u_int axq_fifo_depth; /* depth of FIFO frames */ 323 u_int axq_intrcnt; /* interrupt count */ 324 u_int32_t *axq_link; /* link ptr in last TX desc */ 325 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 326 struct mtx axq_lock; /* lock on q and link */ 327 char axq_name[12]; /* e.g. "ath0_txq4" */ 328 329 /* Per-TID traffic queue for software -> hardware TX */ 330 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 331}; 332 333#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 334#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 335#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 336#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 337 MA_NOTOWNED) 338 339#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 340 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 341 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 342 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 343} while (0) 344#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 345#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 346#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 347#define ATH_TXQ_LOCK_ASSERT(_tq) \ 348 mtx_assert(&(_tq)->axq_lock, MA_OWNED) 349#define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 350 mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 351#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 352 353#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 354 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 355#define ATH_TID_UNLOCK_ASSERT(_sc, _tid) \ 356 ATH_TXQ_UNLOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 357 358#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 359 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 360 (_tq)->axq_depth++; \ 361} while (0) 362#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 363 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 364 (_tq)->axq_depth++; \ 365} while (0) 366#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 367 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 368 (_tq)->axq_depth--; \ 369} while (0) 370#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 371#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 372 373struct ath_vap { 374 struct ieee80211vap av_vap; /* base class */ 375 int av_bslot; /* beacon slot index */ 376 struct ath_buf *av_bcbuf; /* beacon buffer */ 377 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 378 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 379 380 void (*av_recv_mgmt)(struct ieee80211_node *, 381 struct mbuf *, int, int, int); 382 int (*av_newstate)(struct ieee80211vap *, 383 enum ieee80211_state, int); 384 void (*av_bmiss)(struct ieee80211vap *); 385 void (*av_node_ps)(struct ieee80211_node *, int); 386}; 387#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 388 389struct taskqueue; 390struct ath_tx99; 391 392/* 393 * Whether to reset the TX/RX queue with or without 394 * a queue flush. 395 */ 396typedef enum { 397 ATH_RESET_DEFAULT = 0, 398 ATH_RESET_NOLOSS = 1, 399 ATH_RESET_FULL = 2, 400} ATH_RESET_TYPE; 401 402struct ath_rx_methods { 403 void (*recv_stop)(struct ath_softc *sc, int dodelay); 404 int (*recv_start)(struct ath_softc *sc); 405 void (*recv_flush)(struct ath_softc *sc); 406 void (*recv_tasklet)(void *arg, int npending); 407 int (*recv_rxbuf_init)(struct ath_softc *sc, 408 struct ath_buf *bf); 409 int (*recv_setup)(struct ath_softc *sc); 410 int (*recv_teardown)(struct ath_softc *sc); 411}; 412 413/* 414 * Represent the current state of the RX FIFO. 415 */ 416struct ath_rx_edma { 417 struct ath_buf **m_fifo; 418 int m_fifolen; 419 int m_fifo_head; 420 int m_fifo_tail; 421 int m_fifo_depth; 422 struct mbuf *m_rxpending; 423}; 424 425struct ath_tx_edma_fifo { 426 struct ath_buf **m_fifo; 427 int m_fifolen; 428 int m_fifo_head; 429 int m_fifo_tail; 430 int m_fifo_depth; 431}; 432 433struct ath_tx_methods { 434 int (*xmit_setup)(struct ath_softc *sc); 435 int (*xmit_teardown)(struct ath_softc *sc); 436 void (*xmit_attach_comp_func)(struct ath_softc *sc); 437 438 void (*xmit_dma_restart)(struct ath_softc *sc, 439 struct ath_txq *txq); 440 void (*xmit_handoff)(struct ath_softc *sc, 441 struct ath_txq *txq, struct ath_buf *bf); 442 void (*xmit_drain)(struct ath_softc *sc, 443 ATH_RESET_TYPE reset_type); 444}; 445 446struct ath_softc { 447 struct ifnet *sc_ifp; /* interface common */ 448 struct ath_stats sc_stats; /* interface statistics */ 449 struct ath_tx_aggr_stats sc_aggr_stats; 450 struct ath_intr_stats sc_intr_stats; 451 uint64_t sc_debug; 452 uint64_t sc_ktrdebug; 453 int sc_nvaps; /* # vaps */ 454 int sc_nstavaps; /* # station vaps */ 455 int sc_nmeshvaps; /* # mbss vaps */ 456 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 457 u_int8_t sc_nbssid0; /* # vap's using base mac */ 458 uint32_t sc_bssidmask; /* bssid mask */ 459 460 struct ath_rx_methods sc_rx; 461 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 462 struct ath_tx_methods sc_tx; 463 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 464 465 int sc_rx_statuslen; 466 int sc_tx_desclen; 467 int sc_tx_statuslen; 468 int sc_tx_nmaps; /* Number of TX maps */ 469 int sc_edma_bufsize; 470 471 void (*sc_node_cleanup)(struct ieee80211_node *); 472 void (*sc_node_free)(struct ieee80211_node *); 473 device_t sc_dev; 474 HAL_BUS_TAG sc_st; /* bus space tag */ 475 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 476 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 477 struct mtx sc_mtx; /* master lock (recursive) */ 478 struct mtx sc_pcu_mtx; /* PCU access mutex */ 479 char sc_pcu_mtx_name[32]; 480 struct mtx sc_rx_mtx; /* RX access mutex */ 481 char sc_rx_mtx_name[32]; 482 struct taskqueue *sc_tq; /* private task queue */ 483 struct ath_hal *sc_ah; /* Atheros HAL */ 484 struct ath_ratectrl *sc_rc; /* tx rate control support */ 485 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 486 void (*sc_setdefantenna)(struct ath_softc *, u_int); 487 unsigned int sc_invalid : 1,/* disable hardware accesses */ 488 sc_mrretry : 1,/* multi-rate retry support */ 489 sc_mrrprot : 1,/* MRR + protection support */ 490 sc_softled : 1,/* enable LED gpio status */ 491 sc_hardled : 1,/* enable MAC LED status */ 492 sc_splitmic : 1,/* split TKIP MIC keys */ 493 sc_needmib : 1,/* enable MIB stats intr */ 494 sc_diversity: 1,/* enable rx diversity */ 495 sc_hasveol : 1,/* tx VEOL support */ 496 sc_ledstate : 1,/* LED on/off state */ 497 sc_blinking : 1,/* LED blink operation active */ 498 sc_mcastkey : 1,/* mcast key cache search */ 499 sc_scanning : 1,/* scanning active */ 500 sc_syncbeacon:1,/* sync/resync beacon timers */ 501 sc_hasclrkey: 1,/* CLR key supported */ 502 sc_xchanmode: 1,/* extended channel mode */ 503 sc_outdoor : 1,/* outdoor operation */ 504 sc_dturbo : 1,/* dynamic turbo in use */ 505 sc_hasbmask : 1,/* bssid mask support */ 506 sc_hasbmatch: 1,/* bssid match disable support*/ 507 sc_hastsfadd: 1,/* tsf adjust support */ 508 sc_beacons : 1,/* beacons running */ 509 sc_swbmiss : 1,/* sta mode using sw bmiss */ 510 sc_stagbeacons:1,/* use staggered beacons */ 511 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 512 sc_resume_up: 1,/* on resume, start all vaps */ 513 sc_tdma : 1,/* TDMA in use */ 514 sc_setcca : 1,/* set/clr CCA with TDMA */ 515 sc_resetcal : 1,/* reset cal state next trip */ 516 sc_rxslink : 1,/* do self-linked final descriptor */ 517 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 518 sc_isedma : 1;/* supports EDMA */ 519 uint32_t sc_eerd; /* regdomain from EEPROM */ 520 uint32_t sc_eecc; /* country code from EEPROM */ 521 /* rate tables */ 522 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 523 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 524 enum ieee80211_phymode sc_curmode; /* current phy mode */ 525 HAL_OPMODE sc_opmode; /* current operating mode */ 526 u_int16_t sc_curtxpow; /* current tx power limit */ 527 u_int16_t sc_curaid; /* current association id */ 528 struct ieee80211_channel *sc_curchan; /* current installed channel */ 529 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 530 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 531 struct { 532 u_int8_t ieeerate; /* IEEE rate */ 533 u_int8_t rxflags; /* radiotap rx flags */ 534 u_int8_t txflags; /* radiotap tx flags */ 535 u_int16_t ledon; /* softled on time */ 536 u_int16_t ledoff; /* softled off time */ 537 } sc_hwmap[32]; /* h/w rate ix mappings */ 538 u_int8_t sc_protrix; /* protection rate index */ 539 u_int8_t sc_lastdatarix; /* last data frame rate index */ 540 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 541 u_int sc_fftxqmin; /* min frames before staging */ 542 u_int sc_fftxqmax; /* max frames before drop */ 543 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 544 545 HAL_INT sc_imask; /* interrupt mask copy */ 546 547 /* 548 * These are modified in the interrupt handler as well as 549 * the task queues and other contexts. Thus these must be 550 * protected by a mutex, or they could clash. 551 * 552 * For now, access to these is behind the ATH_LOCK, 553 * just to save time. 554 */ 555 uint32_t sc_txq_active; /* bitmap of active TXQs */ 556 uint32_t sc_kickpcu; /* whether to kick the PCU */ 557 uint32_t sc_rxproc_cnt; /* In RX processing */ 558 uint32_t sc_txproc_cnt; /* In TX processing */ 559 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 560 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 561 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 562 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 563 564 u_int sc_keymax; /* size of key cache */ 565 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 566 567 /* 568 * Software based LED blinking 569 */ 570 u_int sc_ledpin; /* GPIO pin for driving LED */ 571 u_int sc_ledon; /* pin setting for LED on */ 572 u_int sc_ledidle; /* idle polling interval */ 573 int sc_ledevent; /* time of last LED event */ 574 u_int8_t sc_txrix; /* current tx rate for LED */ 575 u_int16_t sc_ledoff; /* off time for current blink */ 576 struct callout sc_ledtimer; /* led off timer */ 577 578 /* 579 * Hardware based LED blinking 580 */ 581 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 582 int sc_led_net_pin; /* MAC network LED GPIO pin */ 583 584 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 585 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 586 587 struct ath_descdma sc_rxdma; /* RX descriptors */ 588 ath_bufhead sc_rxbuf; /* receive buffer */ 589 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 590 struct task sc_rxtask; /* rx int processing */ 591 u_int8_t sc_defant; /* current default antenna */ 592 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 593 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 594 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 595 struct ath_rx_radiotap_header sc_rx_th; 596 int sc_rx_th_len; 597 u_int sc_monpass; /* frames to pass in mon.mode */ 598 599 struct ath_descdma sc_txdma; /* TX descriptors */ 600 uint16_t sc_txbuf_descid; 601 ath_bufhead sc_txbuf; /* transmit buffer */ 602 int sc_txbuf_cnt; /* how many buffers avail */ 603 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 604 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 605 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 606 struct mtx sc_txbuflock; /* txbuf lock */ 607 char sc_txname[12]; /* e.g. "ath0_buf" */ 608 u_int sc_txqsetup; /* h/w queues setup */ 609 u_int sc_txintrperiod;/* tx interrupt batching */ 610 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 611 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 612 struct task sc_txtask; /* tx int processing */ 613 struct task sc_txqtask; /* tx proc processing */ 614 615 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 616 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 617 char sc_txcompname[12]; /* eg ath0_txcomp */ 618 619 int sc_wd_timer; /* count down for wd timer */ 620 struct callout sc_wd_ch; /* tx watchdog timer */ 621 struct ath_tx_radiotap_header sc_tx_th; 622 int sc_tx_th_len; 623 624 struct ath_descdma sc_bdma; /* beacon descriptors */ 625 ath_bufhead sc_bbuf; /* beacon buffers */ 626 u_int sc_bhalq; /* HAL q for outgoing beacons */ 627 u_int sc_bmisscount; /* missed beacon transmits */ 628 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 629 struct ath_txq *sc_cabq; /* tx q for cab frames */ 630 struct task sc_bmisstask; /* bmiss int processing */ 631 struct task sc_bstucktask; /* stuck beacon processing */ 632 struct task sc_resettask; /* interface reset task */ 633 struct task sc_fataltask; /* fatal task */ 634 enum { 635 OK, /* no change needed */ 636 UPDATE, /* update pending */ 637 COMMIT /* beacon sent, commit change */ 638 } sc_updateslot; /* slot time update fsm */ 639 int sc_slotupdate; /* slot to advance fsm */ 640 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 641 int sc_nbcnvaps; /* # vaps with beacons */ 642 643 struct callout sc_cal_ch; /* callout handle for cals */ 644 int sc_lastlongcal; /* last long cal completed */ 645 int sc_lastcalreset;/* last cal reset done */ 646 int sc_lastani; /* last ANI poll */ 647 int sc_lastshortcal; /* last short calibration */ 648 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 649 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 650 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 651 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 652 u_int sc_tdmaswba; /* TDMA SWBA counter */ 653 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 654 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 655 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 656 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 657 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 658 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 659 int sc_txchainmask; /* currently configured TX chainmask */ 660 int sc_rxchainmask; /* currently configured RX chainmask */ 661 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 662 663 /* Queue limits */ 664 665 /* 666 * To avoid queue starvation in congested conditions, 667 * these parameters tune the maximum number of frames 668 * queued to the data/mcastq before they're dropped. 669 * 670 * This is to prevent: 671 * + a single destination overwhelming everything, including 672 * management/multicast frames; 673 * + multicast frames overwhelming everything (when the 674 * air is sufficiently busy that cabq can't drain.) 675 * 676 * These implement: 677 * + data_minfree is the maximum number of free buffers 678 * overall to successfully allow a data frame. 679 * 680 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 681 */ 682 int sc_txq_data_minfree; 683 int sc_txq_mcastq_maxdepth; 684 685 /* 686 * Aggregation twiddles 687 * 688 * hwq_limit: how busy to keep the hardware queue - don't schedule 689 * further packets to the hardware, regardless of the TID 690 * tid_hwq_lo: how low the per-TID hwq count has to be before the 691 * TID will be scheduled again 692 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 693 * stops being scheduled. 694 */ 695 int sc_hwq_limit; 696 int sc_tid_hwq_lo; 697 int sc_tid_hwq_hi; 698 699 /* DFS related state */ 700 void *sc_dfs; /* Used by an optional DFS module */ 701 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 702 struct task sc_dfstask; /* DFS processing task */ 703 704 /* TX AMPDU handling */ 705 int (*sc_addba_request)(struct ieee80211_node *, 706 struct ieee80211_tx_ampdu *, int, int, int); 707 int (*sc_addba_response)(struct ieee80211_node *, 708 struct ieee80211_tx_ampdu *, int, int, int); 709 void (*sc_addba_stop)(struct ieee80211_node *, 710 struct ieee80211_tx_ampdu *); 711 void (*sc_addba_response_timeout) 712 (struct ieee80211_node *, 713 struct ieee80211_tx_ampdu *); 714 void (*sc_bar_response)(struct ieee80211_node *ni, 715 struct ieee80211_tx_ampdu *tap, 716 int status); 717}; 718 719#define ATH_LOCK_INIT(_sc) \ 720 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 721 NULL, MTX_DEF | MTX_RECURSE) 722#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 723#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 724#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 725#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 726#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 727 728/* 729 * The PCU lock is non-recursive and should be treated as a spinlock. 730 * Although currently the interrupt code is run in netisr context and 731 * doesn't require this, this may change in the future. 732 * Please keep this in mind when protecting certain code paths 733 * with the PCU lock. 734 * 735 * The PCU lock is used to serialise access to the PCU so things such 736 * as TX, RX, state change (eg channel change), channel reset and updates 737 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 738 * 739 * Although the current single-thread taskqueue mechanism protects the 740 * majority of these situations by simply serialising them, there are 741 * a few others which occur at the same time. These include the TX path 742 * (which only acquires ATH_LOCK when recycling buffers to the free list), 743 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 744 */ 745#define ATH_PCU_LOCK_INIT(_sc) do {\ 746 snprintf((_sc)->sc_pcu_mtx_name, \ 747 sizeof((_sc)->sc_pcu_mtx_name), \ 748 "%s PCU lock", \ 749 device_get_nameunit((_sc)->sc_dev)); \ 750 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 751 NULL, MTX_DEF); \ 752 } while (0) 753#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 754#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 755#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 756#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 757 MA_OWNED) 758#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 759 MA_NOTOWNED) 760 761/* 762 * The RX lock is primarily a(nother) workaround to ensure that the 763 * RX FIFO/list isn't modified by various execution paths. 764 * Even though RX occurs in a single context (the ath taskqueue), the 765 * RX path can be executed via various reset/channel change paths. 766 */ 767#define ATH_RX_LOCK_INIT(_sc) do {\ 768 snprintf((_sc)->sc_rx_mtx_name, \ 769 sizeof((_sc)->sc_rx_mtx_name), \ 770 "%s RX lock", \ 771 device_get_nameunit((_sc)->sc_dev)); \ 772 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 773 NULL, MTX_DEF); \ 774 } while (0) 775#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 776#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 777#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 778#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 779 MA_OWNED) 780#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 781 MA_NOTOWNED) 782 783#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 784 785#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 786 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 787 device_get_nameunit((_sc)->sc_dev)); \ 788 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 789} while (0) 790#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 791#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 792#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 793#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 794 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 795 796#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 797 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 798 "%s_buf", \ 799 device_get_nameunit((_sc)->sc_dev)); \ 800 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 801 MTX_DEF); \ 802} while (0) 803#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 804#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 805#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 806#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 807 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 808 809int ath_attach(u_int16_t, struct ath_softc *); 810int ath_detach(struct ath_softc *); 811void ath_resume(struct ath_softc *); 812void ath_suspend(struct ath_softc *); 813void ath_shutdown(struct ath_softc *); 814void ath_intr(void *); 815 816/* 817 * HAL definitions to comply with local coding convention. 818 */ 819#define ath_hal_detach(_ah) \ 820 ((*(_ah)->ah_detach)((_ah))) 821#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 822 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 823#define ath_hal_macversion(_ah) \ 824 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 825#define ath_hal_getratetable(_ah, _mode) \ 826 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 827#define ath_hal_getmac(_ah, _mac) \ 828 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 829#define ath_hal_setmac(_ah, _mac) \ 830 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 831#define ath_hal_getbssidmask(_ah, _mask) \ 832 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 833#define ath_hal_setbssidmask(_ah, _mask) \ 834 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 835#define ath_hal_intrset(_ah, _mask) \ 836 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 837#define ath_hal_intrget(_ah) \ 838 ((*(_ah)->ah_getInterrupts)((_ah))) 839#define ath_hal_intrpend(_ah) \ 840 ((*(_ah)->ah_isInterruptPending)((_ah))) 841#define ath_hal_getisr(_ah, _pmask) \ 842 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 843#define ath_hal_updatetxtriglevel(_ah, _inc) \ 844 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 845#define ath_hal_setpower(_ah, _mode) \ 846 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 847#define ath_hal_keycachesize(_ah) \ 848 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 849#define ath_hal_keyreset(_ah, _ix) \ 850 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 851#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 852 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 853#define ath_hal_keyisvalid(_ah, _ix) \ 854 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 855#define ath_hal_keysetmac(_ah, _ix, _mac) \ 856 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 857#define ath_hal_getrxfilter(_ah) \ 858 ((*(_ah)->ah_getRxFilter)((_ah))) 859#define ath_hal_setrxfilter(_ah, _filter) \ 860 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 861#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 862 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 863#define ath_hal_waitforbeacon(_ah, _bf) \ 864 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 865#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 866 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 867/* NB: common across all chips */ 868#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 869#define ath_hal_gettsf32(_ah) \ 870 OS_REG_READ(_ah, AR_TSF_L32) 871#define ath_hal_gettsf64(_ah) \ 872 ((*(_ah)->ah_getTsf64)((_ah))) 873#define ath_hal_resettsf(_ah) \ 874 ((*(_ah)->ah_resetTsf)((_ah))) 875#define ath_hal_rxena(_ah) \ 876 ((*(_ah)->ah_enableReceive)((_ah))) 877#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 878 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 879#define ath_hal_gettxbuf(_ah, _q) \ 880 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 881#define ath_hal_numtxpending(_ah, _q) \ 882 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 883#define ath_hal_getrxbuf(_ah, _rxq) \ 884 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 885#define ath_hal_txstart(_ah, _q) \ 886 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 887#define ath_hal_setchannel(_ah, _chan) \ 888 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 889#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 890 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 891#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 892 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 893#define ath_hal_calreset(_ah, _chan) \ 894 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 895#define ath_hal_setledstate(_ah, _state) \ 896 ((*(_ah)->ah_setLedState)((_ah), (_state))) 897#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 898 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 899#define ath_hal_beaconreset(_ah) \ 900 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 901#define ath_hal_beaconsettimers(_ah, _bt) \ 902 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 903#define ath_hal_beacontimers(_ah, _bs) \ 904 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 905#define ath_hal_getnexttbtt(_ah) \ 906 ((*(_ah)->ah_getNextTBTT)((_ah))) 907#define ath_hal_setassocid(_ah, _bss, _associd) \ 908 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 909#define ath_hal_phydisable(_ah) \ 910 ((*(_ah)->ah_phyDisable)((_ah))) 911#define ath_hal_setopmode(_ah) \ 912 ((*(_ah)->ah_setPCUConfig)((_ah))) 913#define ath_hal_stoptxdma(_ah, _qnum) \ 914 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 915#define ath_hal_stoppcurecv(_ah) \ 916 ((*(_ah)->ah_stopPcuReceive)((_ah))) 917#define ath_hal_startpcurecv(_ah) \ 918 ((*(_ah)->ah_startPcuReceive)((_ah))) 919#define ath_hal_stopdmarecv(_ah) \ 920 ((*(_ah)->ah_stopDmaReceive)((_ah))) 921#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 922 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 923 (_indata), (_insize), (_outdata), (_outsize))) 924#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 925 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 926#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 927 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 928#define ath_hal_resettxqueue(_ah, _q) \ 929 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 930#define ath_hal_releasetxqueue(_ah, _q) \ 931 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 932#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 933 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 934#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 935 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 936/* NB: common across all chips */ 937#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 938#define ath_hal_txqenabled(_ah, _qnum) \ 939 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 940#define ath_hal_getrfgain(_ah) \ 941 ((*(_ah)->ah_getRfGain)((_ah))) 942#define ath_hal_getdefantenna(_ah) \ 943 ((*(_ah)->ah_getDefAntenna)((_ah))) 944#define ath_hal_setdefantenna(_ah, _ant) \ 945 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 946#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 947 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 948#define ath_hal_ani_poll(_ah, _chan) \ 949 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 950#define ath_hal_mibevent(_ah, _stats) \ 951 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 952#define ath_hal_setslottime(_ah, _us) \ 953 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 954#define ath_hal_getslottime(_ah) \ 955 ((*(_ah)->ah_getSlotTime)((_ah))) 956#define ath_hal_setacktimeout(_ah, _us) \ 957 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 958#define ath_hal_getacktimeout(_ah) \ 959 ((*(_ah)->ah_getAckTimeout)((_ah))) 960#define ath_hal_setctstimeout(_ah, _us) \ 961 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 962#define ath_hal_getctstimeout(_ah) \ 963 ((*(_ah)->ah_getCTSTimeout)((_ah))) 964#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 965 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 966#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 967 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 968#define ath_hal_ciphersupported(_ah, _cipher) \ 969 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 970#define ath_hal_getregdomain(_ah, _prd) \ 971 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 972#define ath_hal_setregdomain(_ah, _rd) \ 973 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 974#define ath_hal_getcountrycode(_ah, _pcc) \ 975 (*(_pcc) = (_ah)->ah_countryCode) 976#define ath_hal_gettkipmic(_ah) \ 977 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 978#define ath_hal_settkipmic(_ah, _v) \ 979 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 980#define ath_hal_hastkipsplit(_ah) \ 981 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 982#define ath_hal_gettkipsplit(_ah) \ 983 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 984#define ath_hal_settkipsplit(_ah, _v) \ 985 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 986#define ath_hal_haswmetkipmic(_ah) \ 987 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 988#define ath_hal_hwphycounters(_ah) \ 989 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 990#define ath_hal_hasdiversity(_ah) \ 991 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 992#define ath_hal_getdiversity(_ah) \ 993 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 994#define ath_hal_setdiversity(_ah, _v) \ 995 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 996#define ath_hal_getantennaswitch(_ah) \ 997 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 998#define ath_hal_setantennaswitch(_ah, _v) \ 999 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1000#define ath_hal_getdiag(_ah, _pv) \ 1001 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1002#define ath_hal_setdiag(_ah, _v) \ 1003 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1004#define ath_hal_getnumtxqueues(_ah, _pv) \ 1005 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1006#define ath_hal_hasveol(_ah) \ 1007 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1008#define ath_hal_hastxpowlimit(_ah) \ 1009 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1010#define ath_hal_settxpowlimit(_ah, _pow) \ 1011 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1012#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1013 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1014#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1015 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1016#define ath_hal_gettpscale(_ah, _scale) \ 1017 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1018#define ath_hal_settpscale(_ah, _v) \ 1019 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1020#define ath_hal_hastpc(_ah) \ 1021 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1022#define ath_hal_gettpc(_ah) \ 1023 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1024#define ath_hal_settpc(_ah, _v) \ 1025 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1026#define ath_hal_hasbursting(_ah) \ 1027 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1028#define ath_hal_setmcastkeysearch(_ah, _v) \ 1029 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1030#define ath_hal_hasmcastkeysearch(_ah) \ 1031 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1032#define ath_hal_getmcastkeysearch(_ah) \ 1033 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1034#define ath_hal_hasfastframes(_ah) \ 1035 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1036#define ath_hal_hasbssidmask(_ah) \ 1037 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1038#define ath_hal_hasbssidmatch(_ah) \ 1039 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1040#define ath_hal_hastsfadjust(_ah) \ 1041 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1042#define ath_hal_gettsfadjust(_ah) \ 1043 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1044#define ath_hal_settsfadjust(_ah, _onoff) \ 1045 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1046#define ath_hal_hasrfsilent(_ah) \ 1047 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1048#define ath_hal_getrfkill(_ah) \ 1049 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1050#define ath_hal_setrfkill(_ah, _onoff) \ 1051 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1052#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1053 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1054#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1055 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1056#define ath_hal_gettpack(_ah, _ptpack) \ 1057 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1058#define ath_hal_settpack(_ah, _tpack) \ 1059 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1060#define ath_hal_gettpcts(_ah, _ptpcts) \ 1061 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1062#define ath_hal_settpcts(_ah, _tpcts) \ 1063 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1064#define ath_hal_hasintmit(_ah) \ 1065 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1066 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1067#define ath_hal_getintmit(_ah) \ 1068 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1069 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1070#define ath_hal_setintmit(_ah, _v) \ 1071 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1072 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1073 1074/* EDMA definitions */ 1075#define ath_hal_hasedma(_ah) \ 1076 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1077 0, NULL) == HAL_OK) 1078#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1079 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1080 == HAL_OK) 1081#define ath_hal_getntxmaps(_ah, _req) \ 1082 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1083 == HAL_OK) 1084#define ath_hal_gettxdesclen(_ah, _req) \ 1085 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1086 == HAL_OK) 1087#define ath_hal_gettxstatuslen(_ah, _req) \ 1088 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1089 == HAL_OK) 1090#define ath_hal_getrxstatuslen(_ah, _req) \ 1091 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1092 == HAL_OK) 1093#define ath_hal_setrxbufsize(_ah, _req) \ 1094 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1095 == HAL_OK) 1096 1097#define ath_hal_getchannoise(_ah, _c) \ 1098 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1099 1100/* 802.11n HAL methods */ 1101#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1102 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1103#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1104 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1105#define ath_hal_setrxchainmask(_ah, _rx) \ 1106 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1107#define ath_hal_settxchainmask(_ah, _tx) \ 1108 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1109#define ath_hal_split4ktrans(_ah) \ 1110 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1111 0, NULL) == HAL_OK) 1112#define ath_hal_self_linked_final_rxdesc(_ah) \ 1113 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1114 0, NULL) == HAL_OK) 1115#define ath_hal_gtxto_supported(_ah) \ 1116 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1117#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1118 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1119 0, NULL) == HAL_OK) 1120#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1121 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1122#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1123 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1124#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1125 _txr0, _txtr0, _keyix, _ant, _flags, \ 1126 _rtsrate, _rtsdura) \ 1127 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1128 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1129 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1130#define ath_hal_setupxtxdesc(_ah, _ds, \ 1131 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1132 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1133 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1134#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1135 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1136 (_first), (_last), (_ds0))) 1137#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1138 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1139#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1140 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1141#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1142 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1143#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1144 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1145#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1146 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1147#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1148 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1149#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1150 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1151 (_size))) 1152 1153#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1154 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1155 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1156 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1157#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1158 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1159 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1160 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1161 (_first), (_last), (_lastaggr))) 1162#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1163 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1164 1165#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1166 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1167 (_series), (_ns), (_flags))) 1168 1169#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1170 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1171#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1172 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1173#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1174 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1175 1176#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1177 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1178#define ath_hal_clr11n_aggr(_ah, _ds) \ 1179 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1180 1181#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1182 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1183#define ath_hal_gpioset(_ah, _gpio, _b) \ 1184 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1185#define ath_hal_gpioget(_ah, _gpio) \ 1186 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1187#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1188 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1189 1190/* 1191 * PCIe suspend/resume/poweron/poweroff related macros 1192 */ 1193#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1194 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1195#define ath_hal_disablepcie(_ah) \ 1196 ((*(_ah)->ah_disablePCIE)((_ah))) 1197 1198/* 1199 * This is badly-named; you need to set the correct parameters 1200 * to begin to receive useful radar events; and even then 1201 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1202 * more information. 1203 */ 1204#define ath_hal_enabledfs(_ah, _param) \ 1205 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1206#define ath_hal_getdfsthresh(_ah, _param) \ 1207 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1208#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1209 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1210#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1211 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1212 (_buf), (_event))) 1213#define ath_hal_is_fast_clock_enabled(_ah) \ 1214 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1215#define ath_hal_radar_wait(_ah, _chan) \ 1216 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1217#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1218 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1219#define ath_hal_get_chan_ext_busy(_ah) \ 1220 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1221 1222#endif /* _DEV_ATH_ATHVAR_H */ 1223