1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <machine/atomic.h> 39 40#include <dev/ath/ath_hal/ah.h> 41#include <dev/ath/ath_hal/ah_desc.h> 42#include <net80211/ieee80211_radiotap.h> 43#include <dev/ath/if_athioctl.h> 44#include <dev/ath/if_athrate.h> 45#ifdef ATH_DEBUG_ALQ 46#include <dev/ath/if_ath_alq.h> 47#endif 48 49#define ATH_TIMEOUT 1000 50 51/* 52 * There is a separate TX ath_buf pool for management frames. 53 * This ensures that management frames such as probe responses 54 * and BAR frames can be transmitted during periods of high 55 * TX activity. 56 */ 57#define ATH_MGMT_TXBUF 32 58 59/* 60 * 802.11n requires more TX and RX buffers to do AMPDU. 61 */ 62#ifdef ATH_ENABLE_11N 63#define ATH_TXBUF 512 64#define ATH_RXBUF 512 65#endif 66 67#ifndef ATH_RXBUF 68#define ATH_RXBUF 40 /* number of RX buffers */ 69#endif 70#ifndef ATH_TXBUF 71#define ATH_TXBUF 200 /* number of TX buffers */ 72#endif 73#define ATH_BCBUF 4 /* number of beacon buffers */ 74 75#define ATH_TXDESC 10 /* number of descriptors per buffer */ 76#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 77#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 78#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 79 80#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 81#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 82#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 83 84/* 85 * The following bits can be set during the PCI (and perhaps non-PCI 86 * later) device probe path. 87 * 88 * It controls some of the driver and HAL behaviour. 89 */ 90 91#define ATH_PCI_CUS198 0x0001 92#define ATH_PCI_CUS230 0x0002 93#define ATH_PCI_CUS217 0x0004 94#define ATH_PCI_CUS252 0x0008 95#define ATH_PCI_WOW 0x0010 96#define ATH_PCI_BT_ANT_DIV 0x0020 97#define ATH_PCI_D3_L1_WAR 0x0040 98#define ATH_PCI_AR9565_1ANT 0x0080 99#define ATH_PCI_AR9565_2ANT 0x0100 100#define ATH_PCI_NO_PLL_PWRSAVE 0x0200 101#define ATH_PCI_KILLER 0x0400 102 103/* 104 * The key cache is used for h/w cipher state and also for 105 * tracking station state such as the current tx antenna. 106 * We also setup a mapping table between key cache slot indices 107 * and station state to short-circuit node lookups on rx. 108 * Different parts have different size key caches. We handle 109 * up to ATH_KEYMAX entries (could dynamically allocate state). 110 */ 111#define ATH_KEYMAX 128 /* max key cache size we handle */ 112#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 113 114struct taskqueue; 115struct kthread; 116struct ath_buf; 117 118#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 119 120/* 121 * Per-TID state 122 * 123 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 124 */ 125struct ath_tid { 126 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 127 struct ath_node *an; /* pointer to parent */ 128 int tid; /* tid */ 129 int ac; /* which AC gets this traffic */ 130 int hwq_depth; /* how many buffers are on HW */ 131 u_int axq_depth; /* SW queue depth */ 132 133 struct { 134 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 135 u_int axq_depth; /* SW queue depth */ 136 } filtq; 137 138 /* 139 * Entry on the ath_txq; when there's traffic 140 * to send 141 */ 142 TAILQ_ENTRY(ath_tid) axq_qelem; 143 int sched; 144 int paused; /* >0 if the TID has been paused */ 145 146 /* 147 * These are flags - perhaps later collapse 148 * down to a single uint32_t ? 149 */ 150 int addba_tx_pending; /* TX ADDBA pending */ 151 int bar_wait; /* waiting for BAR */ 152 int bar_tx; /* BAR TXed */ 153 int isfiltered; /* is this node currently filtered */ 154 155 /* 156 * Is the TID being cleaned up after a transition 157 * from aggregation to non-aggregation? 158 * When this is set to 1, this TID will be paused 159 * and no further traffic will be queued until all 160 * the hardware packets pending for this TID have been 161 * TXed/completed; at which point (non-aggregation) 162 * traffic will resume being TXed. 163 */ 164 int cleanup_inprogress; 165 /* 166 * How many hardware-queued packets are 167 * waiting to be cleaned up. 168 * This is only valid if cleanup_inprogress is 1. 169 */ 170 int incomp; 171 172 /* 173 * The following implements a ring representing 174 * the frames in the current BAW. 175 * To avoid copying the array content each time 176 * the BAW is moved, the baw_head/baw_tail point 177 * to the current BAW begin/end; when the BAW is 178 * shifted the head/tail of the array are also 179 * appropriately shifted. 180 */ 181 /* active tx buffers, beginning at current BAW */ 182 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 183 /* where the baw head is in the array */ 184 int baw_head; 185 /* where the BAW tail is in the array */ 186 int baw_tail; 187}; 188 189/* driver-specific node state */ 190struct ath_node { 191 struct ieee80211_node an_node; /* base class */ 192 u_int8_t an_mgmtrix; /* min h/w rate index */ 193 u_int8_t an_mcastrix; /* mcast h/w rate index */ 194 uint32_t an_is_powersave; /* node is sleeping */ 195 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 196 uint32_t an_tim_set; /* TIM has been set */ 197 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 198 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 199 char an_name[32]; /* eg "wlan0_a1" */ 200 struct mtx an_mtx; /* protecting the rate control state */ 201 uint32_t an_swq_depth; /* how many SWQ packets for this 202 node */ 203 int clrdmask; /* has clrdmask been set */ 204 uint32_t an_leak_count; /* How many frames to leak during pause */ 205 /* variable-length rate control state follows */ 206}; 207#define ATH_NODE(ni) ((struct ath_node *)(ni)) 208#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 209 210#define ATH_RSSI_LPF_LEN 10 211#define ATH_RSSI_DUMMY_MARKER 0x127 212#define ATH_EP_MUL(x, mul) ((x) * (mul)) 213#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 214#define ATH_LPF_RSSI(x, y, len) \ 215 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 216#define ATH_RSSI_LPF(x, y) do { \ 217 if ((y) >= -20) \ 218 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 219} while (0) 220#define ATH_EP_RND(x,mul) \ 221 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 222#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 223 224typedef enum { 225 ATH_BUFTYPE_NORMAL = 0, 226 ATH_BUFTYPE_MGMT = 1, 227} ath_buf_type_t; 228 229struct ath_buf { 230 TAILQ_ENTRY(ath_buf) bf_list; 231 struct ath_buf * bf_next; /* next buffer in the aggregate */ 232 int bf_nseg; 233 HAL_STATUS bf_rxstatus; 234 uint16_t bf_flags; /* status flags (below) */ 235 uint16_t bf_descid; /* 16 bit descriptor ID */ 236 struct ath_desc *bf_desc; /* virtual addr of desc */ 237 struct ath_desc_status bf_status; /* tx/rx status */ 238 bus_addr_t bf_daddr; /* physical addr of desc */ 239 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 240 struct mbuf *bf_m; /* mbuf for buf */ 241 struct ieee80211_node *bf_node; /* pointer to the node */ 242 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 243 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 244 bus_size_t bf_mapsize; 245#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 246 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 247 uint32_t bf_nextfraglen; /* length of next fragment */ 248 249 /* Completion function to call on TX complete (fail or not) */ 250 /* 251 * "fail" here is set to 1 if the queue entries were removed 252 * through a call to ath_tx_draintxq(). 253 */ 254 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 255 256 /* This state is kept to support software retries and aggregation */ 257 struct { 258 uint16_t bfs_seqno; /* sequence number of this packet */ 259 uint16_t bfs_ndelim; /* number of delims for padding */ 260 261 uint8_t bfs_retries; /* retry count */ 262 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 263 uint8_t bfs_nframes; /* number of frames in aggregate */ 264 uint8_t bfs_pri; /* packet AC priority */ 265 uint8_t bfs_tx_queue; /* destination hardware TX queue */ 266 267 u_int32_t bfs_aggr:1, /* part of aggregate? */ 268 bfs_aggrburst:1, /* part of aggregate burst? */ 269 bfs_isretried:1, /* retried frame? */ 270 bfs_dobaw:1, /* actually check against BAW? */ 271 bfs_addedbaw:1, /* has been added to the BAW */ 272 bfs_shpream:1, /* use short preamble */ 273 bfs_istxfrag:1, /* is fragmented */ 274 bfs_ismrr:1, /* do multi-rate TX retry */ 275 bfs_doprot:1, /* do RTS/CTS based protection */ 276 bfs_doratelookup:1; /* do rate lookup before each TX */ 277 278 /* 279 * These fields are passed into the 280 * descriptor setup functions. 281 */ 282 283 /* Make this an 8 bit value? */ 284 HAL_PKT_TYPE bfs_atype; /* packet type */ 285 286 uint32_t bfs_pktlen; /* length of this packet */ 287 288 uint16_t bfs_hdrlen; /* length of this packet header */ 289 uint16_t bfs_al; /* length of aggregate */ 290 291 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 292 uint8_t bfs_txrate0; /* first TX rate */ 293 uint8_t bfs_try0; /* first try count */ 294 295 uint16_t bfs_txpower; /* tx power */ 296 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 297 uint8_t bfs_ctsrate; /* CTS rate */ 298 299 /* 16 bit? */ 300 int32_t bfs_keyix; /* crypto key index */ 301 int32_t bfs_txantenna; /* TX antenna config */ 302 303 /* Make this an 8 bit value? */ 304 enum ieee80211_protmode bfs_protmode; 305 306 /* 16 bit? */ 307 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 308 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 309 } bf_state; 310}; 311typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 312 313#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 314#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 315#define ATH_BUF_FIFOEND 0x00000004 316#define ATH_BUF_FIFOPTR 0x00000008 317 318#define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT) 319 320/* 321 * DMA state for tx/rx descriptors. 322 */ 323struct ath_descdma { 324 const char* dd_name; 325 struct ath_desc *dd_desc; /* descriptors */ 326 int dd_descsize; /* size of single descriptor */ 327 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 328 bus_size_t dd_desc_len; /* size of dd_desc */ 329 bus_dma_segment_t dd_dseg; 330 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 331 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 332 struct ath_buf *dd_bufptr; /* associated buffers */ 333}; 334 335/* 336 * Data transmit queue state. One of these exists for each 337 * hardware transmit queue. Packets sent to us from above 338 * are assigned to queues based on their priority. Not all 339 * devices support a complete set of hardware transmit queues. 340 * For those devices the array sc_ac2q will map multiple 341 * priorities to fewer hardware queues (typically all to one 342 * hardware queue). 343 */ 344struct ath_txq { 345 struct ath_softc *axq_softc; /* Needed for scheduling */ 346 u_int axq_qnum; /* hardware q number */ 347#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 348 u_int axq_ac; /* WME AC */ 349 u_int axq_flags; 350//#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 351#define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 352 u_int axq_depth; /* queue depth (stat only) */ 353 u_int axq_aggr_depth; /* how many aggregates are queued */ 354 u_int axq_intrcnt; /* interrupt count */ 355 u_int32_t *axq_link; /* link ptr in last TX desc */ 356 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 357 struct mtx axq_lock; /* lock on q and link */ 358 359 /* 360 * This is the FIFO staging buffer when doing EDMA. 361 * 362 * For legacy chips, we just push the head pointer to 363 * the hardware and we ignore this list. 364 * 365 * For EDMA, the staging buffer is treated as normal; 366 * when it's time to push a list of frames to the hardware 367 * we move that list here and we stamp buffers with 368 * flags to identify the beginning/end of that particular 369 * FIFO entry. 370 */ 371 struct { 372 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 373 u_int axq_depth; /* how many frames (1 per legacy, 1 per A-MPDU list) are in the FIFO queue */ 374 } fifo; 375 u_int axq_fifo_depth; /* how many FIFO slots are active */ 376 377 /* 378 * XXX the holdingbf field is protected by the TXBUF lock 379 * for now, NOT the TXQ lock. 380 * 381 * Architecturally, it would likely be better to move 382 * the holdingbf field to a separate array in ath_softc 383 * just to highlight that it's not protected by the normal 384 * TX path lock. 385 */ 386 struct ath_buf *axq_holdingbf; /* holding TX buffer */ 387 char axq_name[12]; /* e.g. "ath0_txq4" */ 388 389 /* Per-TID traffic queue for software -> hardware TX */ 390 /* 391 * This is protected by the general TX path lock, not (for now) 392 * by the TXQ lock. 393 */ 394 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 395}; 396 397#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 398 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 399 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 400 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 401 } while (0) 402#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 403#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 404#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 405#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 406#define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \ 407 MA_NOTOWNED) 408 409 410#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 411#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 412#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 413#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 414 MA_NOTOWNED) 415 416/* 417 * These are for the hardware queue. 418 */ 419#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 420 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 421 (_tq)->axq_depth++; \ 422} while (0) 423#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 424 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 425 (_tq)->axq_depth++; \ 426} while (0) 427#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 428 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 429 (_tq)->axq_depth--; \ 430} while (0) 431#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 432#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 433 434/* 435 * These are for the TID software queue. 436 */ 437#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 438 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 439 (_tq)->axq_depth++; \ 440 (_tq)->an->an_swq_depth++; \ 441} while (0) 442#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 443 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 444 (_tq)->axq_depth++; \ 445 (_tq)->an->an_swq_depth++; \ 446} while (0) 447#define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 448 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 449 (_tq)->axq_depth--; \ 450 (_tq)->an->an_swq_depth--; \ 451} while (0) 452#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 453#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 454 455/* 456 * These are for the TID filtered frame queue 457 */ 458#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 459 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 460 (_tq)->axq_depth++; \ 461 (_tq)->an->an_swq_depth++; \ 462} while (0) 463#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 464 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 465 (_tq)->axq_depth++; \ 466 (_tq)->an->an_swq_depth++; \ 467} while (0) 468#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 469 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 470 (_tq)->axq_depth--; \ 471 (_tq)->an->an_swq_depth--; \ 472} while (0) 473#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 474#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 475 476struct ath_vap { 477 struct ieee80211vap av_vap; /* base class */ 478 int av_bslot; /* beacon slot index */ 479 struct ath_buf *av_bcbuf; /* beacon buffer */ 480 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 481 482 void (*av_recv_mgmt)(struct ieee80211_node *, 483 struct mbuf *, int, 484 const struct ieee80211_rx_stats *, int, int); 485 int (*av_newstate)(struct ieee80211vap *, 486 enum ieee80211_state, int); 487 void (*av_bmiss)(struct ieee80211vap *); 488 void (*av_node_ps)(struct ieee80211_node *, int); 489 int (*av_set_tim)(struct ieee80211_node *, int); 490 void (*av_recv_pspoll)(struct ieee80211_node *, 491 struct mbuf *); 492}; 493#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 494 495struct taskqueue; 496struct ath_tx99; 497 498/* 499 * Whether to reset the TX/RX queue with or without 500 * a queue flush. 501 */ 502typedef enum { 503 ATH_RESET_DEFAULT = 0, 504 ATH_RESET_NOLOSS = 1, 505 ATH_RESET_FULL = 2, 506} ATH_RESET_TYPE; 507 508struct ath_rx_methods { 509 void (*recv_sched_queue)(struct ath_softc *sc, 510 HAL_RX_QUEUE q, int dosched); 511 void (*recv_sched)(struct ath_softc *sc, int dosched); 512 void (*recv_stop)(struct ath_softc *sc, int dodelay); 513 int (*recv_start)(struct ath_softc *sc); 514 void (*recv_flush)(struct ath_softc *sc); 515 void (*recv_tasklet)(void *arg, int npending); 516 int (*recv_rxbuf_init)(struct ath_softc *sc, 517 struct ath_buf *bf); 518 int (*recv_setup)(struct ath_softc *sc); 519 int (*recv_teardown)(struct ath_softc *sc); 520}; 521 522/* 523 * Represent the current state of the RX FIFO. 524 */ 525struct ath_rx_edma { 526 struct ath_buf **m_fifo; 527 int m_fifolen; 528 int m_fifo_head; 529 int m_fifo_tail; 530 int m_fifo_depth; 531 struct mbuf *m_rxpending; 532 struct ath_buf *m_holdbf; 533}; 534 535struct ath_tx_edma_fifo { 536 struct ath_buf **m_fifo; 537 int m_fifolen; 538 int m_fifo_head; 539 int m_fifo_tail; 540 int m_fifo_depth; 541}; 542 543struct ath_tx_methods { 544 int (*xmit_setup)(struct ath_softc *sc); 545 int (*xmit_teardown)(struct ath_softc *sc); 546 void (*xmit_attach_comp_func)(struct ath_softc *sc); 547 548 void (*xmit_dma_restart)(struct ath_softc *sc, 549 struct ath_txq *txq); 550 void (*xmit_handoff)(struct ath_softc *sc, 551 struct ath_txq *txq, struct ath_buf *bf); 552 void (*xmit_drain)(struct ath_softc *sc, 553 ATH_RESET_TYPE reset_type); 554}; 555 556struct ath_softc { 557 struct ieee80211com sc_ic; 558 struct ath_stats sc_stats; /* device statistics */ 559 struct ath_tx_aggr_stats sc_aggr_stats; 560 struct ath_intr_stats sc_intr_stats; 561 uint64_t sc_debug; 562 uint64_t sc_ktrdebug; 563 int sc_nvaps; /* # vaps */ 564 int sc_nstavaps; /* # station vaps */ 565 int sc_nmeshvaps; /* # mbss vaps */ 566 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 567 u_int8_t sc_nbssid0; /* # vap's using base mac */ 568 uint32_t sc_bssidmask; /* bssid mask */ 569 570 struct ath_rx_methods sc_rx; 571 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 572 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 573 struct ath_tx_methods sc_tx; 574 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 575 576 /* 577 * This is (currently) protected by the TX queue lock; 578 * it should migrate to a separate lock later 579 * so as to minimise contention. 580 */ 581 ath_bufhead sc_txbuf_list; 582 583 int sc_rx_statuslen; 584 int sc_tx_desclen; 585 int sc_tx_statuslen; 586 int sc_tx_nmaps; /* Number of TX maps */ 587 int sc_edma_bufsize; 588 int sc_rx_stopped; /* XXX only for EDMA */ 589 int sc_rx_resetted; /* XXX only for EDMA */ 590 591 void (*sc_node_cleanup)(struct ieee80211_node *); 592 void (*sc_node_free)(struct ieee80211_node *); 593 device_t sc_dev; 594 HAL_BUS_TAG sc_st; /* bus space tag */ 595 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 596 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 597 struct mtx sc_mtx; /* master lock (recursive) */ 598 struct mtx sc_pcu_mtx; /* PCU access mutex */ 599 char sc_pcu_mtx_name[32]; 600 struct mtx sc_rx_mtx; /* RX access mutex */ 601 char sc_rx_mtx_name[32]; 602 struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 603 char sc_tx_mtx_name[32]; 604 struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 605 char sc_tx_ic_mtx_name[32]; 606 struct taskqueue *sc_tq; /* private task queue */ 607 struct ath_hal *sc_ah; /* Atheros HAL */ 608 struct ath_ratectrl *sc_rc; /* tx rate control support */ 609 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 610 void (*sc_setdefantenna)(struct ath_softc *, u_int); 611 612 /* 613 * First set of flags. 614 */ 615 uint32_t sc_invalid : 1,/* disable hardware accesses */ 616 sc_mrretry : 1,/* multi-rate retry support */ 617 sc_mrrprot : 1,/* MRR + protection support */ 618 sc_softled : 1,/* enable LED gpio status */ 619 sc_hardled : 1,/* enable MAC LED status */ 620 sc_splitmic : 1,/* split TKIP MIC keys */ 621 sc_needmib : 1,/* enable MIB stats intr */ 622 sc_diversity: 1,/* enable rx diversity */ 623 sc_hasveol : 1,/* tx VEOL support */ 624 sc_ledstate : 1,/* LED on/off state */ 625 sc_blinking : 1,/* LED blink operation active */ 626 sc_mcastkey : 1,/* mcast key cache search */ 627 sc_scanning : 1,/* scanning active */ 628 sc_syncbeacon:1,/* sync/resync beacon timers */ 629 sc_hasclrkey: 1,/* CLR key supported */ 630 sc_xchanmode: 1,/* extended channel mode */ 631 sc_outdoor : 1,/* outdoor operation */ 632 sc_dturbo : 1,/* dynamic turbo in use */ 633 sc_hasbmask : 1,/* bssid mask support */ 634 sc_hasbmatch: 1,/* bssid match disable support*/ 635 sc_hastsfadd: 1,/* tsf adjust support */ 636 sc_beacons : 1,/* beacons running */ 637 sc_swbmiss : 1,/* sta mode using sw bmiss */ 638 sc_stagbeacons:1,/* use staggered beacons */ 639 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 640 sc_resume_up: 1,/* on resume, start all vaps */ 641 sc_tdma : 1,/* TDMA in use */ 642 sc_setcca : 1,/* set/clr CCA with TDMA */ 643 sc_resetcal : 1,/* reset cal state next trip */ 644 sc_rxslink : 1,/* do self-linked final descriptor */ 645 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 646 sc_isedma : 1,/* supports EDMA */ 647 sc_do_mybeacon : 1; /* supports mybeacon */ 648 649 /* 650 * Second set of flags. 651 */ 652 u_int32_t sc_running : 1, /* initialized */ 653 sc_use_ent : 1, 654 sc_rx_stbc : 1, 655 sc_tx_stbc : 1, 656 sc_has_ldpc : 1, 657 sc_hasenforcetxop : 1, /* support enforce TxOP */ 658 sc_hasdivcomb : 1, /* RX diversity combining */ 659 sc_rx_lnamixer : 1, /* RX using LNA mixing */ 660 sc_btcoex_mci : 1; /* MCI bluetooth coex */ 661 662 int sc_cabq_enable; /* Enable cabq transmission */ 663 664 /* 665 * Enterprise mode configuration for AR9380 and later chipsets. 666 */ 667 uint32_t sc_ent_cfg; 668 669 uint32_t sc_eerd; /* regdomain from EEPROM */ 670 uint32_t sc_eecc; /* country code from EEPROM */ 671 /* rate tables */ 672 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 673 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 674 enum ieee80211_phymode sc_curmode; /* current phy mode */ 675 HAL_OPMODE sc_opmode; /* current operating mode */ 676 u_int16_t sc_curtxpow; /* current tx power limit */ 677 u_int16_t sc_curaid; /* current association id */ 678 struct ieee80211_channel *sc_curchan; /* current installed channel */ 679 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 680 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 681 struct { 682 u_int8_t ieeerate; /* IEEE rate */ 683 u_int8_t rxflags; /* radiotap rx flags */ 684 u_int8_t txflags; /* radiotap tx flags */ 685 u_int16_t ledon; /* softled on time */ 686 u_int16_t ledoff; /* softled off time */ 687 } sc_hwmap[32]; /* h/w rate ix mappings */ 688 u_int8_t sc_protrix; /* protection rate index */ 689 u_int8_t sc_lastdatarix; /* last data frame rate index */ 690 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 691 u_int sc_fftxqmin; /* min frames before staging */ 692 u_int sc_fftxqmax; /* max frames before drop */ 693 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 694 695 HAL_INT sc_imask; /* interrupt mask copy */ 696 697 /* 698 * These are modified in the interrupt handler as well as 699 * the task queues and other contexts. Thus these must be 700 * protected by a mutex, or they could clash. 701 * 702 * For now, access to these is behind the ATH_LOCK, 703 * just to save time. 704 */ 705 uint32_t sc_txq_active; /* bitmap of active TXQs */ 706 uint32_t sc_kickpcu; /* whether to kick the PCU */ 707 uint32_t sc_rxproc_cnt; /* In RX processing */ 708 uint32_t sc_txproc_cnt; /* In TX processing */ 709 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 710 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 711 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 712 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 713 714 u_int sc_keymax; /* size of key cache */ 715 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 716 717 /* 718 * Software based LED blinking 719 */ 720 u_int sc_ledpin; /* GPIO pin for driving LED */ 721 u_int sc_ledon; /* pin setting for LED on */ 722 u_int sc_ledidle; /* idle polling interval */ 723 int sc_ledevent; /* time of last LED event */ 724 u_int8_t sc_txrix; /* current tx rate for LED */ 725 u_int16_t sc_ledoff; /* off time for current blink */ 726 struct callout sc_ledtimer; /* led off timer */ 727 728 /* 729 * Hardware based LED blinking 730 */ 731 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 732 int sc_led_net_pin; /* MAC network LED GPIO pin */ 733 734 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 735 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 736 737 struct ath_descdma sc_rxdma; /* RX descriptors */ 738 ath_bufhead sc_rxbuf; /* receive buffer */ 739 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 740 struct task sc_rxtask; /* rx int processing */ 741 u_int8_t sc_defant; /* current default antenna */ 742 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 743 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 744 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 745 struct ath_rx_radiotap_header sc_rx_th; 746 int sc_rx_th_len; 747 u_int sc_monpass; /* frames to pass in mon.mode */ 748 749 struct ath_descdma sc_txdma; /* TX descriptors */ 750 uint16_t sc_txbuf_descid; 751 ath_bufhead sc_txbuf; /* transmit buffer */ 752 int sc_txbuf_cnt; /* how many buffers avail */ 753 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 754 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 755 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 756 struct mtx sc_txbuflock; /* txbuf lock */ 757 char sc_txname[12]; /* e.g. "ath0_buf" */ 758 u_int sc_txqsetup; /* h/w queues setup */ 759 u_int sc_txintrperiod;/* tx interrupt batching */ 760 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 761 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 762 struct task sc_txtask; /* tx int processing */ 763 struct task sc_txqtask; /* tx proc processing */ 764 765 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 766 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 767 char sc_txcompname[12]; /* eg ath0_txcomp */ 768 769 int sc_wd_timer; /* count down for wd timer */ 770 struct callout sc_wd_ch; /* tx watchdog timer */ 771 struct ath_tx_radiotap_header sc_tx_th; 772 int sc_tx_th_len; 773 774 struct ath_descdma sc_bdma; /* beacon descriptors */ 775 ath_bufhead sc_bbuf; /* beacon buffers */ 776 u_int sc_bhalq; /* HAL q for outgoing beacons */ 777 u_int sc_bmisscount; /* missed beacon transmits */ 778 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 779 struct ath_txq *sc_cabq; /* tx q for cab frames */ 780 struct task sc_bmisstask; /* bmiss int processing */ 781 struct task sc_bstucktask; /* stuck beacon processing */ 782 struct task sc_resettask; /* interface reset task */ 783 struct task sc_fataltask; /* fatal task */ 784 enum { 785 OK, /* no change needed */ 786 UPDATE, /* update pending */ 787 COMMIT /* beacon sent, commit change */ 788 } sc_updateslot; /* slot time update fsm */ 789 int sc_slotupdate; /* slot to advance fsm */ 790 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 791 int sc_nbcnvaps; /* # vaps with beacons */ 792 793 struct callout sc_cal_ch; /* callout handle for cals */ 794 int sc_lastlongcal; /* last long cal completed */ 795 int sc_lastcalreset;/* last cal reset done */ 796 int sc_lastani; /* last ANI poll */ 797 int sc_lastshortcal; /* last short calibration */ 798 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 799 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 800 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 801 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 802 u_int sc_tdmaswba; /* TDMA SWBA counter */ 803 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 804 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 805 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 806 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 807 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 808 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 809 uint32_t sc_txchainmask; /* hardware TX chainmask */ 810 uint32_t sc_rxchainmask; /* hardware RX chainmask */ 811 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 812 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 813 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 814 int sc_aggr_limit; /* TX limit on all aggregates */ 815 int sc_delim_min_pad; /* Minimum delimiter count */ 816 817 /* Queue limits */ 818 819 /* 820 * To avoid queue starvation in congested conditions, 821 * these parameters tune the maximum number of frames 822 * queued to the data/mcastq before they're dropped. 823 * 824 * This is to prevent: 825 * + a single destination overwhelming everything, including 826 * management/multicast frames; 827 * + multicast frames overwhelming everything (when the 828 * air is sufficiently busy that cabq can't drain.) 829 * + A node in powersave shouldn't be allowed to exhaust 830 * all available mbufs; 831 * 832 * These implement: 833 * + data_minfree is the maximum number of free buffers 834 * overall to successfully allow a data frame. 835 * 836 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 837 */ 838 int sc_txq_node_maxdepth; 839 int sc_txq_data_minfree; 840 int sc_txq_mcastq_maxdepth; 841 int sc_txq_node_psq_maxdepth; 842 843 /* 844 * Software queue twiddles 845 * 846 * hwq_limit_nonaggr: 847 * when to begin limiting non-aggregate frames to the 848 * hardware queue, regardless of the TID. 849 * hwq_limit_aggr: 850 * when to begin limiting A-MPDU frames to the 851 * hardware queue, regardless of the TID. 852 * tid_hwq_lo: how low the per-TID hwq count has to be before the 853 * TID will be scheduled again 854 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 855 * stops being scheduled. 856 */ 857 int sc_hwq_limit_nonaggr; 858 int sc_hwq_limit_aggr; 859 int sc_tid_hwq_lo; 860 int sc_tid_hwq_hi; 861 862 /* DFS related state */ 863 void *sc_dfs; /* Used by an optional DFS module */ 864 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 865 struct task sc_dfstask; /* DFS processing task */ 866 867 /* Spectral related state */ 868 void *sc_spectral; 869 int sc_dospectral; 870 871 /* LNA diversity related state */ 872 void *sc_lna_div; 873 int sc_dolnadiv; 874 875 /* ALQ */ 876#ifdef ATH_DEBUG_ALQ 877 struct if_ath_alq sc_alq; 878#endif 879 880 /* TX AMPDU handling */ 881 int (*sc_addba_request)(struct ieee80211_node *, 882 struct ieee80211_tx_ampdu *, int, int, int); 883 int (*sc_addba_response)(struct ieee80211_node *, 884 struct ieee80211_tx_ampdu *, int, int, int); 885 void (*sc_addba_stop)(struct ieee80211_node *, 886 struct ieee80211_tx_ampdu *); 887 void (*sc_addba_response_timeout) 888 (struct ieee80211_node *, 889 struct ieee80211_tx_ampdu *); 890 void (*sc_bar_response)(struct ieee80211_node *ni, 891 struct ieee80211_tx_ampdu *tap, 892 int status); 893 894 /* 895 * Powersave state tracking. 896 * 897 * target/cur powerstate is the chip power state. 898 * target selfgen state is the self-generated frames 899 * state. The chip can be awake but transmitted frames 900 * can have the PWRMGT bit set to 1 so the destination 901 * thinks the node is asleep. 902 */ 903 HAL_POWER_MODE sc_target_powerstate; 904 HAL_POWER_MODE sc_target_selfgen_state; 905 906 HAL_POWER_MODE sc_cur_powerstate; 907 908 int sc_powersave_refcnt; 909 910 /* ATH_PCI_* flags */ 911 uint32_t sc_pci_devinfo; 912 913 /* BT coex */ 914 struct { 915 struct ath_descdma buf; 916 917 /* gpm/sched buffer, saved pointers */ 918 char *sched_buf; 919 bus_addr_t sched_paddr; 920 char *gpm_buf; 921 bus_addr_t gpm_paddr; 922 923 uint32_t wlan_channels[4]; 924 } sc_btcoex; 925}; 926 927#define ATH_LOCK_INIT(_sc) \ 928 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 929 NULL, MTX_DEF | MTX_RECURSE) 930#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 931#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 932#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 933#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 934#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 935 936/* 937 * The TX lock is non-reentrant and serialises the TX frame send 938 * and completion operations. 939 */ 940#define ATH_TX_LOCK_INIT(_sc) do {\ 941 snprintf((_sc)->sc_tx_mtx_name, \ 942 sizeof((_sc)->sc_tx_mtx_name), \ 943 "%s TX lock", \ 944 device_get_nameunit((_sc)->sc_dev)); \ 945 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 946 NULL, MTX_DEF); \ 947 } while (0) 948#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 949#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 950#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 951#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 952 MA_OWNED) 953#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 954 MA_NOTOWNED) 955#define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ 956 mtx_trylock(&(_sc)->sc_tx_mtx)) 957 958/* 959 * The PCU lock is non-recursive and should be treated as a spinlock. 960 * Although currently the interrupt code is run in netisr context and 961 * doesn't require this, this may change in the future. 962 * Please keep this in mind when protecting certain code paths 963 * with the PCU lock. 964 * 965 * The PCU lock is used to serialise access to the PCU so things such 966 * as TX, RX, state change (eg channel change), channel reset and updates 967 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 968 * 969 * Although the current single-thread taskqueue mechanism protects the 970 * majority of these situations by simply serialising them, there are 971 * a few others which occur at the same time. These include the TX path 972 * (which only acquires ATH_LOCK when recycling buffers to the free list), 973 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 974 */ 975#define ATH_PCU_LOCK_INIT(_sc) do {\ 976 snprintf((_sc)->sc_pcu_mtx_name, \ 977 sizeof((_sc)->sc_pcu_mtx_name), \ 978 "%s PCU lock", \ 979 device_get_nameunit((_sc)->sc_dev)); \ 980 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 981 NULL, MTX_DEF); \ 982 } while (0) 983#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 984#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 985#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 986#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 987 MA_OWNED) 988#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 989 MA_NOTOWNED) 990 991/* 992 * The RX lock is primarily a(nother) workaround to ensure that the 993 * RX FIFO/list isn't modified by various execution paths. 994 * Even though RX occurs in a single context (the ath taskqueue), the 995 * RX path can be executed via various reset/channel change paths. 996 */ 997#define ATH_RX_LOCK_INIT(_sc) do {\ 998 snprintf((_sc)->sc_rx_mtx_name, \ 999 sizeof((_sc)->sc_rx_mtx_name), \ 1000 "%s RX lock", \ 1001 device_get_nameunit((_sc)->sc_dev)); \ 1002 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 1003 NULL, MTX_DEF); \ 1004 } while (0) 1005#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 1006#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 1007#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 1008#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1009 MA_OWNED) 1010#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1011 MA_NOTOWNED) 1012 1013#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 1014 1015#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 1016 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 1017 device_get_nameunit((_sc)->sc_dev)); \ 1018 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 1019} while (0) 1020#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 1021#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 1022#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 1023#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 1024 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 1025#define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ 1026 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED) 1027 1028#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 1029 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 1030 "%s_buf", \ 1031 device_get_nameunit((_sc)->sc_dev)); \ 1032 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 1033 MTX_DEF); \ 1034} while (0) 1035#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 1036#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 1037#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 1038#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 1039 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 1040 1041int ath_attach(u_int16_t, struct ath_softc *); 1042int ath_detach(struct ath_softc *); 1043void ath_resume(struct ath_softc *); 1044void ath_suspend(struct ath_softc *); 1045void ath_shutdown(struct ath_softc *); 1046void ath_intr(void *); 1047 1048/* 1049 * HAL definitions to comply with local coding convention. 1050 */ 1051#define ath_hal_detach(_ah) \ 1052 ((*(_ah)->ah_detach)((_ah))) 1053#define ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \ 1054 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \ 1055 (_resettype), (_pstatus))) 1056#define ath_hal_macversion(_ah) \ 1057 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 1058#define ath_hal_getratetable(_ah, _mode) \ 1059 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1060#define ath_hal_getmac(_ah, _mac) \ 1061 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1062#define ath_hal_setmac(_ah, _mac) \ 1063 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1064#define ath_hal_getbssidmask(_ah, _mask) \ 1065 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 1066#define ath_hal_setbssidmask(_ah, _mask) \ 1067 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 1068#define ath_hal_intrset(_ah, _mask) \ 1069 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1070#define ath_hal_intrget(_ah) \ 1071 ((*(_ah)->ah_getInterrupts)((_ah))) 1072#define ath_hal_intrpend(_ah) \ 1073 ((*(_ah)->ah_isInterruptPending)((_ah))) 1074#define ath_hal_getisr(_ah, _pmask) \ 1075 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1076#define ath_hal_updatetxtriglevel(_ah, _inc) \ 1077 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1078#define ath_hal_setpower(_ah, _mode) \ 1079 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1080#define ath_hal_setselfgenpower(_ah, _mode) \ 1081 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE)) 1082#define ath_hal_keycachesize(_ah) \ 1083 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1084#define ath_hal_keyreset(_ah, _ix) \ 1085 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1086#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1087 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1088#define ath_hal_keyisvalid(_ah, _ix) \ 1089 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1090#define ath_hal_keysetmac(_ah, _ix, _mac) \ 1091 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1092#define ath_hal_getrxfilter(_ah) \ 1093 ((*(_ah)->ah_getRxFilter)((_ah))) 1094#define ath_hal_setrxfilter(_ah, _filter) \ 1095 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1096#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1097 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1098#define ath_hal_waitforbeacon(_ah, _bf) \ 1099 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1100#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1101 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1102/* NB: common across all chips */ 1103#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1104#define ath_hal_gettsf32(_ah) \ 1105 OS_REG_READ(_ah, AR_TSF_L32) 1106#define ath_hal_gettsf64(_ah) \ 1107 ((*(_ah)->ah_getTsf64)((_ah))) 1108#define ath_hal_settsf64(_ah, _val) \ 1109 ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1110#define ath_hal_resettsf(_ah) \ 1111 ((*(_ah)->ah_resetTsf)((_ah))) 1112#define ath_hal_rxena(_ah) \ 1113 ((*(_ah)->ah_enableReceive)((_ah))) 1114#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1115 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1116#define ath_hal_gettxbuf(_ah, _q) \ 1117 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1118#define ath_hal_numtxpending(_ah, _q) \ 1119 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1120#define ath_hal_getrxbuf(_ah, _rxq) \ 1121 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1122#define ath_hal_txstart(_ah, _q) \ 1123 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1124#define ath_hal_setchannel(_ah, _chan) \ 1125 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1126#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1127 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1128#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1129 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1130#define ath_hal_calreset(_ah, _chan) \ 1131 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1132#define ath_hal_setledstate(_ah, _state) \ 1133 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1134#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1135 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1136#define ath_hal_beaconreset(_ah) \ 1137 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1138#define ath_hal_beaconsettimers(_ah, _bt) \ 1139 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1140#define ath_hal_beacontimers(_ah, _bs) \ 1141 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1142#define ath_hal_getnexttbtt(_ah) \ 1143 ((*(_ah)->ah_getNextTBTT)((_ah))) 1144#define ath_hal_setassocid(_ah, _bss, _associd) \ 1145 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1146#define ath_hal_phydisable(_ah) \ 1147 ((*(_ah)->ah_phyDisable)((_ah))) 1148#define ath_hal_setopmode(_ah) \ 1149 ((*(_ah)->ah_setPCUConfig)((_ah))) 1150#define ath_hal_stoptxdma(_ah, _qnum) \ 1151 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1152#define ath_hal_stoppcurecv(_ah) \ 1153 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1154#define ath_hal_startpcurecv(_ah) \ 1155 ((*(_ah)->ah_startPcuReceive)((_ah))) 1156#define ath_hal_stopdmarecv(_ah) \ 1157 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1158#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1159 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1160 (_indata), (_insize), (_outdata), (_outsize))) 1161#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1162 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1163#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1164 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1165#define ath_hal_resettxqueue(_ah, _q) \ 1166 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1167#define ath_hal_releasetxqueue(_ah, _q) \ 1168 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1169#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1170 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1171#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1172 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1173/* NB: common across all chips */ 1174#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1175#define ath_hal_txqenabled(_ah, _qnum) \ 1176 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1177#define ath_hal_getrfgain(_ah) \ 1178 ((*(_ah)->ah_getRfGain)((_ah))) 1179#define ath_hal_getdefantenna(_ah) \ 1180 ((*(_ah)->ah_getDefAntenna)((_ah))) 1181#define ath_hal_setdefantenna(_ah, _ant) \ 1182 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1183#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1184 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1185#define ath_hal_ani_poll(_ah, _chan) \ 1186 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1187#define ath_hal_mibevent(_ah, _stats) \ 1188 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1189#define ath_hal_setslottime(_ah, _us) \ 1190 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1191#define ath_hal_getslottime(_ah) \ 1192 ((*(_ah)->ah_getSlotTime)((_ah))) 1193#define ath_hal_setacktimeout(_ah, _us) \ 1194 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1195#define ath_hal_getacktimeout(_ah) \ 1196 ((*(_ah)->ah_getAckTimeout)((_ah))) 1197#define ath_hal_setctstimeout(_ah, _us) \ 1198 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1199#define ath_hal_getctstimeout(_ah) \ 1200 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1201#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1202 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1203#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1204 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1205#define ath_hal_ciphersupported(_ah, _cipher) \ 1206 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1207#define ath_hal_getregdomain(_ah, _prd) \ 1208 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1209#define ath_hal_setregdomain(_ah, _rd) \ 1210 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1211#define ath_hal_getcountrycode(_ah, _pcc) \ 1212 (*(_pcc) = (_ah)->ah_countryCode) 1213#define ath_hal_gettkipmic(_ah) \ 1214 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1215#define ath_hal_settkipmic(_ah, _v) \ 1216 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1217#define ath_hal_hastkipsplit(_ah) \ 1218 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1219#define ath_hal_gettkipsplit(_ah) \ 1220 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1221#define ath_hal_settkipsplit(_ah, _v) \ 1222 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1223#define ath_hal_haswmetkipmic(_ah) \ 1224 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1225#define ath_hal_hwphycounters(_ah) \ 1226 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1227#define ath_hal_hasdiversity(_ah) \ 1228 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1229#define ath_hal_getdiversity(_ah) \ 1230 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1231#define ath_hal_setdiversity(_ah, _v) \ 1232 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1233#define ath_hal_getantennaswitch(_ah) \ 1234 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1235#define ath_hal_setantennaswitch(_ah, _v) \ 1236 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1237#define ath_hal_getdiag(_ah, _pv) \ 1238 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1239#define ath_hal_setdiag(_ah, _v) \ 1240 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1241#define ath_hal_getnumtxqueues(_ah, _pv) \ 1242 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1243#define ath_hal_hasveol(_ah) \ 1244 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1245#define ath_hal_hastxpowlimit(_ah) \ 1246 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1247#define ath_hal_settxpowlimit(_ah, _pow) \ 1248 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1249#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1250 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1251#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1252 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1253#define ath_hal_gettpscale(_ah, _scale) \ 1254 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1255#define ath_hal_settpscale(_ah, _v) \ 1256 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1257#define ath_hal_hastpc(_ah) \ 1258 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1259#define ath_hal_gettpc(_ah) \ 1260 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1261#define ath_hal_settpc(_ah, _v) \ 1262 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1263#define ath_hal_hasbursting(_ah) \ 1264 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1265#define ath_hal_setmcastkeysearch(_ah, _v) \ 1266 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1267#define ath_hal_hasmcastkeysearch(_ah) \ 1268 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1269#define ath_hal_getmcastkeysearch(_ah) \ 1270 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1271#define ath_hal_hasfastframes(_ah) \ 1272 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1273#define ath_hal_hasbssidmask(_ah) \ 1274 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1275#define ath_hal_hasbssidmatch(_ah) \ 1276 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1277#define ath_hal_hastsfadjust(_ah) \ 1278 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1279#define ath_hal_gettsfadjust(_ah) \ 1280 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1281#define ath_hal_settsfadjust(_ah, _onoff) \ 1282 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1283#define ath_hal_hasrfsilent(_ah) \ 1284 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1285#define ath_hal_getrfkill(_ah) \ 1286 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1287#define ath_hal_setrfkill(_ah, _onoff) \ 1288 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1289#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1290 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1291#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1292 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1293#define ath_hal_gettpack(_ah, _ptpack) \ 1294 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1295#define ath_hal_settpack(_ah, _tpack) \ 1296 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1297#define ath_hal_gettpcts(_ah, _ptpcts) \ 1298 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1299#define ath_hal_settpcts(_ah, _tpcts) \ 1300 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1301#define ath_hal_hasintmit(_ah) \ 1302 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1303 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1304#define ath_hal_getintmit(_ah) \ 1305 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1306 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1307#define ath_hal_setintmit(_ah, _v) \ 1308 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1309 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1310#define ath_hal_hasmybeacon(_ah) \ 1311 (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK) 1312 1313#define ath_hal_hasenforcetxop(_ah) \ 1314 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) 1315#define ath_hal_getenforcetxop(_ah) \ 1316 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK) 1317#define ath_hal_setenforcetxop(_ah, _v) \ 1318 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL) 1319 1320#define ath_hal_hasrxlnamixer(_ah) \ 1321 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK) 1322 1323#define ath_hal_hasdivantcomb(_ah) \ 1324 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK) 1325#define ath_hal_hasldpc(_ah) \ 1326 (ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK) 1327#define ath_hal_hasldpcwar(_ah) \ 1328 (ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK) 1329 1330/* EDMA definitions */ 1331#define ath_hal_hasedma(_ah) \ 1332 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1333 0, NULL) == HAL_OK) 1334#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1335 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1336 == HAL_OK) 1337#define ath_hal_getntxmaps(_ah, _req) \ 1338 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1339 == HAL_OK) 1340#define ath_hal_gettxdesclen(_ah, _req) \ 1341 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1342 == HAL_OK) 1343#define ath_hal_gettxstatuslen(_ah, _req) \ 1344 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1345 == HAL_OK) 1346#define ath_hal_getrxstatuslen(_ah, _req) \ 1347 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1348 == HAL_OK) 1349#define ath_hal_setrxbufsize(_ah, _req) \ 1350 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1351 == HAL_OK) 1352 1353#define ath_hal_getchannoise(_ah, _c) \ 1354 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1355 1356/* 802.11n HAL methods */ 1357#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1358 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1359#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1360 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1361#define ath_hal_setrxchainmask(_ah, _rx) \ 1362 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1363#define ath_hal_settxchainmask(_ah, _tx) \ 1364 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1365#define ath_hal_split4ktrans(_ah) \ 1366 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1367 0, NULL) == HAL_OK) 1368#define ath_hal_self_linked_final_rxdesc(_ah) \ 1369 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1370 0, NULL) == HAL_OK) 1371#define ath_hal_gtxto_supported(_ah) \ 1372 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1373#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1374 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1375 0, NULL) == HAL_OK) 1376#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1377 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1378#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1379 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1380#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1381 _txr0, _txtr0, _keyix, _ant, _flags, \ 1382 _rtsrate, _rtsdura) \ 1383 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1384 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1385 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1386#define ath_hal_setupxtxdesc(_ah, _ds, \ 1387 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1388 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1389 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1390#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1391 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1392 (_first), (_last), (_ds0))) 1393#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1394 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1395#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1396 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1397#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1398 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1399#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1400 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1401#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1402 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1403#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1404 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1405#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1406 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1407 (_size))) 1408#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1409 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1410 1411#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1412 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1413 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1414 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1415#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1416 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1417 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1418 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1419 (_first), (_last), (_lastaggr))) 1420#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1421 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1422 1423#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1424 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1425 (_series), (_ns), (_flags))) 1426 1427#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1428 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1429#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1430 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1431#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1432 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1433 1434#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1435 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1436#define ath_hal_clr11n_aggr(_ah, _ds) \ 1437 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1438#define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1439 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1440 1441#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1442 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1443#define ath_hal_gpioset(_ah, _gpio, _b) \ 1444 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1445#define ath_hal_gpioget(_ah, _gpio) \ 1446 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1447#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1448 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1449 1450/* 1451 * PCIe suspend/resume/poweron/poweroff related macros 1452 */ 1453#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1454 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1455#define ath_hal_disablepcie(_ah) \ 1456 ((*(_ah)->ah_disablePCIE)((_ah))) 1457 1458/* 1459 * This is badly-named; you need to set the correct parameters 1460 * to begin to receive useful radar events; and even then 1461 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1462 * more information. 1463 */ 1464#define ath_hal_enabledfs(_ah, _param) \ 1465 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1466#define ath_hal_getdfsthresh(_ah, _param) \ 1467 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1468#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1469 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1470#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1471 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1472 (_buf), (_event))) 1473#define ath_hal_is_fast_clock_enabled(_ah) \ 1474 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1475#define ath_hal_radar_wait(_ah, _chan) \ 1476 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1477#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1478 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1479#define ath_hal_get_chan_ext_busy(_ah) \ 1480 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1481#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1482 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1483 1484#define ath_hal_spectral_supported(_ah) \ 1485 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1486#define ath_hal_spectral_get_config(_ah, _p) \ 1487 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1488#define ath_hal_spectral_configure(_ah, _p) \ 1489 ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1490#define ath_hal_spectral_start(_ah) \ 1491 ((*(_ah)->ah_spectralStart)((_ah))) 1492#define ath_hal_spectral_stop(_ah) \ 1493 ((*(_ah)->ah_spectralStop)((_ah))) 1494 1495#define ath_hal_btcoex_supported(_ah) \ 1496 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK) 1497#define ath_hal_btcoex_set_info(_ah, _info) \ 1498 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info))) 1499#define ath_hal_btcoex_set_config(_ah, _cfg) \ 1500 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg))) 1501#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ 1502 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid))) 1503#define ath_hal_btcoex_set_weights(_ah, _weight) \ 1504 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1505#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ 1506 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr))) 1507#define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \ 1508 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val))) 1509#define ath_hal_btcoex_enable(_ah) \ 1510 ((*(_ah)->ah_btCoexEnable)((_ah))) 1511#define ath_hal_btcoex_disable(_ah) \ 1512 ((*(_ah)->ah_btCoexDisable)((_ah))) 1513 1514#define ath_hal_btcoex_mci_setup(_ah, _gp, _gb, _gl, _sp) \ 1515 ((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp))) 1516#define ath_hal_btcoex_mci_send_message(_ah, _h, _f, _p, _l, _wd, _cbt) \ 1517 ((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt))) 1518#define ath_hal_btcoex_mci_get_interrupt(_ah, _mi, _mm) \ 1519 ((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm))) 1520#define ath_hal_btcoex_mci_state(_ah, _st, _pd) \ 1521 ((*(_ah)->ah_btMciState)((_ah), (_st), (_pd))) 1522#define ath_hal_btcoex_mci_detach(_ah) \ 1523 ((*(_ah)->ah_btMciDetach)((_ah))) 1524 1525#define ath_hal_div_comb_conf_get(_ah, _conf) \ 1526 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf))) 1527#define ath_hal_div_comb_conf_set(_ah, _conf) \ 1528 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf))) 1529 1530#endif /* _DEV_ATH_ATHVAR_H */ 1531