if_athvar.h revision 235491
1116743Ssam/*-
2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3116743Ssam * All rights reserved.
4116743Ssam *
5116743Ssam * Redistribution and use in source and binary forms, with or without
6116743Ssam * modification, are permitted provided that the following conditions
7116743Ssam * are met:
8116743Ssam * 1. Redistributions of source code must retain the above copyright
9116743Ssam *    notice, this list of conditions and the following disclaimer,
10116743Ssam *    without modification.
11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12116743Ssam *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13116743Ssam *    redistribution must be conditioned upon including a substantially
14116743Ssam *    similar Disclaimer requirement for further binary redistribution.
15116743Ssam *
16116743Ssam * NO WARRANTY
17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES.
28116743Ssam *
29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athvar.h 235491 2012-05-15 23:39:37Z adrian $
30116743Ssam */
31116743Ssam
32116743Ssam/*
33116743Ssam * Defintions for the Atheros Wireless LAN controller driver.
34116743Ssam */
35116743Ssam#ifndef _DEV_ATH_ATHVAR_H
36116743Ssam#define _DEV_ATH_ATHVAR_H
37116743Ssam
38185522Ssam#include <dev/ath/ath_hal/ah.h>
39185522Ssam#include <dev/ath/ath_hal/ah_desc.h>
40119783Ssam#include <net80211/ieee80211_radiotap.h>
41116743Ssam#include <dev/ath/if_athioctl.h>
42138570Ssam#include <dev/ath/if_athrate.h>
43116743Ssam
44116743Ssam#define	ATH_TIMEOUT		1000
45116743Ssam
46220033Sadrian/*
47220033Sadrian * 802.11n requires more TX and RX buffers to do AMPDU.
48220033Sadrian */
49220053Sadrian#ifdef	ATH_ENABLE_11N
50234323Sadrian#define	ATH_TXBUF	128
51220033Sadrian#define	ATH_RXBUF	512
52220033Sadrian#endif
53220033Sadrian
54155481Ssam#ifndef ATH_RXBUF
55116743Ssam#define	ATH_RXBUF	40		/* number of RX buffers */
56155481Ssam#endif
57155481Ssam#ifndef ATH_TXBUF
58170530Ssam#define	ATH_TXBUF	200		/* number of TX buffers */
59155481Ssam#endif
60178354Ssam#define	ATH_BCBUF	4		/* number of beacon buffers */
61178354Ssam
62140438Ssam#define	ATH_TXDESC	10		/* number of descriptors per buffer */
63138570Ssam#define	ATH_TXMAXTRY	11		/* max number of transmit attempts */
64155480Ssam#define	ATH_TXMGTTRY	4		/* xmit attempts for mgt/ctl frames */
65138570Ssam#define	ATH_TXINTR_PERIOD 5		/* max number of batched tx descriptors */
66116743Ssam
67225818Sadrian#define	ATH_BEACON_AIFS_DEFAULT	 1	/* default aifs for ap beacon q */
68147067Ssam#define	ATH_BEACON_CWMIN_DEFAULT 0	/* default cwmin for ap beacon q */
69147067Ssam#define	ATH_BEACON_CWMAX_DEFAULT 0	/* default cwmax for ap beacon q */
70147067Ssam
71147057Ssam/*
72147057Ssam * The key cache is used for h/w cipher state and also for
73147057Ssam * tracking station state such as the current tx antenna.
74147057Ssam * We also setup a mapping table between key cache slot indices
75147057Ssam * and station state to short-circuit node lookups on rx.
76147057Ssam * Different parts have different size key caches.  We handle
77147057Ssam * up to ATH_KEYMAX entries (could dynamically allocate state).
78147057Ssam */
79147057Ssam#define	ATH_KEYMAX	128		/* max key cache size we handle */
80147057Ssam#define	ATH_KEYBYTES	(ATH_KEYMAX/NBBY)	/* storage space in bytes */
81147057Ssam
82170530Ssamstruct taskqueue;
83170530Ssamstruct kthread;
84170530Ssamstruct ath_buf;
85170530Ssam
86227328Sadrian#define	ATH_TID_MAX_BUFS	(2 * IEEE80211_AGGR_BAWMAX)
87227328Sadrian
88227328Sadrian/*
89227328Sadrian * Per-TID state
90227328Sadrian *
91227328Sadrian * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames.
92227328Sadrian */
93227328Sadrianstruct ath_tid {
94227328Sadrian	TAILQ_HEAD(,ath_buf) axq_q;		/* pending buffers */
95227328Sadrian	u_int			axq_depth;	/* SW queue depth */
96227328Sadrian	char			axq_name[48];	/* lock name */
97227328Sadrian	struct ath_node		*an;		/* pointer to parent */
98227328Sadrian	int			tid;		/* tid */
99227328Sadrian	int			ac;		/* which AC gets this trafic */
100227328Sadrian	int			hwq_depth;	/* how many buffers are on HW */
101227328Sadrian
102227328Sadrian	/*
103227328Sadrian	 * Entry on the ath_txq; when there's traffic
104227328Sadrian	 * to send
105227328Sadrian	 */
106227328Sadrian	TAILQ_ENTRY(ath_tid)	axq_qelem;
107227328Sadrian	int			sched;
108227328Sadrian	int			paused;	/* >0 if the TID has been paused */
109233908Sadrian	int			bar_wait;	/* waiting for BAR */
110233908Sadrian	int			bar_tx;		/* BAR TXed */
111227328Sadrian
112227328Sadrian	/*
113227328Sadrian	 * Is the TID being cleaned up after a transition
114227328Sadrian	 * from aggregation to non-aggregation?
115227328Sadrian	 * When this is set to 1, this TID will be paused
116227328Sadrian	 * and no further traffic will be queued until all
117227328Sadrian	 * the hardware packets pending for this TID have been
118227328Sadrian	 * TXed/completed; at which point (non-aggregation)
119227328Sadrian	 * traffic will resume being TXed.
120227328Sadrian	 */
121227328Sadrian	int			cleanup_inprogress;
122227328Sadrian	/*
123227328Sadrian	 * How many hardware-queued packets are
124227328Sadrian	 * waiting to be cleaned up.
125227328Sadrian	 * This is only valid if cleanup_inprogress is 1.
126227328Sadrian	 */
127227328Sadrian	int			incomp;
128227328Sadrian
129227328Sadrian	/*
130227328Sadrian	 * The following implements a ring representing
131227328Sadrian	 * the frames in the current BAW.
132227328Sadrian	 * To avoid copying the array content each time
133227328Sadrian	 * the BAW is moved, the baw_head/baw_tail point
134227328Sadrian	 * to the current BAW begin/end; when the BAW is
135227328Sadrian	 * shifted the head/tail of the array are also
136227328Sadrian	 * appropriately shifted.
137227328Sadrian	 */
138227328Sadrian	/* active tx buffers, beginning at current BAW */
139227328Sadrian	struct ath_buf		*tx_buf[ATH_TID_MAX_BUFS];
140227328Sadrian	/* where the baw head is in the array */
141227328Sadrian	int			baw_head;
142227328Sadrian	/* where the BAW tail is in the array */
143227328Sadrian	int			baw_tail;
144227328Sadrian};
145227328Sadrian
146138570Ssam/* driver-specific node state */
147116743Ssamstruct ath_node {
148119150Ssam	struct ieee80211_node an_node;	/* base class */
149178354Ssam	u_int8_t	an_mgmtrix;	/* min h/w rate index */
150178354Ssam	u_int8_t	an_mcastrix;	/* mcast h/w rate index */
151170530Ssam	struct ath_buf	*an_ff_buf[WME_NUM_AC]; /* ff staging area */
152227328Sadrian	struct ath_tid	an_tid[IEEE80211_TID_SIZE];	/* per-TID state */
153227328Sadrian	char		an_name[32];	/* eg "wlan0_a1" */
154227328Sadrian	struct mtx	an_mtx;		/* protecting the ath_node state */
155138570Ssam	/* variable-length rate control state follows */
156116743Ssam};
157138570Ssam#define	ATH_NODE(ni)	((struct ath_node *)(ni))
158138570Ssam#define	ATH_NODE_CONST(ni)	((const struct ath_node *)(ni))
159116743Ssam
160138570Ssam#define ATH_RSSI_LPF_LEN	10
161138570Ssam#define ATH_RSSI_DUMMY_MARKER	0x127
162138570Ssam#define ATH_EP_MUL(x, mul)	((x) * (mul))
163138570Ssam#define ATH_RSSI_IN(x)		(ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
164138570Ssam#define ATH_LPF_RSSI(x, y, len) \
165138570Ssam    ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
166138570Ssam#define ATH_RSSI_LPF(x, y) do {						\
167138570Ssam    if ((y) >= -20)							\
168138570Ssam    	x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);	\
169138570Ssam} while (0)
170184358Ssam#define	ATH_EP_RND(x,mul) \
171184358Ssam	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
172184358Ssam#define	ATH_RSSI(x)		ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
173138570Ssam
174116743Ssamstruct ath_buf {
175227344Sadrian	TAILQ_ENTRY(ath_buf)	bf_list;
176227328Sadrian	struct ath_buf *	bf_next;	/* next buffer in the aggregate */
177116743Ssam	int			bf_nseg;
178186904Ssam	uint16_t		bf_flags;	/* status flags (below) */
179116743Ssam	struct ath_desc		*bf_desc;	/* virtual addr of desc */
180165185Ssam	struct ath_desc_status	bf_status;	/* tx/rx status */
181116743Ssam	bus_addr_t		bf_daddr;	/* physical addr of desc */
182138570Ssam	bus_dmamap_t		bf_dmamap;	/* DMA map for mbuf chain */
183116743Ssam	struct mbuf		*bf_m;		/* mbuf for buf */
184116743Ssam	struct ieee80211_node	*bf_node;	/* pointer to the node */
185227328Sadrian	struct ath_desc		*bf_lastds;	/* last descriptor for comp status */
186227328Sadrian	struct ath_buf		*bf_last;	/* last buffer in aggregate, or self for non-aggregate */
187116743Ssam	bus_size_t		bf_mapsize;
188140438Ssam#define	ATH_MAX_SCATTER		ATH_TXDESC	/* max(tx,rx,beacon) desc's */
189116743Ssam	bus_dma_segment_t	bf_segs[ATH_MAX_SCATTER];
190227328Sadrian
191227328Sadrian	/* Completion function to call on TX complete (fail or not) */
192227328Sadrian	/*
193227328Sadrian	 * "fail" here is set to 1 if the queue entries were removed
194227328Sadrian	 * through a call to ath_tx_draintxq().
195227328Sadrian	 */
196227328Sadrian	void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail);
197227328Sadrian
198227328Sadrian	/* This state is kept to support software retries and aggregation */
199227328Sadrian	struct {
200227328Sadrian		int bfs_seqno;		/* sequence number of this packet */
201227328Sadrian		int bfs_retries;	/* retry count */
202227328Sadrian		uint16_t bfs_tid;	/* packet TID (or TID_MAX for no QoS) */
203227328Sadrian		uint16_t bfs_pri;	/* packet AC priority */
204227328Sadrian		struct ath_txq *bfs_txq;	/* eventual dest hardware TXQ */
205227328Sadrian		uint16_t bfs_pktdur;	/* packet duration (at current rate?) */
206227328Sadrian		uint16_t bfs_nframes;	/* number of frames in aggregate */
207227328Sadrian		uint16_t bfs_ndelim;	/* number of delims for padding */
208227328Sadrian
209234109Sadrian		u_int32_t bfs_aggr:1,		/* part of aggregate? */
210234109Sadrian		    bfs_aggrburst:1,	/* part of aggregate burst? */
211234109Sadrian		    bfs_isretried:1,	/* retried frame? */
212234109Sadrian		    bfs_dobaw:1,	/* actually check against BAW? */
213234109Sadrian		    bfs_addedbaw:1,	/* has been added to the BAW */
214234109Sadrian		    bfs_shpream:1,	/* use short preamble */
215234109Sadrian		    bfs_istxfrag:1,	/* is fragmented */
216234109Sadrian		    bfs_ismrr:1,	/* do multi-rate TX retry */
217234109Sadrian		    bfs_doprot:1,	/* do RTS/CTS based protection */
218234109Sadrian		    bfs_doratelookup:1,	/* do rate lookup before each TX */
219234109Sadrian		    bfs_need_seqno:1,	/* need to assign a seqno for aggr */
220234109Sadrian		    bfs_seqno_assigned:1;	/* seqno has been assigned */
221234109Sadrian
222227328Sadrian		int bfs_nfl;		/* next fragment length */
223227328Sadrian
224227328Sadrian		/*
225227328Sadrian		 * These fields are passed into the
226227328Sadrian		 * descriptor setup functions.
227227328Sadrian		 */
228227328Sadrian		HAL_PKT_TYPE bfs_atype;	/* packet type */
229227328Sadrian		int bfs_pktlen;		/* length of this packet */
230227328Sadrian		int bfs_hdrlen;		/* length of this packet header */
231227328Sadrian		uint16_t bfs_al;	/* length of aggregate */
232233966Sadrian		int bfs_txflags;	/* HAL (tx) descriptor flags */
233227328Sadrian		int bfs_txrate0;	/* first TX rate */
234227328Sadrian		int bfs_try0;		/* first try count */
235227328Sadrian		uint8_t bfs_ctsrate0;	/* Non-zero - use this as ctsrate */
236227328Sadrian		int bfs_keyix;		/* crypto key index */
237227328Sadrian		int bfs_txpower;	/* tx power */
238227328Sadrian		int bfs_txantenna;	/* TX antenna config */
239227328Sadrian		enum ieee80211_protmode bfs_protmode;
240227328Sadrian		HAL_11N_RATE_SERIES bfs_rc11n[ATH_RC_NUM];	/* 11n TX series */
241227328Sadrian		int bfs_ctsrate;	/* CTS rate */
242227328Sadrian		int bfs_ctsduration;	/* CTS duration (pre-11n NICs) */
243227328Sadrian		struct ath_rc_series bfs_rc[ATH_RC_NUM];	/* non-11n TX series */
244227328Sadrian	} bf_state;
245116743Ssam};
246227344Sadriantypedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead;
247116743Ssam
248186904Ssam#define	ATH_BUF_BUSY	0x00000002	/* (tx) desc owned by h/w */
249186904Ssam
250138570Ssam/*
251138570Ssam * DMA state for tx/rx descriptors.
252138570Ssam */
253138570Ssamstruct ath_descdma {
254138570Ssam	const char*		dd_name;
255138570Ssam	struct ath_desc		*dd_desc;	/* descriptors */
256138570Ssam	bus_addr_t		dd_desc_paddr;	/* physical addr of dd_desc */
257158298Ssam	bus_size_t		dd_desc_len;	/* size of dd_desc */
258138570Ssam	bus_dma_segment_t	dd_dseg;
259138570Ssam	bus_dma_tag_t		dd_dmat;	/* bus DMA tag */
260138570Ssam	bus_dmamap_t		dd_dmamap;	/* DMA map for descriptors */
261138570Ssam	struct ath_buf		*dd_bufptr;	/* associated buffers */
262138570Ssam};
263138570Ssam
264138570Ssam/*
265138570Ssam * Data transmit queue state.  One of these exists for each
266138570Ssam * hardware transmit queue.  Packets sent to us from above
267138570Ssam * are assigned to queues based on their priority.  Not all
268138570Ssam * devices support a complete set of hardware transmit queues.
269138570Ssam * For those devices the array sc_ac2q will map multiple
270138570Ssam * priorities to fewer hardware queues (typically all to one
271138570Ssam * hardware queue).
272138570Ssam */
273138570Ssamstruct ath_txq {
274227328Sadrian	struct ath_softc	*axq_softc;	/* Needed for scheduling */
275138570Ssam	u_int			axq_qnum;	/* hardware q number */
276178354Ssam#define	ATH_TXQ_SWQ	(HAL_NUM_TX_QUEUES+1)	/* qnum for s/w only queue */
277190579Ssam	u_int			axq_ac;		/* WME AC */
278186904Ssam	u_int			axq_flags;
279186904Ssam#define	ATH_TXQ_PUTPENDING	0x0001		/* ath_hal_puttxbuf pending */
280156073Ssam	u_int			axq_depth;	/* queue depth (stat only) */
281227328Sadrian	u_int			axq_aggr_depth;	/* how many aggregates are queued */
282138570Ssam	u_int			axq_intrcnt;	/* interrupt count */
283138570Ssam	u_int32_t		*axq_link;	/* link ptr in last TX desc */
284227344Sadrian	TAILQ_HEAD(axq_q_s, ath_buf)	axq_q;		/* transmit queue */
285138570Ssam	struct mtx		axq_lock;	/* lock on q and link */
286155482Ssam	char			axq_name[12];	/* e.g. "ath0_txq4" */
287227344Sadrian
288227328Sadrian	/* Per-TID traffic queue for software -> hardware TX */
289227328Sadrian	TAILQ_HEAD(axq_t_s,ath_tid)	axq_tidq;
290138570Ssam};
291138570Ssam
292227328Sadrian#define	ATH_NODE_LOCK(_an)		mtx_lock(&(_an)->an_mtx)
293227328Sadrian#define	ATH_NODE_UNLOCK(_an)		mtx_unlock(&(_an)->an_mtx)
294227328Sadrian#define	ATH_NODE_LOCK_ASSERT(_an)	mtx_assert(&(_an)->an_mtx, MA_OWNED)
295227328Sadrian
296155482Ssam#define	ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
297155482Ssam	snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
298155482Ssam		device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
299167252Ssam	mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
300161425Simp} while (0)
301138570Ssam#define	ATH_TXQ_LOCK_DESTROY(_tq)	mtx_destroy(&(_tq)->axq_lock)
302138570Ssam#define	ATH_TXQ_LOCK(_tq)		mtx_lock(&(_tq)->axq_lock)
303138570Ssam#define	ATH_TXQ_UNLOCK(_tq)		mtx_unlock(&(_tq)->axq_lock)
304138570Ssam#define	ATH_TXQ_LOCK_ASSERT(_tq)	mtx_assert(&(_tq)->axq_lock, MA_OWNED)
305227328Sadrian#define	ATH_TXQ_IS_LOCKED(_tq)		mtx_owned(&(_tq)->axq_lock)
306138570Ssam
307227344Sadrian#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \
308227344Sadrian	TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \
309227344Sadrian	(_tq)->axq_depth++; \
310227344Sadrian} while (0)
311138570Ssam#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
312227344Sadrian	TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
313138570Ssam	(_tq)->axq_depth++; \
314138570Ssam} while (0)
315227344Sadrian#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \
316227344Sadrian	TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \
317138570Ssam	(_tq)->axq_depth--; \
318138570Ssam} while (0)
319227344Sadrian#define	ATH_TXQ_LAST(_tq, _field)	TAILQ_LAST(&(_tq)->axq_q, _field)
320138570Ssam
321178354Ssamstruct ath_vap {
322178354Ssam	struct ieee80211vap av_vap;	/* base class */
323178354Ssam	int		av_bslot;	/* beacon slot index */
324178354Ssam	struct ath_buf	*av_bcbuf;	/* beacon buffer */
325178354Ssam	struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
326178354Ssam	struct ath_txq	av_mcastq;	/* buffered mcast s/w queue */
327178354Ssam
328178354Ssam	void		(*av_recv_mgmt)(struct ieee80211_node *,
329192468Ssam				struct mbuf *, int, int, int);
330178354Ssam	int		(*av_newstate)(struct ieee80211vap *,
331178354Ssam				enum ieee80211_state, int);
332178354Ssam	void		(*av_bmiss)(struct ieee80211vap *);
333178354Ssam};
334178354Ssam#define	ATH_VAP(vap)	((struct ath_vap *)(vap))
335178354Ssam
336155491Ssamstruct taskqueue;
337155486Ssamstruct ath_tx99;
338155486Ssam
339227328Sadrian/*
340227328Sadrian * Whether to reset the TX/RX queue with or without
341227328Sadrian * a queue flush.
342227328Sadrian */
343227328Sadriantypedef enum {
344227328Sadrian	ATH_RESET_DEFAULT = 0,
345227328Sadrian	ATH_RESET_NOLOSS = 1,
346227328Sadrian	ATH_RESET_FULL = 2,
347227328Sadrian} ATH_RESET_TYPE;
348227328Sadrian
349116743Ssamstruct ath_softc {
350147256Sbrooks	struct ifnet		*sc_ifp;	/* interface common */
351138570Ssam	struct ath_stats	sc_stats;	/* interface statistics */
352227328Sadrian	struct ath_tx_aggr_stats	sc_aggr_stats;
353234090Sadrian	struct ath_intr_stats	sc_intr_stats;
354235491Sadrian	uint64_t		sc_debug;
355178354Ssam	int			sc_nvaps;	/* # vaps */
356178354Ssam	int			sc_nstavaps;	/* # station vaps */
357195807Ssam	int			sc_nmeshvaps;	/* # mbss vaps */
358178354Ssam	u_int8_t		sc_hwbssidmask[IEEE80211_ADDR_LEN];
359178354Ssam	u_int8_t		sc_nbssid0;	/* # vap's using base mac */
360178354Ssam	uint32_t		sc_bssidmask;	/* bssid mask */
361178354Ssam
362227328Sadrian	void 			(*sc_node_cleanup)(struct ieee80211_node *);
363138570Ssam	void 			(*sc_node_free)(struct ieee80211_node *);
364116743Ssam	device_t		sc_dev;
365159290Ssam	HAL_BUS_TAG		sc_st;		/* bus space tag */
366159290Ssam	HAL_BUS_HANDLE		sc_sh;		/* bus space handle */
367116743Ssam	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
368116743Ssam	struct mtx		sc_mtx;		/* master lock (recursive) */
369227328Sadrian	struct mtx		sc_pcu_mtx;	/* PCU access mutex */
370227328Sadrian	char			sc_pcu_mtx_name[32];
371155491Ssam	struct taskqueue	*sc_tq;		/* private task queue */
372116743Ssam	struct ath_hal		*sc_ah;		/* Atheros HAL */
373138570Ssam	struct ath_ratectrl	*sc_rc;		/* tx rate control support */
374155486Ssam	struct ath_tx99		*sc_tx99;	/* tx99 adjunct state */
375138570Ssam	void			(*sc_setdefantenna)(struct ath_softc *, u_int);
376178354Ssam	unsigned int		sc_invalid  : 1,/* disable hardware accesses */
377178354Ssam				sc_mrretry  : 1,/* multi-rate retry support */
378178354Ssam				sc_softled  : 1,/* enable LED gpio status */
379228891Sadrian				sc_hardled  : 1,/* enable MAC LED status */
380178354Ssam				sc_splitmic : 1,/* split TKIP MIC keys */
381178354Ssam				sc_needmib  : 1,/* enable MIB stats intr */
382178354Ssam				sc_diversity: 1,/* enable rx diversity */
383178354Ssam				sc_hasveol  : 1,/* tx VEOL support */
384178354Ssam				sc_ledstate : 1,/* LED on/off state */
385178354Ssam				sc_blinking : 1,/* LED blink operation active */
386178354Ssam				sc_mcastkey : 1,/* mcast key cache search */
387178354Ssam				sc_scanning : 1,/* scanning active */
388155496Ssam				sc_syncbeacon:1,/* sync/resync beacon timers */
389178354Ssam				sc_hasclrkey: 1,/* CLR key supported */
390165571Ssam				sc_xchanmode: 1,/* extended channel mode */
391170530Ssam				sc_outdoor  : 1,/* outdoor operation */
392178354Ssam				sc_dturbo   : 1,/* dynamic turbo in use */
393178354Ssam				sc_hasbmask : 1,/* bssid mask support */
394195618Srpaulo				sc_hasbmatch: 1,/* bssid match disable support*/
395178354Ssam				sc_hastsfadd: 1,/* tsf adjust support */
396178354Ssam				sc_beacons  : 1,/* beacons running */
397178354Ssam				sc_swbmiss  : 1,/* sta mode using sw bmiss */
398178354Ssam				sc_stagbeacons:1,/* use staggered beacons */
399179401Ssam				sc_wmetkipmic:1,/* can do WME+TKIP MIC */
400185744Ssam				sc_resume_up: 1,/* on resume, start all vaps */
401186904Ssam				sc_tdma	    : 1,/* TDMA in use */
402189380Ssam				sc_setcca   : 1,/* set/clr CCA with TDMA */
403220324Sadrian				sc_resetcal : 1,/* reset cal state next trip */
404224588Sadrian				sc_rxslink  : 1,/* do self-linked final descriptor */
405225444Sadrian				sc_rxtsf32  : 1;/* RX dec TSF is 32 bits */
406178751Ssam	uint32_t		sc_eerd;	/* regdomain from EEPROM */
407178751Ssam	uint32_t		sc_eecc;	/* country code from EEPROM */
408116743Ssam						/* rate tables */
409188783Ssam	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
410116743Ssam	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
411116743Ssam	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
412155490Ssam	HAL_OPMODE		sc_opmode;	/* current operating mode */
413138570Ssam	u_int16_t		sc_curtxpow;	/* current tx power limit */
414170530Ssam	u_int16_t		sc_curaid;	/* current association id */
415187831Ssam	struct ieee80211_channel *sc_curchan;	/* current installed channel */
416170530Ssam	u_int8_t		sc_curbssid[IEEE80211_ADDR_LEN];
417116743Ssam	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
418140432Ssam	struct {
419140432Ssam		u_int8_t	ieeerate;	/* IEEE rate */
420140761Ssam		u_int8_t	rxflags;	/* radiotap rx flags */
421140761Ssam		u_int8_t	txflags;	/* radiotap tx flags */
422140432Ssam		u_int16_t	ledon;		/* softled on time */
423140432Ssam		u_int16_t	ledoff;		/* softled off time */
424140432Ssam	} sc_hwmap[32];				/* h/w rate ix mappings */
425138570Ssam	u_int8_t		sc_protrix;	/* protection rate index */
426170530Ssam	u_int8_t		sc_lastdatarix;	/* last data frame rate index */
427155483Ssam	u_int			sc_mcastrate;	/* ieee rate for mcastrateix */
428170530Ssam	u_int			sc_fftxqmin;	/* min frames before staging */
429170530Ssam	u_int			sc_fftxqmax;	/* max frames before drop */
430138570Ssam	u_int			sc_txantenna;	/* tx antenna (fixed or auto) */
431227346Sadrian
432116743Ssam	HAL_INT			sc_imask;	/* interrupt mask copy */
433227651Sadrian
434227346Sadrian	/*
435227346Sadrian	 * These are modified in the interrupt handler as well as
436227346Sadrian	 * the task queues and other contexts. Thus these must be
437227346Sadrian	 * protected by a mutex, or they could clash.
438227346Sadrian	 *
439227346Sadrian	 * For now, access to these is behind the ATH_LOCK,
440227346Sadrian	 * just to save time.
441227346Sadrian	 */
442227346Sadrian	uint32_t		sc_txq_active;	/* bitmap of active TXQs */
443227346Sadrian	uint32_t		sc_kickpcu;	/* whether to kick the PCU */
444227651Sadrian	uint32_t		sc_rxproc_cnt;	/* In RX processing */
445227651Sadrian	uint32_t		sc_txproc_cnt;	/* In TX processing */
446227651Sadrian	uint32_t		sc_txstart_cnt;	/* In TX output (raw/start) */
447227651Sadrian	uint32_t		sc_inreset_cnt;	/* In active reset/chanchange */
448227651Sadrian	uint32_t		sc_txrx_cnt;	/* refcount on stop/start'ing TX */
449227651Sadrian	uint32_t		sc_intr_cnt;	/* refcount on interrupt handling */
450227346Sadrian
451138570Ssam	u_int			sc_keymax;	/* size of key cache */
452147057Ssam	u_int8_t		sc_keymap[ATH_KEYBYTES];/* key use bit map */
453116743Ssam
454228891Sadrian	/*
455228891Sadrian	 * Software based LED blinking
456228891Sadrian	 */
457140432Ssam	u_int			sc_ledpin;	/* GPIO pin for driving LED */
458140432Ssam	u_int			sc_ledon;	/* pin setting for LED on */
459140432Ssam	u_int			sc_ledidle;	/* idle polling interval */
460140432Ssam	int			sc_ledevent;	/* time of last LED event */
461184368Ssam	u_int8_t		sc_txrix;	/* current tx rate for LED */
462140432Ssam	u_int16_t		sc_ledoff;	/* off time for current blink */
463140432Ssam	struct callout		sc_ledtimer;	/* led off timer */
464138570Ssam
465228891Sadrian	/*
466228891Sadrian	 * Hardware based LED blinking
467228891Sadrian	 */
468228891Sadrian	int			sc_led_pwr_pin;	/* MAC power LED GPIO pin */
469228891Sadrian	int			sc_led_net_pin;	/* MAC network LED GPIO pin */
470228891Sadrian
471155515Ssam	u_int			sc_rfsilentpin;	/* GPIO pin for rfkill int */
472155515Ssam	u_int			sc_rfsilentpol;	/* pin setting for rfkill on */
473155515Ssam
474178354Ssam	struct ath_descdma	sc_rxdma;	/* RX descriptors */
475138570Ssam	ath_bufhead		sc_rxbuf;	/* receive buffer */
476170530Ssam	struct mbuf		*sc_rxpending;	/* pending receive data */
477116743Ssam	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
478116743Ssam	struct task		sc_rxtask;	/* rx int processing */
479138570Ssam	u_int8_t		sc_defant;	/* current default antenna */
480138570Ssam	u_int8_t		sc_rxotherant;	/* rx's on non-default antenna*/
481155492Ssam	u_int64_t		sc_lastrx;	/* tsf at last rx'd frame */
482192468Ssam	struct ath_rx_status	*sc_lastrs;	/* h/w status of last rx */
483192468Ssam	struct ath_rx_radiotap_header sc_rx_th;
484192468Ssam	int			sc_rx_th_len;
485192468Ssam	u_int			sc_monpass;	/* frames to pass in mon.mode */
486116743Ssam
487138570Ssam	struct ath_descdma	sc_txdma;	/* TX descriptors */
488138570Ssam	ath_bufhead		sc_txbuf;	/* transmit buffer */
489138570Ssam	struct mtx		sc_txbuflock;	/* txbuf lock */
490155482Ssam	char			sc_txname[12];	/* e.g. "ath0_buf" */
491138570Ssam	u_int			sc_txqsetup;	/* h/w queues setup */
492138570Ssam	u_int			sc_txintrperiod;/* tx interrupt batching */
493138570Ssam	struct ath_txq		sc_txq[HAL_NUM_TX_QUEUES];
494138570Ssam	struct ath_txq		*sc_ac2q[5];	/* WME AC -> h/w q map */
495116743Ssam	struct task		sc_txtask;	/* tx int processing */
496233673Sadrian	struct task		sc_txqtask;	/* tx proc processing */
497189605Ssam	int			sc_wd_timer;	/* count down for wd timer */
498189605Ssam	struct callout		sc_wd_ch;	/* tx watchdog timer */
499192468Ssam	struct ath_tx_radiotap_header sc_tx_th;
500192468Ssam	int			sc_tx_th_len;
501116743Ssam
502138570Ssam	struct ath_descdma	sc_bdma;	/* beacon descriptors */
503138570Ssam	ath_bufhead		sc_bbuf;	/* beacon buffers */
504116743Ssam	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
505138570Ssam	u_int			sc_bmisscount;	/* missed beacon transmits */
506138570Ssam	u_int32_t		sc_ant_tx[8];	/* recent tx frames/antenna */
507138570Ssam	struct ath_txq		*sc_cabq;	/* tx q for cab frames */
508116743Ssam	struct task		sc_bmisstask;	/* bmiss int processing */
509138570Ssam	struct task		sc_bstucktask;	/* stuck beacon processing */
510232163Sadrian	struct task		sc_resettask;	/* interface reset task */
511234369Sadrian	struct task		sc_fataltask;	/* fatal task */
512138570Ssam	enum {
513138570Ssam		OK,				/* no change needed */
514138570Ssam		UPDATE,				/* update pending */
515138570Ssam		COMMIT				/* beacon sent, commit change */
516138570Ssam	} sc_updateslot;			/* slot time update fsm */
517178354Ssam	int			sc_slotupdate;	/* slot to advance fsm */
518178354Ssam	struct ieee80211vap	*sc_bslot[ATH_BCBUF];
519178354Ssam	int			sc_nbcnvaps;	/* # vaps with beacons */
520116743Ssam
521116743Ssam	struct callout		sc_cal_ch;	/* callout handle for cals */
522185744Ssam	int			sc_lastlongcal;	/* last long cal completed */
523185744Ssam	int			sc_lastcalreset;/* last cal reset done */
524217684Sadrian	int			sc_lastani;	/* last ANI poll */
525217684Sadrian	int			sc_lastshortcal;	/* last short calibration */
526217684Sadrian	HAL_BOOL		sc_doresetcal;	/* Yes, we're doing a reset cal atm */
527155485Ssam	HAL_NODE_STATS		sc_halstats;	/* station-mode rssi stats */
528186904Ssam	u_int			sc_tdmadbaprep;	/* TDMA DBA prep time */
529186904Ssam	u_int			sc_tdmaswbaprep;/* TDMA SWBA prep time */
530186904Ssam	u_int			sc_tdmaswba;	/* TDMA SWBA counter */
531186904Ssam	u_int32_t		sc_tdmabintval;	/* TDMA beacon interval (TU) */
532186904Ssam	u_int32_t		sc_tdmaguard;	/* TDMA guard time (usec) */
533186904Ssam	u_int			sc_tdmaslotlen;	/* TDMA slot length (usec) */
534186904Ssam	u_int32_t		sc_avgtsfdeltap;/* TDMA slot adjust (+) */
535186904Ssam	u_int32_t		sc_avgtsfdeltam;/* TDMA slot adjust (-) */
536217624Sadrian	uint16_t		*sc_eepromdata;	/* Local eeprom data, if AR9100 */
537218151Sadrian	int			sc_txchainmask;	/* currently configured TX chainmask */
538218151Sadrian	int			sc_rxchainmask;	/* currently configured RX chainmask */
539233967Sadrian	int			sc_rts_aggr_limit;	/* TX limit on RTS aggregates */
540222585Sadrian
541232764Sadrian	/* Queue limits */
542232764Sadrian
543227328Sadrian	/*
544232764Sadrian	 * To avoid queue starvation in congested conditions,
545232764Sadrian	 * these parameters tune the maximum number of frames
546232764Sadrian	 * queued to the data/mcastq before they're dropped.
547232764Sadrian	 *
548232764Sadrian	 * This is to prevent:
549232764Sadrian	 * + a single destination overwhelming everything, including
550232764Sadrian	 *   management/multicast frames;
551232764Sadrian	 * + multicast frames overwhelming everything (when the
552232764Sadrian	 *   air is sufficiently busy that cabq can't drain.)
553232764Sadrian	 *
554232764Sadrian	 * These implement:
555232764Sadrian	 * + data_minfree is the maximum number of free buffers
556232764Sadrian	 *   overall to successfully allow a data frame.
557232764Sadrian	 *
558232794Sadrian	 * + mcastq_maxdepth is the maximum depth allowed of the cabq.
559232764Sadrian	 */
560232764Sadrian	int			sc_txq_data_minfree;
561232764Sadrian	int			sc_txq_mcastq_maxdepth;
562232764Sadrian
563232764Sadrian	/*
564227328Sadrian	 * Aggregation twiddles
565227328Sadrian	 *
566227328Sadrian	 * hwq_limit:	how busy to keep the hardware queue - don't schedule
567227328Sadrian	 *		further packets to the hardware, regardless of the TID
568227328Sadrian	 * tid_hwq_lo:	how low the per-TID hwq count has to be before the
569227328Sadrian	 *		TID will be scheduled again
570227328Sadrian	 * tid_hwq_hi:	how many frames to queue to the HWQ before the TID
571227328Sadrian	 *		stops being scheduled.
572227328Sadrian	 */
573227328Sadrian	int			sc_hwq_limit;
574227328Sadrian	int			sc_tid_hwq_lo;
575227328Sadrian	int			sc_tid_hwq_hi;
576227328Sadrian
577222585Sadrian	/* DFS related state */
578222585Sadrian	void			*sc_dfs;	/* Used by an optional DFS module */
579222668Sadrian	int			sc_dodfs;	/* Whether to enable DFS rx filter bits */
580222585Sadrian	struct task		sc_dfstask;	/* DFS processing task */
581227328Sadrian
582227328Sadrian	/* TX AMPDU handling */
583227328Sadrian	int			(*sc_addba_request)(struct ieee80211_node *,
584227328Sadrian				    struct ieee80211_tx_ampdu *, int, int, int);
585227328Sadrian	int			(*sc_addba_response)(struct ieee80211_node *,
586227328Sadrian				    struct ieee80211_tx_ampdu *, int, int, int);
587227328Sadrian	void			(*sc_addba_stop)(struct ieee80211_node *,
588227328Sadrian				    struct ieee80211_tx_ampdu *);
589227328Sadrian	void			(*sc_addba_response_timeout)
590227328Sadrian				    (struct ieee80211_node *,
591227328Sadrian				    struct ieee80211_tx_ampdu *);
592227328Sadrian	void			(*sc_bar_response)(struct ieee80211_node *ni,
593227328Sadrian				    struct ieee80211_tx_ampdu *tap,
594227328Sadrian				    int status);
595116743Ssam};
596116743Ssam
597121100Ssam#define	ATH_LOCK_INIT(_sc) \
598121100Ssam	mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
599167252Ssam		 NULL, MTX_DEF | MTX_RECURSE)
600121100Ssam#define	ATH_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_mtx)
601121100Ssam#define	ATH_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
602121100Ssam#define	ATH_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
603121100Ssam#define	ATH_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
604227651Sadrian#define	ATH_UNLOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
605121100Ssam
606227328Sadrian/*
607227328Sadrian * The PCU lock is non-recursive and should be treated as a spinlock.
608227328Sadrian * Although currently the interrupt code is run in netisr context and
609227328Sadrian * doesn't require this, this may change in the future.
610227328Sadrian * Please keep this in mind when protecting certain code paths
611227328Sadrian * with the PCU lock.
612227328Sadrian *
613227328Sadrian * The PCU lock is used to serialise access to the PCU so things such
614227328Sadrian * as TX, RX, state change (eg channel change), channel reset and updates
615227328Sadrian * from interrupt context (eg kickpcu, txqactive bits) do not clash.
616227328Sadrian *
617227328Sadrian * Although the current single-thread taskqueue mechanism protects the
618227328Sadrian * majority of these situations by simply serialising them, there are
619227328Sadrian * a few others which occur at the same time. These include the TX path
620227328Sadrian * (which only acquires ATH_LOCK when recycling buffers to the free list),
621227328Sadrian * ath_set_channel, the channel scanning API and perhaps quite a bit more.
622227328Sadrian */
623227328Sadrian#define	ATH_PCU_LOCK_INIT(_sc) do {\
624227328Sadrian	snprintf((_sc)->sc_pcu_mtx_name,				\
625227328Sadrian	    sizeof((_sc)->sc_pcu_mtx_name),				\
626227328Sadrian	    "%s PCU lock",						\
627227328Sadrian	    device_get_nameunit((_sc)->sc_dev));			\
628227328Sadrian	mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name,		\
629227328Sadrian		 NULL, MTX_DEF);					\
630227328Sadrian	} while (0)
631227328Sadrian#define	ATH_PCU_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_pcu_mtx)
632227328Sadrian#define	ATH_PCU_LOCK(_sc)		mtx_lock(&(_sc)->sc_pcu_mtx)
633227328Sadrian#define	ATH_PCU_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_pcu_mtx)
634227328Sadrian#define	ATH_PCU_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_pcu_mtx,	\
635227328Sadrian		MA_OWNED)
636227651Sadrian#define	ATH_PCU_UNLOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_pcu_mtx,	\
637227651Sadrian		MA_NOTOWNED)
638227328Sadrian
639138570Ssam#define	ATH_TXQ_SETUP(sc, i)	((sc)->sc_txqsetup & (1<<i))
640138570Ssam
641155482Ssam#define	ATH_TXBUF_LOCK_INIT(_sc) do { \
642155482Ssam	snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
643155482Ssam		device_get_nameunit((_sc)->sc_dev)); \
644167252Ssam	mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
645155482Ssam} while (0)
646121100Ssam#define	ATH_TXBUF_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txbuflock)
647121100Ssam#define	ATH_TXBUF_LOCK(_sc)		mtx_lock(&(_sc)->sc_txbuflock)
648121100Ssam#define	ATH_TXBUF_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_txbuflock)
649121100Ssam#define	ATH_TXBUF_LOCK_ASSERT(_sc) \
650121100Ssam	mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
651121100Ssam
652116743Ssamint	ath_attach(u_int16_t, struct ath_softc *);
653116743Ssamint	ath_detach(struct ath_softc *);
654116743Ssamvoid	ath_resume(struct ath_softc *);
655116743Ssamvoid	ath_suspend(struct ath_softc *);
656116743Ssamvoid	ath_shutdown(struct ath_softc *);
657116743Ssamvoid	ath_intr(void *);
658116743Ssam
659116743Ssam/*
660116743Ssam * HAL definitions to comply with local coding convention.
661116743Ssam */
662138570Ssam#define	ath_hal_detach(_ah) \
663138570Ssam	((*(_ah)->ah_detach)((_ah)))
664116743Ssam#define	ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
665116743Ssam	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
666186904Ssam#define	ath_hal_macversion(_ah) \
667186904Ssam	(((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
668116743Ssam#define	ath_hal_getratetable(_ah, _mode) \
669116743Ssam	((*(_ah)->ah_getRateTable)((_ah), (_mode)))
670116743Ssam#define	ath_hal_getmac(_ah, _mac) \
671116743Ssam	((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
672138570Ssam#define	ath_hal_setmac(_ah, _mac) \
673138570Ssam	((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
674178354Ssam#define	ath_hal_getbssidmask(_ah, _mask) \
675178354Ssam	((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
676178354Ssam#define	ath_hal_setbssidmask(_ah, _mask) \
677178354Ssam	((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
678116743Ssam#define	ath_hal_intrset(_ah, _mask) \
679116743Ssam	((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
680116743Ssam#define	ath_hal_intrget(_ah) \
681116743Ssam	((*(_ah)->ah_getInterrupts)((_ah)))
682116743Ssam#define	ath_hal_intrpend(_ah) \
683116743Ssam	((*(_ah)->ah_isInterruptPending)((_ah)))
684116743Ssam#define	ath_hal_getisr(_ah, _pmask) \
685116743Ssam	((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
686116743Ssam#define	ath_hal_updatetxtriglevel(_ah, _inc) \
687116743Ssam	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
688155515Ssam#define	ath_hal_setpower(_ah, _mode) \
689155515Ssam	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
690138570Ssam#define	ath_hal_keycachesize(_ah) \
691138570Ssam	((*(_ah)->ah_getKeyCacheSize)((_ah)))
692116743Ssam#define	ath_hal_keyreset(_ah, _ix) \
693116743Ssam	((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
694138570Ssam#define	ath_hal_keyset(_ah, _ix, _pk, _mac) \
695138570Ssam	((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
696116743Ssam#define	ath_hal_keyisvalid(_ah, _ix) \
697116743Ssam	(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
698116743Ssam#define	ath_hal_keysetmac(_ah, _ix, _mac) \
699116743Ssam	((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
700116743Ssam#define	ath_hal_getrxfilter(_ah) \
701116743Ssam	((*(_ah)->ah_getRxFilter)((_ah)))
702116743Ssam#define	ath_hal_setrxfilter(_ah, _filter) \
703116743Ssam	((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
704116743Ssam#define	ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
705116743Ssam	((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
706116743Ssam#define	ath_hal_waitforbeacon(_ah, _bf) \
707116743Ssam	((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
708116743Ssam#define	ath_hal_putrxbuf(_ah, _bufaddr) \
709116743Ssam	((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
710186904Ssam/* NB: common across all chips */
711186904Ssam#define	AR_TSF_L32	0x804c	/* MAC local clock lower 32 bits */
712116743Ssam#define	ath_hal_gettsf32(_ah) \
713186904Ssam	OS_REG_READ(_ah, AR_TSF_L32)
714116743Ssam#define	ath_hal_gettsf64(_ah) \
715116743Ssam	((*(_ah)->ah_getTsf64)((_ah)))
716116743Ssam#define	ath_hal_resettsf(_ah) \
717116743Ssam	((*(_ah)->ah_resetTsf)((_ah)))
718116743Ssam#define	ath_hal_rxena(_ah) \
719116743Ssam	((*(_ah)->ah_enableReceive)((_ah)))
720116743Ssam#define	ath_hal_puttxbuf(_ah, _q, _bufaddr) \
721116743Ssam	((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
722116743Ssam#define	ath_hal_gettxbuf(_ah, _q) \
723116743Ssam	((*(_ah)->ah_getTxDP)((_ah), (_q)))
724138570Ssam#define	ath_hal_numtxpending(_ah, _q) \
725138570Ssam	((*(_ah)->ah_numTxPending)((_ah), (_q)))
726116743Ssam#define	ath_hal_getrxbuf(_ah) \
727116743Ssam	((*(_ah)->ah_getRxDP)((_ah)))
728116743Ssam#define	ath_hal_txstart(_ah, _q) \
729116743Ssam	((*(_ah)->ah_startTxDma)((_ah), (_q)))
730116743Ssam#define	ath_hal_setchannel(_ah, _chan) \
731116743Ssam	((*(_ah)->ah_setChannel)((_ah), (_chan)))
732155515Ssam#define	ath_hal_calibrate(_ah, _chan, _iqcal) \
733155515Ssam	((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
734185744Ssam#define	ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
735185744Ssam	((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
736185744Ssam#define	ath_hal_calreset(_ah, _chan) \
737185744Ssam	((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
738116743Ssam#define	ath_hal_setledstate(_ah, _state) \
739116743Ssam	((*(_ah)->ah_setLedState)((_ah), (_state)))
740138570Ssam#define	ath_hal_beaconinit(_ah, _nextb, _bperiod) \
741138570Ssam	((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
742116743Ssam#define	ath_hal_beaconreset(_ah) \
743116743Ssam	((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
744186904Ssam#define	ath_hal_beaconsettimers(_ah, _bt) \
745186904Ssam	((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
746138570Ssam#define	ath_hal_beacontimers(_ah, _bs) \
747138570Ssam	((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
748225444Sadrian#define	ath_hal_getnexttbtt(_ah) \
749225444Sadrian	((*(_ah)->ah_getNextTBTT)((_ah)))
750116743Ssam#define	ath_hal_setassocid(_ah, _bss, _associd) \
751138570Ssam	((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
752138570Ssam#define	ath_hal_phydisable(_ah) \
753138570Ssam	((*(_ah)->ah_phyDisable)((_ah)))
754138570Ssam#define	ath_hal_setopmode(_ah) \
755138570Ssam	((*(_ah)->ah_setPCUConfig)((_ah)))
756116743Ssam#define	ath_hal_stoptxdma(_ah, _qnum) \
757116743Ssam	((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
758116743Ssam#define	ath_hal_stoppcurecv(_ah) \
759116743Ssam	((*(_ah)->ah_stopPcuReceive)((_ah)))
760116743Ssam#define	ath_hal_startpcurecv(_ah) \
761116743Ssam	((*(_ah)->ah_startPcuReceive)((_ah)))
762116743Ssam#define	ath_hal_stopdmarecv(_ah) \
763116743Ssam	((*(_ah)->ah_stopDmaReceive)((_ah)))
764138570Ssam#define	ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
765138570Ssam	((*(_ah)->ah_getDiagState)((_ah), (_id), \
766138570Ssam		(_indata), (_insize), (_outdata), (_outsize)))
767155732Ssam#define	ath_hal_getfatalstate(_ah, _outdata, _outsize) \
768170530Ssam	ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
769116743Ssam#define	ath_hal_setuptxqueue(_ah, _type, _irq) \
770116743Ssam	((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
771116743Ssam#define	ath_hal_resettxqueue(_ah, _q) \
772116743Ssam	((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
773116743Ssam#define	ath_hal_releasetxqueue(_ah, _q) \
774116743Ssam	((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
775138570Ssam#define	ath_hal_gettxqueueprops(_ah, _q, _qi) \
776138570Ssam	((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
777138570Ssam#define	ath_hal_settxqueueprops(_ah, _q, _qi) \
778138570Ssam	((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
779186904Ssam/* NB: common across all chips */
780186904Ssam#define	AR_Q_TXE	0x0840	/* MAC Transmit Queue enable */
781186904Ssam#define	ath_hal_txqenabled(_ah, _qnum) \
782186904Ssam	(OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
783116743Ssam#define	ath_hal_getrfgain(_ah) \
784116743Ssam	((*(_ah)->ah_getRfGain)((_ah)))
785138570Ssam#define	ath_hal_getdefantenna(_ah) \
786138570Ssam	((*(_ah)->ah_getDefAntenna)((_ah)))
787138570Ssam#define	ath_hal_setdefantenna(_ah, _ant) \
788138570Ssam	((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
789155515Ssam#define	ath_hal_rxmonitor(_ah, _arg, _chan) \
790155515Ssam	((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
791217684Sadrian#define	ath_hal_ani_poll(_ah, _chan) \
792217684Sadrian	((*(_ah)->ah_aniPoll)((_ah), (_chan)))
793138570Ssam#define	ath_hal_mibevent(_ah, _stats) \
794138570Ssam	((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
795138570Ssam#define	ath_hal_setslottime(_ah, _us) \
796138570Ssam	((*(_ah)->ah_setSlotTime)((_ah), (_us)))
797138570Ssam#define	ath_hal_getslottime(_ah) \
798138570Ssam	((*(_ah)->ah_getSlotTime)((_ah)))
799138570Ssam#define	ath_hal_setacktimeout(_ah, _us) \
800138570Ssam	((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
801138570Ssam#define	ath_hal_getacktimeout(_ah) \
802138570Ssam	((*(_ah)->ah_getAckTimeout)((_ah)))
803138570Ssam#define	ath_hal_setctstimeout(_ah, _us) \
804138570Ssam	((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
805138570Ssam#define	ath_hal_getctstimeout(_ah) \
806138570Ssam	((*(_ah)->ah_getCTSTimeout)((_ah)))
807138570Ssam#define	ath_hal_getcapability(_ah, _cap, _param, _result) \
808138570Ssam	((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
809138570Ssam#define	ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
810138570Ssam	((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
811138570Ssam#define	ath_hal_ciphersupported(_ah, _cipher) \
812138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
813138570Ssam#define	ath_hal_getregdomain(_ah, _prd) \
814155515Ssam	(ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
815155489Ssam#define	ath_hal_setregdomain(_ah, _rd) \
816184369Ssam	ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
817138570Ssam#define	ath_hal_getcountrycode(_ah, _pcc) \
818138570Ssam	(*(_pcc) = (_ah)->ah_countryCode)
819178354Ssam#define	ath_hal_gettkipmic(_ah) \
820178354Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
821178354Ssam#define	ath_hal_settkipmic(_ah, _v) \
822178354Ssam	ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
823162410Ssam#define	ath_hal_hastkipsplit(_ah) \
824138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
825162410Ssam#define	ath_hal_gettkipsplit(_ah) \
826162410Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
827162410Ssam#define	ath_hal_settkipsplit(_ah, _v) \
828162410Ssam	ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
829178354Ssam#define	ath_hal_haswmetkipmic(_ah) \
830178354Ssam	(ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
831138570Ssam#define	ath_hal_hwphycounters(_ah) \
832138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
833138570Ssam#define	ath_hal_hasdiversity(_ah) \
834138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
835138570Ssam#define	ath_hal_getdiversity(_ah) \
836138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
837138570Ssam#define	ath_hal_setdiversity(_ah, _v) \
838138570Ssam	ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
839166954Ssam#define	ath_hal_getantennaswitch(_ah) \
840166954Ssam	((*(_ah)->ah_getAntennaSwitch)((_ah)))
841166954Ssam#define	ath_hal_setantennaswitch(_ah, _v) \
842166954Ssam	((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
843138570Ssam#define	ath_hal_getdiag(_ah, _pv) \
844138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
845138570Ssam#define	ath_hal_setdiag(_ah, _v) \
846138570Ssam	ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
847138570Ssam#define	ath_hal_getnumtxqueues(_ah, _pv) \
848138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
849138570Ssam#define	ath_hal_hasveol(_ah) \
850138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
851138570Ssam#define	ath_hal_hastxpowlimit(_ah) \
852138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
853138570Ssam#define	ath_hal_settxpowlimit(_ah, _pow) \
854138570Ssam	((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
855138570Ssam#define	ath_hal_gettxpowlimit(_ah, _ppow) \
856138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
857138570Ssam#define	ath_hal_getmaxtxpow(_ah, _ppow) \
858138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
859138570Ssam#define	ath_hal_gettpscale(_ah, _scale) \
860138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
861138570Ssam#define	ath_hal_settpscale(_ah, _v) \
862138570Ssam	ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
863138570Ssam#define	ath_hal_hastpc(_ah) \
864138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
865138570Ssam#define	ath_hal_gettpc(_ah) \
866138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
867138570Ssam#define	ath_hal_settpc(_ah, _v) \
868138570Ssam	ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
869138570Ssam#define	ath_hal_hasbursting(_ah) \
870138570Ssam	(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
871203683Srpaulo#define	ath_hal_setmcastkeysearch(_ah, _v) \
872203683Srpaulo	ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
873147057Ssam#define	ath_hal_hasmcastkeysearch(_ah) \
874147057Ssam	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
875147057Ssam#define	ath_hal_getmcastkeysearch(_ah) \
876147057Ssam	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
877170530Ssam#define	ath_hal_hasfastframes(_ah) \
878170530Ssam	(ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
879178354Ssam#define	ath_hal_hasbssidmask(_ah) \
880178354Ssam	(ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
881195114Ssam#define	ath_hal_hasbssidmatch(_ah) \
882195114Ssam	(ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
883178354Ssam#define	ath_hal_hastsfadjust(_ah) \
884178354Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
885178354Ssam#define	ath_hal_gettsfadjust(_ah) \
886178354Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
887178354Ssam#define	ath_hal_settsfadjust(_ah, _onoff) \
888178354Ssam	ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
889155515Ssam#define	ath_hal_hasrfsilent(_ah) \
890155515Ssam	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
891155515Ssam#define	ath_hal_getrfkill(_ah) \
892155515Ssam	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
893155515Ssam#define	ath_hal_setrfkill(_ah, _onoff) \
894155515Ssam	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
895155515Ssam#define	ath_hal_getrfsilent(_ah, _prfsilent) \
896155515Ssam	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
897155515Ssam#define	ath_hal_setrfsilent(_ah, _rfsilent) \
898155515Ssam	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
899155515Ssam#define	ath_hal_gettpack(_ah, _ptpack) \
900155515Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
901155515Ssam#define	ath_hal_settpack(_ah, _tpack) \
902155515Ssam	ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
903155515Ssam#define	ath_hal_gettpcts(_ah, _ptpcts) \
904155515Ssam	(ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
905155515Ssam#define	ath_hal_settpcts(_ah, _tpcts) \
906155515Ssam	ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
907184354Ssam#define	ath_hal_hasintmit(_ah) \
908230493Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
909230493Sadrian	HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK)
910184354Ssam#define	ath_hal_getintmit(_ah) \
911230493Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
912230493Sadrian	HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK)
913184354Ssam#define	ath_hal_setintmit(_ah, _v) \
914230493Sadrian	ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \
915230493Sadrian	HAL_CAP_INTMIT_ENABLE, _v, NULL)
916154140Ssam#define	ath_hal_getchannoise(_ah, _c) \
917154140Ssam	((*(_ah)->ah_getChanNoise)((_ah), (_c)))
918218151Sadrian#define	ath_hal_getrxchainmask(_ah, _prxchainmask) \
919218151Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask))
920218151Sadrian#define	ath_hal_gettxchainmask(_ah, _ptxchainmask) \
921218151Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask))
922231369Sadrian#define	ath_hal_setrxchainmask(_ah, _rx) \
923231369Sadrian	(ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL))
924231369Sadrian#define	ath_hal_settxchainmask(_ah, _tx) \
925231369Sadrian	(ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL))
926218490Sadrian#define	ath_hal_split4ktrans(_ah) \
927230493Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \
928230493Sadrian	0, NULL) == HAL_OK)
929220324Sadrian#define	ath_hal_self_linked_final_rxdesc(_ah) \
930230493Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \
931230493Sadrian	0, NULL) == HAL_OK)
932220772Sadrian#define	ath_hal_gtxto_supported(_ah) \
933220772Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK)
934225444Sadrian#define	ath_hal_has_long_rxdesc_tsf(_ah) \
935230493Sadrian	(ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \
936230493Sadrian	0, NULL) == HAL_OK)
937116743Ssam#define	ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
938116743Ssam	((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
939165185Ssam#define	ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
940165185Ssam	((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
941116743Ssam#define	ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
942116743Ssam		_txr0, _txtr0, _keyix, _ant, _flags, \
943116743Ssam		_rtsrate, _rtsdura) \
944116743Ssam	((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
945116743Ssam		(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
946155515Ssam		(_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
947138570Ssam#define	ath_hal_setupxtxdesc(_ah, _ds, \
948116743Ssam		_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
949138570Ssam	((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
950116743Ssam		(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
951138570Ssam#define	ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
952138570Ssam	((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
953165185Ssam#define	ath_hal_txprocdesc(_ah, _ds, _ts) \
954165185Ssam	((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
955155515Ssam#define	ath_hal_gettxintrtxqs(_ah, _txqs) \
956155515Ssam	((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
957217627Sadrian#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \
958217627Sadrian	((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
959116743Ssam
960218066Sadrian#define	ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \
961218066Sadrian		_txr0, _txtr0, _antm, _rcr, _rcd) \
962218066Sadrian	((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
963218066Sadrian	(_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd)))
964227328Sadrian#define	ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \
965233895Sadrian	_cipher, _delims, _seglen, _first, _last, _lastaggr) \
966227328Sadrian	((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \
967227328Sadrian	(_type), (_keyix), (_cipher), (_delims), (_seglen), \
968233895Sadrian	(_first), (_last), (_lastaggr)))
969218066Sadrian#define	ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \
970218066Sadrian	((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
971227328Sadrian
972218067Sadrian#define	ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \
973218066Sadrian	((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
974218067Sadrian	(_series), (_ns), (_flags)))
975227328Sadrian
976227328Sadrian#define	ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \
977227328Sadrian	((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num)))
978218066Sadrian#define	ath_hal_set11naggrmiddle(_ah, _ds, _num) \
979227328Sadrian	((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num)))
980227328Sadrian#define	ath_hal_set11n_aggr_last(_ah, _ds) \
981227328Sadrian	((*(_ah)->ah_set11nAggrLast)((_ah), (_ds)))
982227328Sadrian
983218066Sadrian#define	ath_hal_set11nburstduration(_ah, _ds, _dur) \
984218066Sadrian	((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
985227328Sadrian#define	ath_hal_clr11n_aggr(_ah, _ds) \
986227328Sadrian	((*(_ah)->ah_clr11nAggr)((_ah), (_ds)))
987218066Sadrian
988230493Sadrian#define	ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
989230493Sadrian	((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
990230493Sadrian#define	ath_hal_gpioset(_ah, _gpio, _b) \
991230493Sadrian	((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
992230493Sadrian#define	ath_hal_gpioget(_ah, _gpio) \
993230493Sadrian	((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
994230493Sadrian#define	ath_hal_gpiosetintr(_ah, _gpio, _b) \
995230493Sadrian	((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
996230493Sadrian
997222585Sadrian/*
998222585Sadrian * This is badly-named; you need to set the correct parameters
999222585Sadrian * to begin to receive useful radar events; and even then
1000222585Sadrian * it doesn't "enable" DFS. See the ath_dfs/null/ module for
1001222585Sadrian * more information.
1002222585Sadrian */
1003222585Sadrian#define	ath_hal_enabledfs(_ah, _param) \
1004222585Sadrian	((*(_ah)->ah_enableDfs)((_ah), (_param)))
1005222585Sadrian#define	ath_hal_getdfsthresh(_ah, _param) \
1006222585Sadrian	((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
1007222815Sadrian#define	ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \
1008230493Sadrian	((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \
1009230493Sadrian	(_buf), (_event)))
1010224714Sadrian#define	ath_hal_is_fast_clock_enabled(_ah) \
1011224720Sadrian	((*(_ah)->ah_isFastClockEnabled)((_ah)))
1012230493Sadrian#define	ath_hal_radar_wait(_ah, _chan) \
1013155515Ssam	((*(_ah)->ah_radarWait)((_ah), (_chan)))
1014234873Sadrian#define	ath_hal_get_mib_cycle_counts(_ah, _sample) \
1015234873Sadrian	((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
1016230493Sadrian#define	ath_hal_get_chan_ext_busy(_ah) \
1017230492Sadrian	((*(_ah)->ah_get11nExtBusy)((_ah)))
1018155515Ssam
1019116743Ssam#endif /* _DEV_ATH_ATHVAR_H */
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