if_athvar.h revision 235491
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 235491 2012-05-15 23:39:37Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * 802.11n requires more TX and RX buffers to do AMPDU. 48 */ 49#ifdef ATH_ENABLE_11N 50#define ATH_TXBUF 128 51#define ATH_RXBUF 512 52#endif 53 54#ifndef ATH_RXBUF 55#define ATH_RXBUF 40 /* number of RX buffers */ 56#endif 57#ifndef ATH_TXBUF 58#define ATH_TXBUF 200 /* number of TX buffers */ 59#endif 60#define ATH_BCBUF 4 /* number of beacon buffers */ 61 62#define ATH_TXDESC 10 /* number of descriptors per buffer */ 63#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 64#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 65#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 66 67#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 68#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 69#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 70 71/* 72 * The key cache is used for h/w cipher state and also for 73 * tracking station state such as the current tx antenna. 74 * We also setup a mapping table between key cache slot indices 75 * and station state to short-circuit node lookups on rx. 76 * Different parts have different size key caches. We handle 77 * up to ATH_KEYMAX entries (could dynamically allocate state). 78 */ 79#define ATH_KEYMAX 128 /* max key cache size we handle */ 80#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 81 82struct taskqueue; 83struct kthread; 84struct ath_buf; 85 86#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 87 88/* 89 * Per-TID state 90 * 91 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 92 */ 93struct ath_tid { 94 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 95 u_int axq_depth; /* SW queue depth */ 96 char axq_name[48]; /* lock name */ 97 struct ath_node *an; /* pointer to parent */ 98 int tid; /* tid */ 99 int ac; /* which AC gets this trafic */ 100 int hwq_depth; /* how many buffers are on HW */ 101 102 /* 103 * Entry on the ath_txq; when there's traffic 104 * to send 105 */ 106 TAILQ_ENTRY(ath_tid) axq_qelem; 107 int sched; 108 int paused; /* >0 if the TID has been paused */ 109 int bar_wait; /* waiting for BAR */ 110 int bar_tx; /* BAR TXed */ 111 112 /* 113 * Is the TID being cleaned up after a transition 114 * from aggregation to non-aggregation? 115 * When this is set to 1, this TID will be paused 116 * and no further traffic will be queued until all 117 * the hardware packets pending for this TID have been 118 * TXed/completed; at which point (non-aggregation) 119 * traffic will resume being TXed. 120 */ 121 int cleanup_inprogress; 122 /* 123 * How many hardware-queued packets are 124 * waiting to be cleaned up. 125 * This is only valid if cleanup_inprogress is 1. 126 */ 127 int incomp; 128 129 /* 130 * The following implements a ring representing 131 * the frames in the current BAW. 132 * To avoid copying the array content each time 133 * the BAW is moved, the baw_head/baw_tail point 134 * to the current BAW begin/end; when the BAW is 135 * shifted the head/tail of the array are also 136 * appropriately shifted. 137 */ 138 /* active tx buffers, beginning at current BAW */ 139 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 140 /* where the baw head is in the array */ 141 int baw_head; 142 /* where the BAW tail is in the array */ 143 int baw_tail; 144}; 145 146/* driver-specific node state */ 147struct ath_node { 148 struct ieee80211_node an_node; /* base class */ 149 u_int8_t an_mgmtrix; /* min h/w rate index */ 150 u_int8_t an_mcastrix; /* mcast h/w rate index */ 151 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 152 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 153 char an_name[32]; /* eg "wlan0_a1" */ 154 struct mtx an_mtx; /* protecting the ath_node state */ 155 /* variable-length rate control state follows */ 156}; 157#define ATH_NODE(ni) ((struct ath_node *)(ni)) 158#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 159 160#define ATH_RSSI_LPF_LEN 10 161#define ATH_RSSI_DUMMY_MARKER 0x127 162#define ATH_EP_MUL(x, mul) ((x) * (mul)) 163#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 164#define ATH_LPF_RSSI(x, y, len) \ 165 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 166#define ATH_RSSI_LPF(x, y) do { \ 167 if ((y) >= -20) \ 168 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 169} while (0) 170#define ATH_EP_RND(x,mul) \ 171 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 172#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 173 174struct ath_buf { 175 TAILQ_ENTRY(ath_buf) bf_list; 176 struct ath_buf * bf_next; /* next buffer in the aggregate */ 177 int bf_nseg; 178 uint16_t bf_flags; /* status flags (below) */ 179 struct ath_desc *bf_desc; /* virtual addr of desc */ 180 struct ath_desc_status bf_status; /* tx/rx status */ 181 bus_addr_t bf_daddr; /* physical addr of desc */ 182 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 183 struct mbuf *bf_m; /* mbuf for buf */ 184 struct ieee80211_node *bf_node; /* pointer to the node */ 185 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 186 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 187 bus_size_t bf_mapsize; 188#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 189 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 190 191 /* Completion function to call on TX complete (fail or not) */ 192 /* 193 * "fail" here is set to 1 if the queue entries were removed 194 * through a call to ath_tx_draintxq(). 195 */ 196 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 197 198 /* This state is kept to support software retries and aggregation */ 199 struct { 200 int bfs_seqno; /* sequence number of this packet */ 201 int bfs_retries; /* retry count */ 202 uint16_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 203 uint16_t bfs_pri; /* packet AC priority */ 204 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 205 uint16_t bfs_pktdur; /* packet duration (at current rate?) */ 206 uint16_t bfs_nframes; /* number of frames in aggregate */ 207 uint16_t bfs_ndelim; /* number of delims for padding */ 208 209 u_int32_t bfs_aggr:1, /* part of aggregate? */ 210 bfs_aggrburst:1, /* part of aggregate burst? */ 211 bfs_isretried:1, /* retried frame? */ 212 bfs_dobaw:1, /* actually check against BAW? */ 213 bfs_addedbaw:1, /* has been added to the BAW */ 214 bfs_shpream:1, /* use short preamble */ 215 bfs_istxfrag:1, /* is fragmented */ 216 bfs_ismrr:1, /* do multi-rate TX retry */ 217 bfs_doprot:1, /* do RTS/CTS based protection */ 218 bfs_doratelookup:1, /* do rate lookup before each TX */ 219 bfs_need_seqno:1, /* need to assign a seqno for aggr */ 220 bfs_seqno_assigned:1; /* seqno has been assigned */ 221 222 int bfs_nfl; /* next fragment length */ 223 224 /* 225 * These fields are passed into the 226 * descriptor setup functions. 227 */ 228 HAL_PKT_TYPE bfs_atype; /* packet type */ 229 int bfs_pktlen; /* length of this packet */ 230 int bfs_hdrlen; /* length of this packet header */ 231 uint16_t bfs_al; /* length of aggregate */ 232 int bfs_txflags; /* HAL (tx) descriptor flags */ 233 int bfs_txrate0; /* first TX rate */ 234 int bfs_try0; /* first try count */ 235 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 236 int bfs_keyix; /* crypto key index */ 237 int bfs_txpower; /* tx power */ 238 int bfs_txantenna; /* TX antenna config */ 239 enum ieee80211_protmode bfs_protmode; 240 HAL_11N_RATE_SERIES bfs_rc11n[ATH_RC_NUM]; /* 11n TX series */ 241 int bfs_ctsrate; /* CTS rate */ 242 int bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 243 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 244 } bf_state; 245}; 246typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 247 248#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 249 250/* 251 * DMA state for tx/rx descriptors. 252 */ 253struct ath_descdma { 254 const char* dd_name; 255 struct ath_desc *dd_desc; /* descriptors */ 256 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 257 bus_size_t dd_desc_len; /* size of dd_desc */ 258 bus_dma_segment_t dd_dseg; 259 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 260 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 261 struct ath_buf *dd_bufptr; /* associated buffers */ 262}; 263 264/* 265 * Data transmit queue state. One of these exists for each 266 * hardware transmit queue. Packets sent to us from above 267 * are assigned to queues based on their priority. Not all 268 * devices support a complete set of hardware transmit queues. 269 * For those devices the array sc_ac2q will map multiple 270 * priorities to fewer hardware queues (typically all to one 271 * hardware queue). 272 */ 273struct ath_txq { 274 struct ath_softc *axq_softc; /* Needed for scheduling */ 275 u_int axq_qnum; /* hardware q number */ 276#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 277 u_int axq_ac; /* WME AC */ 278 u_int axq_flags; 279#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 280 u_int axq_depth; /* queue depth (stat only) */ 281 u_int axq_aggr_depth; /* how many aggregates are queued */ 282 u_int axq_intrcnt; /* interrupt count */ 283 u_int32_t *axq_link; /* link ptr in last TX desc */ 284 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 285 struct mtx axq_lock; /* lock on q and link */ 286 char axq_name[12]; /* e.g. "ath0_txq4" */ 287 288 /* Per-TID traffic queue for software -> hardware TX */ 289 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 290}; 291 292#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 293#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 294#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 295 296#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 297 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 298 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 299 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 300} while (0) 301#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 302#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 303#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 304#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 305#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 306 307#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 308 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 309 (_tq)->axq_depth++; \ 310} while (0) 311#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 312 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 313 (_tq)->axq_depth++; \ 314} while (0) 315#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 316 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 317 (_tq)->axq_depth--; \ 318} while (0) 319#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 320 321struct ath_vap { 322 struct ieee80211vap av_vap; /* base class */ 323 int av_bslot; /* beacon slot index */ 324 struct ath_buf *av_bcbuf; /* beacon buffer */ 325 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 326 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 327 328 void (*av_recv_mgmt)(struct ieee80211_node *, 329 struct mbuf *, int, int, int); 330 int (*av_newstate)(struct ieee80211vap *, 331 enum ieee80211_state, int); 332 void (*av_bmiss)(struct ieee80211vap *); 333}; 334#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 335 336struct taskqueue; 337struct ath_tx99; 338 339/* 340 * Whether to reset the TX/RX queue with or without 341 * a queue flush. 342 */ 343typedef enum { 344 ATH_RESET_DEFAULT = 0, 345 ATH_RESET_NOLOSS = 1, 346 ATH_RESET_FULL = 2, 347} ATH_RESET_TYPE; 348 349struct ath_softc { 350 struct ifnet *sc_ifp; /* interface common */ 351 struct ath_stats sc_stats; /* interface statistics */ 352 struct ath_tx_aggr_stats sc_aggr_stats; 353 struct ath_intr_stats sc_intr_stats; 354 uint64_t sc_debug; 355 int sc_nvaps; /* # vaps */ 356 int sc_nstavaps; /* # station vaps */ 357 int sc_nmeshvaps; /* # mbss vaps */ 358 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 359 u_int8_t sc_nbssid0; /* # vap's using base mac */ 360 uint32_t sc_bssidmask; /* bssid mask */ 361 362 void (*sc_node_cleanup)(struct ieee80211_node *); 363 void (*sc_node_free)(struct ieee80211_node *); 364 device_t sc_dev; 365 HAL_BUS_TAG sc_st; /* bus space tag */ 366 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 367 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 368 struct mtx sc_mtx; /* master lock (recursive) */ 369 struct mtx sc_pcu_mtx; /* PCU access mutex */ 370 char sc_pcu_mtx_name[32]; 371 struct taskqueue *sc_tq; /* private task queue */ 372 struct ath_hal *sc_ah; /* Atheros HAL */ 373 struct ath_ratectrl *sc_rc; /* tx rate control support */ 374 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 375 void (*sc_setdefantenna)(struct ath_softc *, u_int); 376 unsigned int sc_invalid : 1,/* disable hardware accesses */ 377 sc_mrretry : 1,/* multi-rate retry support */ 378 sc_softled : 1,/* enable LED gpio status */ 379 sc_hardled : 1,/* enable MAC LED status */ 380 sc_splitmic : 1,/* split TKIP MIC keys */ 381 sc_needmib : 1,/* enable MIB stats intr */ 382 sc_diversity: 1,/* enable rx diversity */ 383 sc_hasveol : 1,/* tx VEOL support */ 384 sc_ledstate : 1,/* LED on/off state */ 385 sc_blinking : 1,/* LED blink operation active */ 386 sc_mcastkey : 1,/* mcast key cache search */ 387 sc_scanning : 1,/* scanning active */ 388 sc_syncbeacon:1,/* sync/resync beacon timers */ 389 sc_hasclrkey: 1,/* CLR key supported */ 390 sc_xchanmode: 1,/* extended channel mode */ 391 sc_outdoor : 1,/* outdoor operation */ 392 sc_dturbo : 1,/* dynamic turbo in use */ 393 sc_hasbmask : 1,/* bssid mask support */ 394 sc_hasbmatch: 1,/* bssid match disable support*/ 395 sc_hastsfadd: 1,/* tsf adjust support */ 396 sc_beacons : 1,/* beacons running */ 397 sc_swbmiss : 1,/* sta mode using sw bmiss */ 398 sc_stagbeacons:1,/* use staggered beacons */ 399 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 400 sc_resume_up: 1,/* on resume, start all vaps */ 401 sc_tdma : 1,/* TDMA in use */ 402 sc_setcca : 1,/* set/clr CCA with TDMA */ 403 sc_resetcal : 1,/* reset cal state next trip */ 404 sc_rxslink : 1,/* do self-linked final descriptor */ 405 sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 406 uint32_t sc_eerd; /* regdomain from EEPROM */ 407 uint32_t sc_eecc; /* country code from EEPROM */ 408 /* rate tables */ 409 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 410 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 411 enum ieee80211_phymode sc_curmode; /* current phy mode */ 412 HAL_OPMODE sc_opmode; /* current operating mode */ 413 u_int16_t sc_curtxpow; /* current tx power limit */ 414 u_int16_t sc_curaid; /* current association id */ 415 struct ieee80211_channel *sc_curchan; /* current installed channel */ 416 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 417 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 418 struct { 419 u_int8_t ieeerate; /* IEEE rate */ 420 u_int8_t rxflags; /* radiotap rx flags */ 421 u_int8_t txflags; /* radiotap tx flags */ 422 u_int16_t ledon; /* softled on time */ 423 u_int16_t ledoff; /* softled off time */ 424 } sc_hwmap[32]; /* h/w rate ix mappings */ 425 u_int8_t sc_protrix; /* protection rate index */ 426 u_int8_t sc_lastdatarix; /* last data frame rate index */ 427 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 428 u_int sc_fftxqmin; /* min frames before staging */ 429 u_int sc_fftxqmax; /* max frames before drop */ 430 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 431 432 HAL_INT sc_imask; /* interrupt mask copy */ 433 434 /* 435 * These are modified in the interrupt handler as well as 436 * the task queues and other contexts. Thus these must be 437 * protected by a mutex, or they could clash. 438 * 439 * For now, access to these is behind the ATH_LOCK, 440 * just to save time. 441 */ 442 uint32_t sc_txq_active; /* bitmap of active TXQs */ 443 uint32_t sc_kickpcu; /* whether to kick the PCU */ 444 uint32_t sc_rxproc_cnt; /* In RX processing */ 445 uint32_t sc_txproc_cnt; /* In TX processing */ 446 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 447 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 448 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 449 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 450 451 u_int sc_keymax; /* size of key cache */ 452 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 453 454 /* 455 * Software based LED blinking 456 */ 457 u_int sc_ledpin; /* GPIO pin for driving LED */ 458 u_int sc_ledon; /* pin setting for LED on */ 459 u_int sc_ledidle; /* idle polling interval */ 460 int sc_ledevent; /* time of last LED event */ 461 u_int8_t sc_txrix; /* current tx rate for LED */ 462 u_int16_t sc_ledoff; /* off time for current blink */ 463 struct callout sc_ledtimer; /* led off timer */ 464 465 /* 466 * Hardware based LED blinking 467 */ 468 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 469 int sc_led_net_pin; /* MAC network LED GPIO pin */ 470 471 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 472 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 473 474 struct ath_descdma sc_rxdma; /* RX descriptors */ 475 ath_bufhead sc_rxbuf; /* receive buffer */ 476 struct mbuf *sc_rxpending; /* pending receive data */ 477 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 478 struct task sc_rxtask; /* rx int processing */ 479 u_int8_t sc_defant; /* current default antenna */ 480 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 481 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 482 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 483 struct ath_rx_radiotap_header sc_rx_th; 484 int sc_rx_th_len; 485 u_int sc_monpass; /* frames to pass in mon.mode */ 486 487 struct ath_descdma sc_txdma; /* TX descriptors */ 488 ath_bufhead sc_txbuf; /* transmit buffer */ 489 struct mtx sc_txbuflock; /* txbuf lock */ 490 char sc_txname[12]; /* e.g. "ath0_buf" */ 491 u_int sc_txqsetup; /* h/w queues setup */ 492 u_int sc_txintrperiod;/* tx interrupt batching */ 493 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 494 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 495 struct task sc_txtask; /* tx int processing */ 496 struct task sc_txqtask; /* tx proc processing */ 497 int sc_wd_timer; /* count down for wd timer */ 498 struct callout sc_wd_ch; /* tx watchdog timer */ 499 struct ath_tx_radiotap_header sc_tx_th; 500 int sc_tx_th_len; 501 502 struct ath_descdma sc_bdma; /* beacon descriptors */ 503 ath_bufhead sc_bbuf; /* beacon buffers */ 504 u_int sc_bhalq; /* HAL q for outgoing beacons */ 505 u_int sc_bmisscount; /* missed beacon transmits */ 506 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 507 struct ath_txq *sc_cabq; /* tx q for cab frames */ 508 struct task sc_bmisstask; /* bmiss int processing */ 509 struct task sc_bstucktask; /* stuck beacon processing */ 510 struct task sc_resettask; /* interface reset task */ 511 struct task sc_fataltask; /* fatal task */ 512 enum { 513 OK, /* no change needed */ 514 UPDATE, /* update pending */ 515 COMMIT /* beacon sent, commit change */ 516 } sc_updateslot; /* slot time update fsm */ 517 int sc_slotupdate; /* slot to advance fsm */ 518 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 519 int sc_nbcnvaps; /* # vaps with beacons */ 520 521 struct callout sc_cal_ch; /* callout handle for cals */ 522 int sc_lastlongcal; /* last long cal completed */ 523 int sc_lastcalreset;/* last cal reset done */ 524 int sc_lastani; /* last ANI poll */ 525 int sc_lastshortcal; /* last short calibration */ 526 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 527 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 528 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 529 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 530 u_int sc_tdmaswba; /* TDMA SWBA counter */ 531 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 532 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 533 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 534 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 535 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 536 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 537 int sc_txchainmask; /* currently configured TX chainmask */ 538 int sc_rxchainmask; /* currently configured RX chainmask */ 539 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 540 541 /* Queue limits */ 542 543 /* 544 * To avoid queue starvation in congested conditions, 545 * these parameters tune the maximum number of frames 546 * queued to the data/mcastq before they're dropped. 547 * 548 * This is to prevent: 549 * + a single destination overwhelming everything, including 550 * management/multicast frames; 551 * + multicast frames overwhelming everything (when the 552 * air is sufficiently busy that cabq can't drain.) 553 * 554 * These implement: 555 * + data_minfree is the maximum number of free buffers 556 * overall to successfully allow a data frame. 557 * 558 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 559 */ 560 int sc_txq_data_minfree; 561 int sc_txq_mcastq_maxdepth; 562 563 /* 564 * Aggregation twiddles 565 * 566 * hwq_limit: how busy to keep the hardware queue - don't schedule 567 * further packets to the hardware, regardless of the TID 568 * tid_hwq_lo: how low the per-TID hwq count has to be before the 569 * TID will be scheduled again 570 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 571 * stops being scheduled. 572 */ 573 int sc_hwq_limit; 574 int sc_tid_hwq_lo; 575 int sc_tid_hwq_hi; 576 577 /* DFS related state */ 578 void *sc_dfs; /* Used by an optional DFS module */ 579 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 580 struct task sc_dfstask; /* DFS processing task */ 581 582 /* TX AMPDU handling */ 583 int (*sc_addba_request)(struct ieee80211_node *, 584 struct ieee80211_tx_ampdu *, int, int, int); 585 int (*sc_addba_response)(struct ieee80211_node *, 586 struct ieee80211_tx_ampdu *, int, int, int); 587 void (*sc_addba_stop)(struct ieee80211_node *, 588 struct ieee80211_tx_ampdu *); 589 void (*sc_addba_response_timeout) 590 (struct ieee80211_node *, 591 struct ieee80211_tx_ampdu *); 592 void (*sc_bar_response)(struct ieee80211_node *ni, 593 struct ieee80211_tx_ampdu *tap, 594 int status); 595}; 596 597#define ATH_LOCK_INIT(_sc) \ 598 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 599 NULL, MTX_DEF | MTX_RECURSE) 600#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 601#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 602#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 603#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 604#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 605 606/* 607 * The PCU lock is non-recursive and should be treated as a spinlock. 608 * Although currently the interrupt code is run in netisr context and 609 * doesn't require this, this may change in the future. 610 * Please keep this in mind when protecting certain code paths 611 * with the PCU lock. 612 * 613 * The PCU lock is used to serialise access to the PCU so things such 614 * as TX, RX, state change (eg channel change), channel reset and updates 615 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 616 * 617 * Although the current single-thread taskqueue mechanism protects the 618 * majority of these situations by simply serialising them, there are 619 * a few others which occur at the same time. These include the TX path 620 * (which only acquires ATH_LOCK when recycling buffers to the free list), 621 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 622 */ 623#define ATH_PCU_LOCK_INIT(_sc) do {\ 624 snprintf((_sc)->sc_pcu_mtx_name, \ 625 sizeof((_sc)->sc_pcu_mtx_name), \ 626 "%s PCU lock", \ 627 device_get_nameunit((_sc)->sc_dev)); \ 628 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 629 NULL, MTX_DEF); \ 630 } while (0) 631#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 632#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 633#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 634#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 635 MA_OWNED) 636#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 637 MA_NOTOWNED) 638 639#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 640 641#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 642 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 643 device_get_nameunit((_sc)->sc_dev)); \ 644 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 645} while (0) 646#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 647#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 648#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 649#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 650 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 651 652int ath_attach(u_int16_t, struct ath_softc *); 653int ath_detach(struct ath_softc *); 654void ath_resume(struct ath_softc *); 655void ath_suspend(struct ath_softc *); 656void ath_shutdown(struct ath_softc *); 657void ath_intr(void *); 658 659/* 660 * HAL definitions to comply with local coding convention. 661 */ 662#define ath_hal_detach(_ah) \ 663 ((*(_ah)->ah_detach)((_ah))) 664#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 665 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 666#define ath_hal_macversion(_ah) \ 667 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 668#define ath_hal_getratetable(_ah, _mode) \ 669 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 670#define ath_hal_getmac(_ah, _mac) \ 671 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 672#define ath_hal_setmac(_ah, _mac) \ 673 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 674#define ath_hal_getbssidmask(_ah, _mask) \ 675 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 676#define ath_hal_setbssidmask(_ah, _mask) \ 677 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 678#define ath_hal_intrset(_ah, _mask) \ 679 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 680#define ath_hal_intrget(_ah) \ 681 ((*(_ah)->ah_getInterrupts)((_ah))) 682#define ath_hal_intrpend(_ah) \ 683 ((*(_ah)->ah_isInterruptPending)((_ah))) 684#define ath_hal_getisr(_ah, _pmask) \ 685 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 686#define ath_hal_updatetxtriglevel(_ah, _inc) \ 687 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 688#define ath_hal_setpower(_ah, _mode) \ 689 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 690#define ath_hal_keycachesize(_ah) \ 691 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 692#define ath_hal_keyreset(_ah, _ix) \ 693 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 694#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 695 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 696#define ath_hal_keyisvalid(_ah, _ix) \ 697 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 698#define ath_hal_keysetmac(_ah, _ix, _mac) \ 699 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 700#define ath_hal_getrxfilter(_ah) \ 701 ((*(_ah)->ah_getRxFilter)((_ah))) 702#define ath_hal_setrxfilter(_ah, _filter) \ 703 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 704#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 705 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 706#define ath_hal_waitforbeacon(_ah, _bf) \ 707 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 708#define ath_hal_putrxbuf(_ah, _bufaddr) \ 709 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 710/* NB: common across all chips */ 711#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 712#define ath_hal_gettsf32(_ah) \ 713 OS_REG_READ(_ah, AR_TSF_L32) 714#define ath_hal_gettsf64(_ah) \ 715 ((*(_ah)->ah_getTsf64)((_ah))) 716#define ath_hal_resettsf(_ah) \ 717 ((*(_ah)->ah_resetTsf)((_ah))) 718#define ath_hal_rxena(_ah) \ 719 ((*(_ah)->ah_enableReceive)((_ah))) 720#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 721 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 722#define ath_hal_gettxbuf(_ah, _q) \ 723 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 724#define ath_hal_numtxpending(_ah, _q) \ 725 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 726#define ath_hal_getrxbuf(_ah) \ 727 ((*(_ah)->ah_getRxDP)((_ah))) 728#define ath_hal_txstart(_ah, _q) \ 729 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 730#define ath_hal_setchannel(_ah, _chan) \ 731 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 732#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 733 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 734#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 735 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 736#define ath_hal_calreset(_ah, _chan) \ 737 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 738#define ath_hal_setledstate(_ah, _state) \ 739 ((*(_ah)->ah_setLedState)((_ah), (_state))) 740#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 741 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 742#define ath_hal_beaconreset(_ah) \ 743 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 744#define ath_hal_beaconsettimers(_ah, _bt) \ 745 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 746#define ath_hal_beacontimers(_ah, _bs) \ 747 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 748#define ath_hal_getnexttbtt(_ah) \ 749 ((*(_ah)->ah_getNextTBTT)((_ah))) 750#define ath_hal_setassocid(_ah, _bss, _associd) \ 751 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 752#define ath_hal_phydisable(_ah) \ 753 ((*(_ah)->ah_phyDisable)((_ah))) 754#define ath_hal_setopmode(_ah) \ 755 ((*(_ah)->ah_setPCUConfig)((_ah))) 756#define ath_hal_stoptxdma(_ah, _qnum) \ 757 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 758#define ath_hal_stoppcurecv(_ah) \ 759 ((*(_ah)->ah_stopPcuReceive)((_ah))) 760#define ath_hal_startpcurecv(_ah) \ 761 ((*(_ah)->ah_startPcuReceive)((_ah))) 762#define ath_hal_stopdmarecv(_ah) \ 763 ((*(_ah)->ah_stopDmaReceive)((_ah))) 764#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 765 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 766 (_indata), (_insize), (_outdata), (_outsize))) 767#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 768 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 769#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 770 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 771#define ath_hal_resettxqueue(_ah, _q) \ 772 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 773#define ath_hal_releasetxqueue(_ah, _q) \ 774 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 775#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 776 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 777#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 778 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 779/* NB: common across all chips */ 780#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 781#define ath_hal_txqenabled(_ah, _qnum) \ 782 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 783#define ath_hal_getrfgain(_ah) \ 784 ((*(_ah)->ah_getRfGain)((_ah))) 785#define ath_hal_getdefantenna(_ah) \ 786 ((*(_ah)->ah_getDefAntenna)((_ah))) 787#define ath_hal_setdefantenna(_ah, _ant) \ 788 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 789#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 790 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 791#define ath_hal_ani_poll(_ah, _chan) \ 792 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 793#define ath_hal_mibevent(_ah, _stats) \ 794 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 795#define ath_hal_setslottime(_ah, _us) \ 796 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 797#define ath_hal_getslottime(_ah) \ 798 ((*(_ah)->ah_getSlotTime)((_ah))) 799#define ath_hal_setacktimeout(_ah, _us) \ 800 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 801#define ath_hal_getacktimeout(_ah) \ 802 ((*(_ah)->ah_getAckTimeout)((_ah))) 803#define ath_hal_setctstimeout(_ah, _us) \ 804 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 805#define ath_hal_getctstimeout(_ah) \ 806 ((*(_ah)->ah_getCTSTimeout)((_ah))) 807#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 808 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 809#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 810 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 811#define ath_hal_ciphersupported(_ah, _cipher) \ 812 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 813#define ath_hal_getregdomain(_ah, _prd) \ 814 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 815#define ath_hal_setregdomain(_ah, _rd) \ 816 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 817#define ath_hal_getcountrycode(_ah, _pcc) \ 818 (*(_pcc) = (_ah)->ah_countryCode) 819#define ath_hal_gettkipmic(_ah) \ 820 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 821#define ath_hal_settkipmic(_ah, _v) \ 822 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 823#define ath_hal_hastkipsplit(_ah) \ 824 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 825#define ath_hal_gettkipsplit(_ah) \ 826 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 827#define ath_hal_settkipsplit(_ah, _v) \ 828 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 829#define ath_hal_haswmetkipmic(_ah) \ 830 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 831#define ath_hal_hwphycounters(_ah) \ 832 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 833#define ath_hal_hasdiversity(_ah) \ 834 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 835#define ath_hal_getdiversity(_ah) \ 836 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 837#define ath_hal_setdiversity(_ah, _v) \ 838 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 839#define ath_hal_getantennaswitch(_ah) \ 840 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 841#define ath_hal_setantennaswitch(_ah, _v) \ 842 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 843#define ath_hal_getdiag(_ah, _pv) \ 844 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 845#define ath_hal_setdiag(_ah, _v) \ 846 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 847#define ath_hal_getnumtxqueues(_ah, _pv) \ 848 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 849#define ath_hal_hasveol(_ah) \ 850 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 851#define ath_hal_hastxpowlimit(_ah) \ 852 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 853#define ath_hal_settxpowlimit(_ah, _pow) \ 854 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 855#define ath_hal_gettxpowlimit(_ah, _ppow) \ 856 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 857#define ath_hal_getmaxtxpow(_ah, _ppow) \ 858 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 859#define ath_hal_gettpscale(_ah, _scale) \ 860 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 861#define ath_hal_settpscale(_ah, _v) \ 862 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 863#define ath_hal_hastpc(_ah) \ 864 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 865#define ath_hal_gettpc(_ah) \ 866 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 867#define ath_hal_settpc(_ah, _v) \ 868 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 869#define ath_hal_hasbursting(_ah) \ 870 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 871#define ath_hal_setmcastkeysearch(_ah, _v) \ 872 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 873#define ath_hal_hasmcastkeysearch(_ah) \ 874 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 875#define ath_hal_getmcastkeysearch(_ah) \ 876 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 877#define ath_hal_hasfastframes(_ah) \ 878 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 879#define ath_hal_hasbssidmask(_ah) \ 880 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 881#define ath_hal_hasbssidmatch(_ah) \ 882 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 883#define ath_hal_hastsfadjust(_ah) \ 884 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 885#define ath_hal_gettsfadjust(_ah) \ 886 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 887#define ath_hal_settsfadjust(_ah, _onoff) \ 888 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 889#define ath_hal_hasrfsilent(_ah) \ 890 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 891#define ath_hal_getrfkill(_ah) \ 892 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 893#define ath_hal_setrfkill(_ah, _onoff) \ 894 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 895#define ath_hal_getrfsilent(_ah, _prfsilent) \ 896 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 897#define ath_hal_setrfsilent(_ah, _rfsilent) \ 898 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 899#define ath_hal_gettpack(_ah, _ptpack) \ 900 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 901#define ath_hal_settpack(_ah, _tpack) \ 902 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 903#define ath_hal_gettpcts(_ah, _ptpcts) \ 904 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 905#define ath_hal_settpcts(_ah, _tpcts) \ 906 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 907#define ath_hal_hasintmit(_ah) \ 908 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 909 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 910#define ath_hal_getintmit(_ah) \ 911 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 912 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 913#define ath_hal_setintmit(_ah, _v) \ 914 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 915 HAL_CAP_INTMIT_ENABLE, _v, NULL) 916#define ath_hal_getchannoise(_ah, _c) \ 917 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 918#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 919 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 920#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 921 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 922#define ath_hal_setrxchainmask(_ah, _rx) \ 923 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 924#define ath_hal_settxchainmask(_ah, _tx) \ 925 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 926#define ath_hal_split4ktrans(_ah) \ 927 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 928 0, NULL) == HAL_OK) 929#define ath_hal_self_linked_final_rxdesc(_ah) \ 930 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 931 0, NULL) == HAL_OK) 932#define ath_hal_gtxto_supported(_ah) \ 933 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 934#define ath_hal_has_long_rxdesc_tsf(_ah) \ 935 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 936 0, NULL) == HAL_OK) 937#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 938 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 939#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 940 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 941#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 942 _txr0, _txtr0, _keyix, _ant, _flags, \ 943 _rtsrate, _rtsdura) \ 944 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 945 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 946 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 947#define ath_hal_setupxtxdesc(_ah, _ds, \ 948 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 949 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 950 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 951#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 952 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 953#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 954 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 955#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 956 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 957#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 958 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 959 960#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 961 _txr0, _txtr0, _antm, _rcr, _rcd) \ 962 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 963 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 964#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 965 _cipher, _delims, _seglen, _first, _last, _lastaggr) \ 966 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 967 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 968 (_first), (_last), (_lastaggr))) 969#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 970 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 971 972#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 973 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 974 (_series), (_ns), (_flags))) 975 976#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 977 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 978#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 979 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 980#define ath_hal_set11n_aggr_last(_ah, _ds) \ 981 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 982 983#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 984 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 985#define ath_hal_clr11n_aggr(_ah, _ds) \ 986 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 987 988#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 989 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 990#define ath_hal_gpioset(_ah, _gpio, _b) \ 991 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 992#define ath_hal_gpioget(_ah, _gpio) \ 993 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 994#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 995 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 996 997/* 998 * This is badly-named; you need to set the correct parameters 999 * to begin to receive useful radar events; and even then 1000 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1001 * more information. 1002 */ 1003#define ath_hal_enabledfs(_ah, _param) \ 1004 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1005#define ath_hal_getdfsthresh(_ah, _param) \ 1006 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1007#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1008 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1009 (_buf), (_event))) 1010#define ath_hal_is_fast_clock_enabled(_ah) \ 1011 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1012#define ath_hal_radar_wait(_ah, _chan) \ 1013 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1014#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1015 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1016#define ath_hal_get_chan_ext_busy(_ah) \ 1017 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1018 1019#endif /* _DEV_ATH_ATHVAR_H */ 1020