i80321reg.h revision 236987
1135669Scognet/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */ 2135669Scognet 3139735Simp/*- 4135669Scognet * Copyright (c) 2002 Wasabi Systems, Inc. 5135669Scognet * All rights reserved. 6135669Scognet * 7135669Scognet * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8135669Scognet * 9135669Scognet * Redistribution and use in source and binary forms, with or without 10135669Scognet * modification, are permitted provided that the following conditions 11135669Scognet * are met: 12135669Scognet * 1. Redistributions of source code must retain the above copyright 13135669Scognet * notice, this list of conditions and the following disclaimer. 14135669Scognet * 2. Redistributions in binary form must reproduce the above copyright 15135669Scognet * notice, this list of conditions and the following disclaimer in the 16135669Scognet * documentation and/or other materials provided with the distribution. 17135669Scognet * 3. All advertising materials mentioning features or use of this software 18135669Scognet * must display the following acknowledgement: 19135669Scognet * This product includes software developed for the NetBSD Project by 20135669Scognet * Wasabi Systems, Inc. 21135669Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22135669Scognet * or promote products derived from this software without specific prior 23135669Scognet * written permission. 24135669Scognet * 25135669Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26135669Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27135669Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28135669Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29135669Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30135669Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31135669Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32135669Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33135669Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34135669Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35135669Scognet * POSSIBILITY OF SUCH DAMAGE. 36135669Scognet * 37135669Scognet * $FreeBSD: head/sys/arm/xscale/i80321/i80321reg.h 236987 2012-06-13 04:38:09Z imp $ 38135669Scognet * 39135669Scognet */ 40135669Scognet 41236987Simp#ifndef _ARM_XSCALE_I80321REG_H_ 42236987Simp#define _ARM_XSCALE_I80321REG_H_ 43135669Scognet 44135669Scognet/* 45135669Scognet * Register definitions for the Intel 80321 (``Verde'') I/O processor, 46135669Scognet * based on the XScale core. 47135669Scognet */ 48135669Scognet 49135669Scognet/* 50135669Scognet * Base i80321 memory map: 51135669Scognet * 52135669Scognet * 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window 53135669Scognet * 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows 54135669Scognet * 0x9002.0000 - 0xffff.dfff External Memory 55135669Scognet * 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers 56135669Scognet * 0xffff.e900 - 0xffff.ffff Reserved 57135669Scognet */ 58135669Scognet 59135669Scognet#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL 60135669Scognet#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL 61135669Scognet 62135669Scognet#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL 63135669Scognet#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL 64135669Scognet 65135669Scognet#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL 66135669Scognet#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL 67135669Scognet 68135669Scognet#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL 69135669Scognet 70135669Scognet#define VERDE_EXTMEM_BASE 0x90020000UL 71135669Scognet 72135669Scognet#define VERDE_PMMR_BASE 0xffffe000UL 73135669Scognet#define VERDE_PMMR_SIZE 0x00001700UL 74135669Scognet 75135669Scognet/* 76135669Scognet * Peripheral Memory Mapped Registers. Defined as offsets 77135669Scognet * from the VERDE_PMMR_BASE. 78135669Scognet */ 79135669Scognet#define VERDE_ATU_BASE 0x0100 80135669Scognet#define VERDE_ATU_SIZE 0x0100 81135669Scognet 82135669Scognet#define VERDE_MU_BASE 0x0300 83135669Scognet#define VERDE_MU_SIZE 0x0100 84135669Scognet 85135669Scognet#define VERDE_DMA_BASE 0x0400 86135669Scognet#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) 87135669Scognet#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) 88135669Scognet#define VERDE_DMA_SIZE 0x0100 89135669Scognet#define VERDE_DMA_CHSIZE 0x0040 90135669Scognet 91135669Scognet#define VERDE_MCU_BASE 0x0500 92135669Scognet#define VERDE_MCU_SIZE 0x0100 93135669Scognet 94161592Scognet#if defined(CPU_XSCALE_80321) 95135669Scognet#define VERDE_SSP_BASE 0x0600 96135669Scognet#define VERDE_SSP_SIZE 0x0080 97161592Scognet#endif 98135669Scognet 99135669Scognet#define VERDE_PBIU_BASE 0x0680 100135669Scognet#define VERDE_PBIU_SIZE 0x0080 101135669Scognet 102161592Scognet#if defined(CPU_XSCALE_80321) 103135669Scognet#define VERDE_AAU_BASE 0x0800 104135669Scognet#define VERDE_AAU_SIZE 0x0100 105236987Simp#endif 106135669Scognet 107135669Scognet#define VERDE_I2C_BASE 0x1680 108135669Scognet#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) 109135669Scognet#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) 110135669Scognet#define VERDE_I2C_SIZE 0x0080 111135669Scognet#define VERDE_I2C_CHSIZE 0x0020 112135669Scognet 113135669Scognet/* 114135669Scognet * Address Translation Unit 115135669Scognet */ 116135669Scognet /* 0x00 - 0x38 -- PCI configuration space header */ 117135669Scognet#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ 118135669Scognet#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ 119135669Scognet#define ATU_ERLR 0x48 /* Expansion ROM Limit */ 120135669Scognet#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ 121135669Scognet#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ 122135669Scognet#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ 123135669Scognet#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ 124135669Scognet#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ 125135669Scognet#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ 126135669Scognet#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ 127135669Scognet#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ 128135669Scognet#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ 129135669Scognet#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ 130135669Scognet#define ATU_ATUCR 0x80 /* ATU Configuration */ 131135669Scognet#define ATU_PCSR 0x84 /* PCI Configuration and Status */ 132135669Scognet#define ATU_ATUISR 0x88 /* ATU Interrupt Status */ 133135669Scognet#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ 134135669Scognet#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ 135135669Scognet#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ 136135669Scognet#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ 137135669Scognet#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ 138135669Scognet#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ 139135669Scognet#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ 140135669Scognet#define ATU_MSI_PORT 0xb4 /* MSI port */ 141135669Scognet#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ 142135669Scognet#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ 143135669Scognet#define ATU_PCI_X_NEXT 0xe1 /* (1) */ 144135669Scognet#define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ 145135669Scognet#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ 146135669Scognet 147135669Scognet#define ATUCR_DRC_ALIAS (1U << 19) 148135669Scognet#define ATUCR_DAU2GXEN (1U << 18) 149135669Scognet#define ATUCR_P_SERR_MA (1U << 16) 150135669Scognet#define ATUCR_DTS (1U << 15) 151135669Scognet#define ATUCR_P_SERR_DIE (1U << 9) 152135669Scognet#define ATUCR_DAE (1U << 8) 153135669Scognet#define ATUCR_BIST_IE (1U << 3) 154135669Scognet#define ATUCR_OUT_EN (1U << 1) 155135669Scognet 156135669Scognet#define PCSR_DAAAPE (1U << 18) 157135669Scognet#define PCSR_PCI_X_CAP (3U << 16) 158135669Scognet#define PCSR_PCI_X_CAP_BORING (0 << 16) 159135669Scognet#define PCSR_PCI_X_CAP_66 (1U << 16) 160135669Scognet#define PCSR_PCI_X_CAP_100 (2U << 16) 161135669Scognet#define PCSR_PCI_X_CAP_133 (3U << 16) 162135669Scognet#define PCSR_OTQB (1U << 15) 163135669Scognet#define PCSR_IRTQB (1U << 14) 164135669Scognet#define PCSR_DTV (1U << 12) 165135669Scognet#define PCSR_BUS66 (1U << 10) 166135669Scognet#define PCSR_BUS64 (1U << 8) 167135669Scognet#define PCSR_RIB (1U << 5) 168135669Scognet#define PCSR_RPB (1U << 4) 169135669Scognet#define PCSR_CCR (1U << 2) 170135669Scognet#define PCSR_CPR (1U << 1) 171135669Scognet 172135669Scognet#define ATUISR_IMW1BU (1U << 14) 173135669Scognet#define ATUISR_ISCEM (1U << 13) 174135669Scognet#define ATUISR_RSCEM (1U << 12) 175135669Scognet#define ATUISR_PST (1U << 11) 176135669Scognet#define ATUISR_P_SERR_ASRT (1U << 10) 177135669Scognet#define ATUISR_DPE (1U << 9) 178135669Scognet#define ATUISR_BIST (1U << 8) 179135669Scognet#define ATUISR_IBMA (1U << 7) 180135669Scognet#define ATUISR_P_SERR_DET (1U << 4) 181135669Scognet#define ATUISR_PMA (1U << 3) 182135669Scognet#define ATUISR_PTAM (1U << 2) 183135669Scognet#define ATUISR_PTAT (1U << 1) 184135669Scognet#define ATUISR_PMPE (1U << 0) 185135669Scognet 186135669Scognet#define ATUIMR_IMW1BU (1U << 11) 187135669Scognet#define ATUIMR_ISCEM (1U << 10) 188135669Scognet#define ATUIMR_RSCEM (1U << 9) 189135669Scognet#define ATUIMR_PST (1U << 8) 190135669Scognet#define ATUIMR_DPE (1U << 7) 191135669Scognet#define ATUIMR_P_SERR_ASRT (1U << 6) 192135669Scognet#define ATUIMR_PMA (1U << 5) 193135669Scognet#define ATUIMR_PTAM (1U << 4) 194135669Scognet#define ATUIMR_PTAT (1U << 3) 195135669Scognet#define ATUIMR_PMPE (1U << 2) 196135669Scognet#define ATUIMR_IE_SERR_EN (1U << 1) 197135669Scognet#define ATUIMR_ECC_TAE (1U << 0) 198135669Scognet 199135669Scognet#define PCIXCMD_MOST_1 (0 << 4) 200135669Scognet#define PCIXCMD_MOST_2 (1 << 4) 201135669Scognet#define PCIXCMD_MOST_3 (2 << 4) 202135669Scognet#define PCIXCMD_MOST_4 (3 << 4) 203135669Scognet#define PCIXCMD_MOST_8 (4 << 4) 204135669Scognet#define PCIXCMD_MOST_12 (5 << 4) 205135669Scognet#define PCIXCMD_MOST_16 (6 << 4) 206135669Scognet#define PCIXCMD_MOST_32 (7 << 4) 207135669Scognet#define PCIXCMD_MOST_MASK (7 << 4) 208135669Scognet#define PCIXCMD_MMRBC_512 (0 << 2) 209135669Scognet#define PCIXCMD_MMRBC_1024 (1 << 2) 210135669Scognet#define PCIXCMD_MMRBC_2048 (2 << 2) 211135669Scognet#define PCIXCMD_MMRBC_4096 (3 << 2) 212135669Scognet#define PCIXCMD_MMRBC_MASK (3 << 2) 213135669Scognet#define PCIXCMD_ERO (1U << 1) 214135669Scognet#define PCIXCMD_DPERE (1U << 0) 215135669Scognet 216135669Scognet#define PCIXSR_RSCEM (1U << 29) 217135669Scognet#define PCIXSR_DMCRS_MASK (7 << 26) 218135669Scognet#define PCIXSR_DMOST_MASK (7 << 23) 219135669Scognet#define PCIXSR_COMPLEX (1U << 20) 220135669Scognet#define PCIXSR_USC (1U << 19) 221135669Scognet#define PCIXSR_SCD (1U << 18) 222135669Scognet#define PCIXSR_133_CAP (1U << 17) 223135669Scognet#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ 224135669Scognet#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) 225135669Scognet#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) 226135669Scognet#define PCIXSR_FUNCNO(x) ((x) & 0x7) 227135669Scognet 228135669Scognet/* 229135669Scognet * Memory Controller Unit 230135669Scognet */ 231135669Scognet#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ 232135669Scognet#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ 233135669Scognet#define MCU_SDBR 0x08 /* SDRAM Base Register */ 234135669Scognet#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ 235135669Scognet#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ 236135669Scognet#define MCU_ECCR 0x34 /* ECC Control Register */ 237135669Scognet#define MCU_ELOG0 0x38 /* ECC Log 0 */ 238135669Scognet#define MCU_ELOG1 0x3c /* ECC Log 1 */ 239135669Scognet#define MCU_ECAR0 0x40 /* ECC address 0 */ 240135669Scognet#define MCU_ECAR1 0x44 /* ECC address 1 */ 241135669Scognet#define MCU_ECTST 0x48 /* ECC test register */ 242135669Scognet#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ 243135669Scognet#define MCU_RFR 0x50 /* Refresh Frequency Register */ 244135669Scognet#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ 245135669Scognet#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ 246135669Scognet#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ 247135669Scognet#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ 248135669Scognet#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ 249135669Scognet#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ 250135669Scognet#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ 251135669Scognet#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ 252135669Scognet#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ 253135669Scognet#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ 254135669Scognet#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ 255135669Scognet#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ 256135669Scognet#define MCU_DSDR 0x84 /* Data Strobe Delay Register */ 257135669Scognet#define MCU_REDR 0x88 /* Rx Enable Delay Register */ 258135669Scognet 259135669Scognet#define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ 260135669Scognet#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ 261135669Scognet 262135669Scognet#define SBRx_TECH (1U << 31) 263135669Scognet#define SBRx_BOUND 0x0000003f 264135669Scognet 265135669Scognet#define ECCR_SBERE (1U << 0) 266135669Scognet#define ECCR_MBERE (1U << 1) 267135669Scognet#define ECCR_SBECE (1U << 2) 268135669Scognet#define ECCR_ECCEN (1U << 3) 269135669Scognet 270135669Scognet#define ELOGx_SYNDROME 0x000000ff 271135669Scognet#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ 272135669Scognet#define ELOGx_RW (1U << 12) /* 1 = write error */ 273135669Scognet /* 274135669Scognet * Dev ID Func Requester 275135669Scognet * 2 0 XScale core 276135669Scognet * 2 1 ATU 277135669Scognet * 13 0 DMA channel 0 278135669Scognet * 13 1 DMA channel 1 279135669Scognet * 26 0 ATU 280135669Scognet */ 281135669Scognet#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) 282135669Scognet#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) 283135669Scognet 284135669Scognet#define MCISR_ECC_ERR0 (1U << 0) 285135669Scognet#define MCISR_ECC_ERR1 (1U << 1) 286135669Scognet#define MCISR_ECC_ERRN (1U << 2) 287135669Scognet 288135669Scognet/* 289135669Scognet * Timers 290135669Scognet * 291135669Scognet * The i80321 timer registers are available in both memory-mapped 292135669Scognet * and coprocessor spaces. Most of the registers are read-only 293135669Scognet * if memory-mapped, so we access them via coprocessor space. 294135669Scognet * 295135669Scognet * TMR0 cp6 c0,1 0xffffe7e0 296135669Scognet * TMR1 cp6 c1,1 0xffffe7e4 297135669Scognet * TCR0 cp6 c2,1 0xffffe7e8 298135669Scognet * TCR1 cp6 c3,1 0xffffe7ec 299135669Scognet * TRR0 cp6 c4,1 0xffffe7f0 300135669Scognet * TRR1 cp6 c5,1 0xffffe7f4 301135669Scognet * TISR cp6 c6,1 0xffffe7f8 302135669Scognet * WDTCR cp6 c7,1 0xffffe7fc 303135669Scognet */ 304135669Scognet 305135669Scognet#define TMRx_TC (1U << 0) 306135669Scognet#define TMRx_ENABLE (1U << 1) 307135669Scognet#define TMRx_RELOAD (1U << 2) 308135669Scognet#define TMRx_CSEL_CORE (0 << 4) 309135669Scognet#define TMRx_CSEL_CORE_div4 (1 << 4) 310135669Scognet#define TMRx_CSEL_CORE_div8 (2 << 4) 311135669Scognet#define TMRx_CSEL_CORE_div16 (3 << 4) 312135669Scognet 313135669Scognet#define TISR_TMR0 (1U << 0) 314135669Scognet#define TISR_TMR1 (1U << 1) 315135669Scognet 316135669Scognet#define WDTCR_ENABLE1 0x1e1e1e1e 317135669Scognet#define WDTCR_ENABLE2 0xe1e1e1e1 318135669Scognet 319135669Scognet/* 320135669Scognet * Interrupt Controller Unit. 321135669Scognet * 322135669Scognet * INTCTL cp6 c0,0 0xffffe7d0 323135669Scognet * INTSTR cp6 c4,0 0xffffe7d4 324135669Scognet * IINTSRC cp6 c8,0 0xffffe7d8 325135669Scognet * FINTSRC cp6 c9,0 0xffffe7dc 326135669Scognet * PIRSR 0xffffe1ec 327135669Scognet */ 328135669Scognet 329135669Scognet#define ICU_PIRSR 0x01ec 330135669Scognet#define ICU_GPOE 0x07c4 331135669Scognet#define ICU_GPID 0x07c8 332135669Scognet#define ICU_GPOD 0x07cc 333135669Scognet 334135669Scognet/* 335135669Scognet * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE 336135669Scognet * INTERRUPTS. See i80321_icu.c 337135669Scognet */ 338135669Scognet#define ICU_INT_HPI 31 /* high priority interrupt */ 339135669Scognet#define ICU_INT_XINT0 27 /* external interrupts */ 340135669Scognet#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) 341135669Scognet#define ICU_INT_bit26 26 342161592Scognet 343161592Scognet#if defined (CPU_XSCALE_80219) 344161592Scognet#define ICU_INT_bit25 25 /* reserved */ 345161592Scognet#else 346161592Scognet/* CPU_XSCALE_80321 */ 347135669Scognet#define ICU_INT_SSP 25 /* SSP serial port */ 348161592Scognet#endif 349161592Scognet 350135669Scognet#define ICU_INT_MUE 24 /* msg unit error */ 351161592Scognet 352161592Scognet#if defined (CPU_XSCALE_80219) 353161592Scognet#define ICU_INT_bit23 23 /* reserved */ 354161592Scognet#else 355161592Scognet/* CPU_XSCALE_80321 */ 356135669Scognet#define ICU_INT_AAUE 23 /* AAU error */ 357161592Scognet#endif 358161592Scognet 359135669Scognet#define ICU_INT_bit22 22 360135669Scognet#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ 361135669Scognet#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ 362135669Scognet#define ICU_INT_MCUE 19 /* memory controller error */ 363135669Scognet#define ICU_INT_ATUE 18 /* ATU error */ 364135669Scognet#define ICU_INT_BIUE 17 /* bus interface unit error */ 365135669Scognet#define ICU_INT_PMU 16 /* XScale PMU */ 366135669Scognet#define ICU_INT_PPM 15 /* peripheral PMU */ 367135669Scognet#define ICU_INT_BIST 14 /* ATU Start BIST */ 368135669Scognet#define ICU_INT_MU 13 /* messaging unit */ 369135669Scognet#define ICU_INT_I2C1 12 /* i2c unit 1 */ 370135669Scognet#define ICU_INT_I2C0 11 /* i2c unit 0 */ 371135669Scognet#define ICU_INT_TMR1 10 /* timer 1 */ 372135669Scognet#define ICU_INT_TMR0 9 /* timer 0 */ 373135669Scognet#define ICU_INT_CPPM 8 /* core processor PMU */ 374161592Scognet 375161592Scognet#if defined(CPU_XSCALE_80219) 376161592Scognet#define ICU_INT_bit7 7 /* reserved */ 377161592Scognet#define ICU_INT_bit6 6 /* reserved */ 378161592Scognet#else 379161592Scognet/* CPU_XSCALE_80321 */ 380135669Scognet#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ 381135669Scognet#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ 382161592Scognet#endif 383161592Scognet 384135669Scognet#define ICU_INT_bit5 5 385135669Scognet#define ICU_INT_bit4 4 386135669Scognet#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ 387135669Scognet#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ 388135669Scognet#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ 389135669Scognet#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ 390135669Scognet 391161592Scognet#if defined (CPU_XSCALE_80219) 392161592Scognet#define ICU_INT_HWMASK (0xffffffff & \ 393161592Scognet ~((1 << ICU_INT_bit26) | \ 394161592Scognet (1 << ICU_INT_bit25) | \ 395161592Scognet (1 << ICU_INT_bit23) | \ 396161592Scognet (1 << ICU_INT_bit22) | \ 397161592Scognet (1 << ICU_INT_bit7) | \ 398161592Scognet (1 << ICU_INT_bit6) | \ 399161592Scognet (1 << ICU_INT_bit5) | \ 400161592Scognet (1 << ICU_INT_bit4))) 401161592Scognet 402161592Scognet#else 403161592Scognet/* CPU_XSCALE_80321 */ 404135669Scognet#define ICU_INT_HWMASK (0xffffffff & \ 405135669Scognet ~((1 << ICU_INT_bit26) | \ 406135669Scognet (1 << ICU_INT_bit22) | \ 407135669Scognet (1 << ICU_INT_bit5) | \ 408135669Scognet (1 << ICU_INT_bit4))) 409161592Scognet#endif 410135669Scognet 411135669Scognet/* 412135669Scognet * SSP Serial Port 413135669Scognet */ 414161592Scognet#if defined (CPU_XSCALE_80321) 415135669Scognet 416135669Scognet#define SSP_SSCR0 0x00 /* SSC control 0 */ 417135669Scognet#define SSP_SSCR1 0x04 /* SSC control 1 */ 418135669Scognet#define SSP_SSSR 0x08 /* SSP status */ 419135669Scognet#define SSP_SSITR 0x0c /* SSP interrupt test */ 420135669Scognet#define SSP_SSDR 0x10 /* SSP data */ 421135669Scognet 422135669Scognet#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */ 423135669Scognet#define SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph Iface */ 424135669Scognet#define SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */ 425135669Scognet#define SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */ 426135669Scognet#define SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */ 427135669Scognet#define SSP_SSCR0_ECS (1U << 6)/* external clock select */ 428135669Scognet#define SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */ 429135669Scognet#define SSP_SSCR0_SCR(x) ((x) << 8)/* serial clock rate */ 430135669Scognet /* bit rate = 3.6864 * 10e6 / 431135669Scognet (2 * (SCR + 1)) */ 432135669Scognet 433135669Scognet#define SSP_SSCR1_RIE (1U << 0)/* Rx FIFO interrupt enable */ 434135669Scognet#define SSP_SSCR1_TIE (1U << 1)/* Tx FIFO interrupt enable */ 435135669Scognet#define SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */ 436135669Scognet#define SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 = high) */ 437135669Scognet#define SSP_SSCR1_SPH (1U << 4)/* Moto SPI SSCLK phase: 438135669Scognet 0 = inactive full at start, 439135669Scognet 1/2 at end of frame 440135669Scognet 1 = inactive 1/2 at start, 441135669Scognet full at end of frame */ 442135669Scognet#define SSP_SSCR1_MWDS (1U << 5)/* Microwire data size: 443135669Scognet 0 = 8 bit 444135669Scognet 1 = 16 bit */ 445135669Scognet#define SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */ 446135669Scognet#define SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */ 447135669Scognet#define SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */ 448135669Scognet#define SSP_SSCR1_STRF (1U << 15)/* FIFO write/read FIFO select: 449135669Scognet 0 = Tx FIFO 450135669Scognet 1 = Rx FIFO */ 451135669Scognet 452135669Scognet#define SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */ 453135669Scognet#define SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */ 454135669Scognet#define SSP_SSSR_BSY (1U << 4)/* SSP is busy */ 455135669Scognet#define SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */ 456135669Scognet#define SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */ 457135669Scognet#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */ 458135669Scognet#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */ 459135669Scognet#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */ 460135669Scognet 461135669Scognet#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */ 462135669Scognet#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */ 463135669Scognet#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */ 464135669Scognet 465161592Scognet#endif /* CPU_XSCALE_80321 */ 466161592Scognet 467135669Scognet/* 468135669Scognet * Peripheral Bus Interface Unit 469135669Scognet */ 470135669Scognet 471135669Scognet#define PBIU_PBCR 0x00 /* PBIU Control Register */ 472135669Scognet#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ 473135669Scognet#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ 474135669Scognet#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ 475135669Scognet#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ 476135669Scognet#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ 477135669Scognet#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ 478135669Scognet#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ 479135669Scognet#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ 480135669Scognet#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ 481135669Scognet#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ 482135669Scognet#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ 483135669Scognet#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ 484135669Scognet#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ 485135669Scognet#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ 486135669Scognet#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ 487135669Scognet#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ 488135669Scognet 489135669Scognet#define PBIU_PBCR_PBIEN (1 << 0) 490135669Scognet#define PBIU_PBCR_PBI100 (1 << 1) 491135669Scognet#define PBIU_PBCR_PBI66 (2 << 1) 492135669Scognet#define PBIU_PBCR_PBI33 (3 << 1) 493135669Scognet#define PBIU_PBCR_PBBEN (1 << 3) 494135669Scognet 495135669Scognet#define PBIU_PBARx_WIDTH8 (0 << 0) 496135669Scognet#define PBIU_PBARx_WIDTH16 (1 << 0) 497135669Scognet#define PBIU_PBARx_WIDTH32 (2 << 0) 498135669Scognet#define PBIU_PBARx_ADWAIT4 (0 << 2) 499135669Scognet#define PBIU_PBARx_ADWAIT8 (1 << 2) 500135669Scognet#define PBIU_PBARx_ADWAIT12 (2 << 2) 501135669Scognet#define PBIU_PBARx_ADWAIT16 (3 << 2) 502135669Scognet#define PBIU_PBARx_ADWAIT20 (4 << 2) 503135669Scognet#define PBIU_PBARx_RCWAIT1 (0 << 6) 504135669Scognet#define PBIU_PBARx_RCWAIT4 (1 << 6) 505135669Scognet#define PBIU_PBARx_RCWAIT8 (2 << 6) 506135669Scognet#define PBIU_PBARx_RCWAIT12 (3 << 6) 507135669Scognet#define PBIU_PBARx_RCWAIT16 (4 << 6) 508135669Scognet#define PBIU_PBARx_RCWAIT20 (5 << 6) 509135669Scognet#define PBIU_PBARx_FWE (1 << 9) 510135669Scognet#define PBIU_BASE_MASK 0xfffff000U 511135669Scognet 512135669Scognet#define PBIU_PBLRx_SIZE(x) (~((x) - 1)) 513135669Scognet 514135669Scognet/* 515135669Scognet * Messaging Unit 516135669Scognet */ 517135669Scognet#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ 518135669Scognet#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ 519135669Scognet#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ 520135669Scognet#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */ 521135669Scognet#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */ 522135669Scognet#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ 523135669Scognet#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ 524135669Scognet#define MU_ODR 0x002c /* MU Outbound Doorbell Register */ 525135669Scognet#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ 526135669Scognet#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ 527135669Scognet#define MU_MUCR 0x0050 /* MU Configuration Register */ 528135669Scognet#define MU_QBAR 0x0054 /* MU Queue Base Address Register */ 529135669Scognet#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ 530135669Scognet#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ 531135669Scognet#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ 532135669Scognet#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ 533135669Scognet#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ 534135669Scognet#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ 535135669Scognet#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ 536135669Scognet#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ 537135669Scognet#define MU_IAR 0x0080 /* MU Index Address Register */ 538135669Scognet 539135669Scognet#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ 540135669Scognet#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ 541135669Scognet#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ 542135669Scognet#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ 543135669Scognet#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ 544135669Scognet#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ 545135669Scognet#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ 546135669Scognet 547135669Scognet#endif /* _ARM_XSCALE_I80321REG_H_ */ 548