1/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */ 2 3/*- 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 * 39 */ 40 41#ifndef _ARM_XSCALE_I80321REG_H_ 42#define _ARM_XSCALE_I80321REG_H_ 43 44/* 45 * Register definitions for the Intel 80321 (``Verde'') I/O processor, 46 * based on the XScale core. 47 */ 48 49/* 50 * Base i80321 memory map: 51 * 52 * 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window 53 * 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows 54 * 0x9002.0000 - 0xffff.dfff External Memory 55 * 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers 56 * 0xffff.e900 - 0xffff.ffff Reserved 57 */ 58 59#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL 60#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL 61 62#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL 63#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL 64 65#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL 66#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL 67 68#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL 69 70#define VERDE_EXTMEM_BASE 0x90020000UL 71 72#define VERDE_PMMR_BASE 0xffffe000UL 73#define VERDE_PMMR_SIZE 0x00001700UL 74 75/* 76 * Peripheral Memory Mapped Registers. Defined as offsets 77 * from the VERDE_PMMR_BASE. 78 */ 79#define VERDE_ATU_BASE 0x0100 80#define VERDE_ATU_SIZE 0x0100 81 82#define VERDE_MU_BASE 0x0300 83#define VERDE_MU_SIZE 0x0100 84 85#define VERDE_DMA_BASE 0x0400 86#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) 87#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) 88#define VERDE_DMA_SIZE 0x0100 89#define VERDE_DMA_CHSIZE 0x0040 90 91#define VERDE_MCU_BASE 0x0500 92#define VERDE_MCU_SIZE 0x0100 93 94#define VERDE_PBIU_BASE 0x0680 95#define VERDE_PBIU_SIZE 0x0080 96 97#define VERDE_I2C_BASE 0x1680 98#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) 99#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) 100#define VERDE_I2C_SIZE 0x0080 101#define VERDE_I2C_CHSIZE 0x0020 102 103/* 104 * Address Translation Unit 105 */ 106 /* 0x00 - 0x38 -- PCI configuration space header */ 107#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ 108#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ 109#define ATU_ERLR 0x48 /* Expansion ROM Limit */ 110#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ 111#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ 112#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ 113#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ 114#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ 115#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ 116#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ 117#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ 118#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ 119#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ 120#define ATU_ATUCR 0x80 /* ATU Configuration */ 121#define ATU_PCSR 0x84 /* PCI Configuration and Status */ 122#define ATU_ATUISR 0x88 /* ATU Interrupt Status */ 123#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ 124#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ 125#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ 126#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ 127#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ 128#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ 129#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ 130#define ATU_MSI_PORT 0xb4 /* MSI port */ 131#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ 132#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ 133#define ATU_PCI_X_NEXT 0xe1 /* (1) */ 134#define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ 135#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ 136 137#define ATUCR_DRC_ALIAS (1U << 19) 138#define ATUCR_DAU2GXEN (1U << 18) 139#define ATUCR_P_SERR_MA (1U << 16) 140#define ATUCR_DTS (1U << 15) 141#define ATUCR_P_SERR_DIE (1U << 9) 142#define ATUCR_DAE (1U << 8) 143#define ATUCR_BIST_IE (1U << 3) 144#define ATUCR_OUT_EN (1U << 1) 145 146#define PCSR_DAAAPE (1U << 18) 147#define PCSR_PCI_X_CAP (3U << 16) 148#define PCSR_PCI_X_CAP_BORING (0 << 16) 149#define PCSR_PCI_X_CAP_66 (1U << 16) 150#define PCSR_PCI_X_CAP_100 (2U << 16) 151#define PCSR_PCI_X_CAP_133 (3U << 16) 152#define PCSR_OTQB (1U << 15) 153#define PCSR_IRTQB (1U << 14) 154#define PCSR_DTV (1U << 12) 155#define PCSR_BUS66 (1U << 10) 156#define PCSR_BUS64 (1U << 8) 157#define PCSR_RIB (1U << 5) 158#define PCSR_RPB (1U << 4) 159#define PCSR_CCR (1U << 2) 160#define PCSR_CPR (1U << 1) 161 162#define ATUISR_IMW1BU (1U << 14) 163#define ATUISR_ISCEM (1U << 13) 164#define ATUISR_RSCEM (1U << 12) 165#define ATUISR_PST (1U << 11) 166#define ATUISR_P_SERR_ASRT (1U << 10) 167#define ATUISR_DPE (1U << 9) 168#define ATUISR_BIST (1U << 8) 169#define ATUISR_IBMA (1U << 7) 170#define ATUISR_P_SERR_DET (1U << 4) 171#define ATUISR_PMA (1U << 3) 172#define ATUISR_PTAM (1U << 2) 173#define ATUISR_PTAT (1U << 1) 174#define ATUISR_PMPE (1U << 0) 175 176#define ATUIMR_IMW1BU (1U << 11) 177#define ATUIMR_ISCEM (1U << 10) 178#define ATUIMR_RSCEM (1U << 9) 179#define ATUIMR_PST (1U << 8) 180#define ATUIMR_DPE (1U << 7) 181#define ATUIMR_P_SERR_ASRT (1U << 6) 182#define ATUIMR_PMA (1U << 5) 183#define ATUIMR_PTAM (1U << 4) 184#define ATUIMR_PTAT (1U << 3) 185#define ATUIMR_PMPE (1U << 2) 186#define ATUIMR_IE_SERR_EN (1U << 1) 187#define ATUIMR_ECC_TAE (1U << 0) 188 189#define PCIXCMD_MOST_1 (0 << 4) 190#define PCIXCMD_MOST_2 (1 << 4) 191#define PCIXCMD_MOST_3 (2 << 4) 192#define PCIXCMD_MOST_4 (3 << 4) 193#define PCIXCMD_MOST_8 (4 << 4) 194#define PCIXCMD_MOST_12 (5 << 4) 195#define PCIXCMD_MOST_16 (6 << 4) 196#define PCIXCMD_MOST_32 (7 << 4) 197#define PCIXCMD_MOST_MASK (7 << 4) 198#define PCIXCMD_MMRBC_512 (0 << 2) 199#define PCIXCMD_MMRBC_1024 (1 << 2) 200#define PCIXCMD_MMRBC_2048 (2 << 2) 201#define PCIXCMD_MMRBC_4096 (3 << 2) 202#define PCIXCMD_MMRBC_MASK (3 << 2) 203#define PCIXCMD_ERO (1U << 1) 204#define PCIXCMD_DPERE (1U << 0) 205 206#define PCIXSR_RSCEM (1U << 29) 207#define PCIXSR_DMCRS_MASK (7 << 26) 208#define PCIXSR_DMOST_MASK (7 << 23) 209#define PCIXSR_COMPLEX (1U << 20) 210#define PCIXSR_USC (1U << 19) 211#define PCIXSR_SCD (1U << 18) 212#define PCIXSR_133_CAP (1U << 17) 213#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ 214#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) 215#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) 216#define PCIXSR_FUNCNO(x) ((x) & 0x7) 217 218/* 219 * Memory Controller Unit 220 */ 221#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ 222#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ 223#define MCU_SDBR 0x08 /* SDRAM Base Register */ 224#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ 225#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ 226#define MCU_ECCR 0x34 /* ECC Control Register */ 227#define MCU_ELOG0 0x38 /* ECC Log 0 */ 228#define MCU_ELOG1 0x3c /* ECC Log 1 */ 229#define MCU_ECAR0 0x40 /* ECC address 0 */ 230#define MCU_ECAR1 0x44 /* ECC address 1 */ 231#define MCU_ECTST 0x48 /* ECC test register */ 232#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ 233#define MCU_RFR 0x50 /* Refresh Frequency Register */ 234#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ 235#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ 236#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ 237#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ 238#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ 239#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ 240#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ 241#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ 242#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ 243#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ 244#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ 245#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ 246#define MCU_DSDR 0x84 /* Data Strobe Delay Register */ 247#define MCU_REDR 0x88 /* Rx Enable Delay Register */ 248 249#define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ 250#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ 251 252#define SBRx_TECH (1U << 31) 253#define SBRx_BOUND 0x0000003f 254 255#define ECCR_SBERE (1U << 0) 256#define ECCR_MBERE (1U << 1) 257#define ECCR_SBECE (1U << 2) 258#define ECCR_ECCEN (1U << 3) 259 260#define ELOGx_SYNDROME 0x000000ff 261#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ 262#define ELOGx_RW (1U << 12) /* 1 = write error */ 263 /* 264 * Dev ID Func Requester 265 * 2 0 XScale core 266 * 2 1 ATU 267 * 13 0 DMA channel 0 268 * 13 1 DMA channel 1 269 * 26 0 ATU 270 */ 271#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) 272#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) 273 274#define MCISR_ECC_ERR0 (1U << 0) 275#define MCISR_ECC_ERR1 (1U << 1) 276#define MCISR_ECC_ERRN (1U << 2) 277 278/* 279 * Timers 280 * 281 * The i80321 timer registers are available in both memory-mapped 282 * and coprocessor spaces. Most of the registers are read-only 283 * if memory-mapped, so we access them via coprocessor space. 284 * 285 * TMR0 cp6 c0,1 0xffffe7e0 286 * TMR1 cp6 c1,1 0xffffe7e4 287 * TCR0 cp6 c2,1 0xffffe7e8 288 * TCR1 cp6 c3,1 0xffffe7ec 289 * TRR0 cp6 c4,1 0xffffe7f0 290 * TRR1 cp6 c5,1 0xffffe7f4 291 * TISR cp6 c6,1 0xffffe7f8 292 * WDTCR cp6 c7,1 0xffffe7fc 293 */ 294 295#define TMRx_TC (1U << 0) 296#define TMRx_ENABLE (1U << 1) 297#define TMRx_RELOAD (1U << 2) 298#define TMRx_CSEL_CORE (0 << 4) 299#define TMRx_CSEL_CORE_div4 (1 << 4) 300#define TMRx_CSEL_CORE_div8 (2 << 4) 301#define TMRx_CSEL_CORE_div16 (3 << 4) 302 303#define TISR_TMR0 (1U << 0) 304#define TISR_TMR1 (1U << 1) 305 306#define WDTCR_ENABLE1 0x1e1e1e1e 307#define WDTCR_ENABLE2 0xe1e1e1e1 308 309/* 310 * Interrupt Controller Unit. 311 * 312 * INTCTL cp6 c0,0 0xffffe7d0 313 * INTSTR cp6 c4,0 0xffffe7d4 314 * IINTSRC cp6 c8,0 0xffffe7d8 315 * FINTSRC cp6 c9,0 0xffffe7dc 316 * PIRSR 0xffffe1ec 317 */ 318 319#define ICU_PIRSR 0x01ec 320#define ICU_GPOE 0x07c4 321#define ICU_GPID 0x07c8 322#define ICU_GPOD 0x07cc 323 324/* 325 * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE 326 * INTERRUPTS. See i80321_icu.c 327 */ 328#define ICU_INT_HPI 31 /* high priority interrupt */ 329#define ICU_INT_XINT0 27 /* external interrupts */ 330#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) 331#define ICU_INT_bit26 26 332 333/* CPU_XSCALE_80321 */ 334#define ICU_INT_SSP 25 /* SSP serial port */ 335 336#define ICU_INT_MUE 24 /* msg unit error */ 337 338/* CPU_XSCALE_80321 */ 339#define ICU_INT_AAUE 23 /* AAU error */ 340 341#define ICU_INT_bit22 22 342#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ 343#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ 344#define ICU_INT_MCUE 19 /* memory controller error */ 345#define ICU_INT_ATUE 18 /* ATU error */ 346#define ICU_INT_BIUE 17 /* bus interface unit error */ 347#define ICU_INT_PMU 16 /* XScale PMU */ 348#define ICU_INT_PPM 15 /* peripheral PMU */ 349#define ICU_INT_BIST 14 /* ATU Start BIST */ 350#define ICU_INT_MU 13 /* messaging unit */ 351#define ICU_INT_I2C1 12 /* i2c unit 1 */ 352#define ICU_INT_I2C0 11 /* i2c unit 0 */ 353#define ICU_INT_TMR1 10 /* timer 1 */ 354#define ICU_INT_TMR0 9 /* timer 0 */ 355#define ICU_INT_CPPM 8 /* core processor PMU */ 356 357/* CPU_XSCALE_80321 */ 358#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ 359#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ 360 361#define ICU_INT_bit5 5 362#define ICU_INT_bit4 4 363#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ 364#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ 365#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ 366#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ 367 368/* CPU_XSCALE_80321 */ 369#define ICU_INT_HWMASK (0xffffffff & \ 370 ~((1 << ICU_INT_bit26) | \ 371 (1 << ICU_INT_bit22) | \ 372 (1 << ICU_INT_bit5) | \ 373 (1 << ICU_INT_bit4))) 374 375/* 376 * Peripheral Bus Interface Unit 377 */ 378 379#define PBIU_PBCR 0x00 /* PBIU Control Register */ 380#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ 381#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ 382#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ 383#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ 384#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ 385#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ 386#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ 387#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ 388#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ 389#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ 390#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ 391#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ 392#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ 393#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ 394#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ 395#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ 396 397#define PBIU_PBCR_PBIEN (1 << 0) 398#define PBIU_PBCR_PBI100 (1 << 1) 399#define PBIU_PBCR_PBI66 (2 << 1) 400#define PBIU_PBCR_PBI33 (3 << 1) 401#define PBIU_PBCR_PBBEN (1 << 3) 402 403#define PBIU_PBARx_WIDTH8 (0 << 0) 404#define PBIU_PBARx_WIDTH16 (1 << 0) 405#define PBIU_PBARx_WIDTH32 (2 << 0) 406#define PBIU_PBARx_ADWAIT4 (0 << 2) 407#define PBIU_PBARx_ADWAIT8 (1 << 2) 408#define PBIU_PBARx_ADWAIT12 (2 << 2) 409#define PBIU_PBARx_ADWAIT16 (3 << 2) 410#define PBIU_PBARx_ADWAIT20 (4 << 2) 411#define PBIU_PBARx_RCWAIT1 (0 << 6) 412#define PBIU_PBARx_RCWAIT4 (1 << 6) 413#define PBIU_PBARx_RCWAIT8 (2 << 6) 414#define PBIU_PBARx_RCWAIT12 (3 << 6) 415#define PBIU_PBARx_RCWAIT16 (4 << 6) 416#define PBIU_PBARx_RCWAIT20 (5 << 6) 417#define PBIU_PBARx_FWE (1 << 9) 418#define PBIU_BASE_MASK 0xfffff000U 419 420#define PBIU_PBLRx_SIZE(x) (~((x) - 1)) 421 422/* 423 * Messaging Unit 424 */ 425#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ 426#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ 427#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ 428#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */ 429#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */ 430#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ 431#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ 432#define MU_ODR 0x002c /* MU Outbound Doorbell Register */ 433#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ 434#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ 435#define MU_MUCR 0x0050 /* MU Configuration Register */ 436#define MU_QBAR 0x0054 /* MU Queue Base Address Register */ 437#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ 438#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ 439#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ 440#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ 441#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ 442#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ 443#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ 444#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ 445#define MU_IAR 0x0080 /* MU Index Address Register */ 446 447#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ 448#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ 449#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ 450#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ 451#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ 452#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ 453#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ 454 455#endif /* _ARM_XSCALE_I80321REG_H_ */ 456