i80321reg.h revision 236987
150476Speter/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */ 28478Swollman 38478Swollman/*- 474815Sru * Copyright (c) 2002 Wasabi Systems, Inc. 58478Swollman * All rights reserved. 68478Swollman * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD: head/sys/arm/xscale/i80321/i80321reg.h 236987 2012-06-13 04:38:09Z imp $ 38 * 39 */ 40 41#ifndef _ARM_XSCALE_I80321REG_H_ 42#define _ARM_XSCALE_I80321REG_H_ 43 44/* 45 * Register definitions for the Intel 80321 (``Verde'') I/O processor, 46 * based on the XScale core. 47 */ 48 49/* 50 * Base i80321 memory map: 51 * 52 * 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window 53 * 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows 54 * 0x9002.0000 - 0xffff.dfff External Memory 55 * 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers 56 * 0xffff.e900 - 0xffff.ffff Reserved 57 */ 58 59#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL 60#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL 61 62#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL 63#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL 64 65#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL 66#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL 67 68#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL 69 70#define VERDE_EXTMEM_BASE 0x90020000UL 71 72#define VERDE_PMMR_BASE 0xffffe000UL 73#define VERDE_PMMR_SIZE 0x00001700UL 74 75/* 76 * Peripheral Memory Mapped Registers. Defined as offsets 77 * from the VERDE_PMMR_BASE. 78 */ 79#define VERDE_ATU_BASE 0x0100 80#define VERDE_ATU_SIZE 0x0100 81 82#define VERDE_MU_BASE 0x0300 83#define VERDE_MU_SIZE 0x0100 84 85#define VERDE_DMA_BASE 0x0400 86#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) 87#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) 88#define VERDE_DMA_SIZE 0x0100 89#define VERDE_DMA_CHSIZE 0x0040 90 91#define VERDE_MCU_BASE 0x0500 92#define VERDE_MCU_SIZE 0x0100 93 94#if defined(CPU_XSCALE_80321) 95#define VERDE_SSP_BASE 0x0600 96#define VERDE_SSP_SIZE 0x0080 97#endif 98 99#define VERDE_PBIU_BASE 0x0680 100#define VERDE_PBIU_SIZE 0x0080 101 102#if defined(CPU_XSCALE_80321) 103#define VERDE_AAU_BASE 0x0800 104#define VERDE_AAU_SIZE 0x0100 105#endif 106 107#define VERDE_I2C_BASE 0x1680 108#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) 109#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) 110#define VERDE_I2C_SIZE 0x0080 111#define VERDE_I2C_CHSIZE 0x0020 112 113/* 114 * Address Translation Unit 115 */ 116 /* 0x00 - 0x38 -- PCI configuration space header */ 117#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ 118#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ 119#define ATU_ERLR 0x48 /* Expansion ROM Limit */ 120#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ 121#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ 122#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ 123#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ 124#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ 125#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ 126#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ 127#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ 128#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ 129#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ 130#define ATU_ATUCR 0x80 /* ATU Configuration */ 131#define ATU_PCSR 0x84 /* PCI Configuration and Status */ 132#define ATU_ATUISR 0x88 /* ATU Interrupt Status */ 133#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ 134#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ 135#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ 136#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ 137#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ 138#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ 139#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ 140#define ATU_MSI_PORT 0xb4 /* MSI port */ 141#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ 142#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ 143#define ATU_PCI_X_NEXT 0xe1 /* (1) */ 144#define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ 145#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ 146 147#define ATUCR_DRC_ALIAS (1U << 19) 148#define ATUCR_DAU2GXEN (1U << 18) 149#define ATUCR_P_SERR_MA (1U << 16) 150#define ATUCR_DTS (1U << 15) 151#define ATUCR_P_SERR_DIE (1U << 9) 152#define ATUCR_DAE (1U << 8) 153#define ATUCR_BIST_IE (1U << 3) 154#define ATUCR_OUT_EN (1U << 1) 155 156#define PCSR_DAAAPE (1U << 18) 157#define PCSR_PCI_X_CAP (3U << 16) 158#define PCSR_PCI_X_CAP_BORING (0 << 16) 159#define PCSR_PCI_X_CAP_66 (1U << 16) 160#define PCSR_PCI_X_CAP_100 (2U << 16) 161#define PCSR_PCI_X_CAP_133 (3U << 16) 162#define PCSR_OTQB (1U << 15) 163#define PCSR_IRTQB (1U << 14) 164#define PCSR_DTV (1U << 12) 165#define PCSR_BUS66 (1U << 10) 166#define PCSR_BUS64 (1U << 8) 167#define PCSR_RIB (1U << 5) 168#define PCSR_RPB (1U << 4) 169#define PCSR_CCR (1U << 2) 170#define PCSR_CPR (1U << 1) 171 172#define ATUISR_IMW1BU (1U << 14) 173#define ATUISR_ISCEM (1U << 13) 174#define ATUISR_RSCEM (1U << 12) 175#define ATUISR_PST (1U << 11) 176#define ATUISR_P_SERR_ASRT (1U << 10) 177#define ATUISR_DPE (1U << 9) 178#define ATUISR_BIST (1U << 8) 179#define ATUISR_IBMA (1U << 7) 180#define ATUISR_P_SERR_DET (1U << 4) 181#define ATUISR_PMA (1U << 3) 182#define ATUISR_PTAM (1U << 2) 183#define ATUISR_PTAT (1U << 1) 184#define ATUISR_PMPE (1U << 0) 185 186#define ATUIMR_IMW1BU (1U << 11) 187#define ATUIMR_ISCEM (1U << 10) 188#define ATUIMR_RSCEM (1U << 9) 189#define ATUIMR_PST (1U << 8) 190#define ATUIMR_DPE (1U << 7) 191#define ATUIMR_P_SERR_ASRT (1U << 6) 192#define ATUIMR_PMA (1U << 5) 193#define ATUIMR_PTAM (1U << 4) 194#define ATUIMR_PTAT (1U << 3) 195#define ATUIMR_PMPE (1U << 2) 196#define ATUIMR_IE_SERR_EN (1U << 1) 197#define ATUIMR_ECC_TAE (1U << 0) 198 199#define PCIXCMD_MOST_1 (0 << 4) 200#define PCIXCMD_MOST_2 (1 << 4) 201#define PCIXCMD_MOST_3 (2 << 4) 202#define PCIXCMD_MOST_4 (3 << 4) 203#define PCIXCMD_MOST_8 (4 << 4) 204#define PCIXCMD_MOST_12 (5 << 4) 205#define PCIXCMD_MOST_16 (6 << 4) 206#define PCIXCMD_MOST_32 (7 << 4) 207#define PCIXCMD_MOST_MASK (7 << 4) 208#define PCIXCMD_MMRBC_512 (0 << 2) 209#define PCIXCMD_MMRBC_1024 (1 << 2) 210#define PCIXCMD_MMRBC_2048 (2 << 2) 211#define PCIXCMD_MMRBC_4096 (3 << 2) 212#define PCIXCMD_MMRBC_MASK (3 << 2) 213#define PCIXCMD_ERO (1U << 1) 214#define PCIXCMD_DPERE (1U << 0) 215 216#define PCIXSR_RSCEM (1U << 29) 217#define PCIXSR_DMCRS_MASK (7 << 26) 218#define PCIXSR_DMOST_MASK (7 << 23) 219#define PCIXSR_COMPLEX (1U << 20) 220#define PCIXSR_USC (1U << 19) 221#define PCIXSR_SCD (1U << 18) 222#define PCIXSR_133_CAP (1U << 17) 223#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ 224#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) 225#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) 226#define PCIXSR_FUNCNO(x) ((x) & 0x7) 227 228/* 229 * Memory Controller Unit 230 */ 231#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ 232#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ 233#define MCU_SDBR 0x08 /* SDRAM Base Register */ 234#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ 235#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ 236#define MCU_ECCR 0x34 /* ECC Control Register */ 237#define MCU_ELOG0 0x38 /* ECC Log 0 */ 238#define MCU_ELOG1 0x3c /* ECC Log 1 */ 239#define MCU_ECAR0 0x40 /* ECC address 0 */ 240#define MCU_ECAR1 0x44 /* ECC address 1 */ 241#define MCU_ECTST 0x48 /* ECC test register */ 242#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ 243#define MCU_RFR 0x50 /* Refresh Frequency Register */ 244#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ 245#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ 246#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ 247#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ 248#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ 249#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ 250#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ 251#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ 252#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ 253#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ 254#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ 255#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ 256#define MCU_DSDR 0x84 /* Data Strobe Delay Register */ 257#define MCU_REDR 0x88 /* Rx Enable Delay Register */ 258 259#define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ 260#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ 261 262#define SBRx_TECH (1U << 31) 263#define SBRx_BOUND 0x0000003f 264 265#define ECCR_SBERE (1U << 0) 266#define ECCR_MBERE (1U << 1) 267#define ECCR_SBECE (1U << 2) 268#define ECCR_ECCEN (1U << 3) 269 270#define ELOGx_SYNDROME 0x000000ff 271#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ 272#define ELOGx_RW (1U << 12) /* 1 = write error */ 273 /* 274 * Dev ID Func Requester 275 * 2 0 XScale core 276 * 2 1 ATU 277 * 13 0 DMA channel 0 278 * 13 1 DMA channel 1 279 * 26 0 ATU 280 */ 281#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) 282#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) 283 284#define MCISR_ECC_ERR0 (1U << 0) 285#define MCISR_ECC_ERR1 (1U << 1) 286#define MCISR_ECC_ERRN (1U << 2) 287 288/* 289 * Timers 290 * 291 * The i80321 timer registers are available in both memory-mapped 292 * and coprocessor spaces. Most of the registers are read-only 293 * if memory-mapped, so we access them via coprocessor space. 294 * 295 * TMR0 cp6 c0,1 0xffffe7e0 296 * TMR1 cp6 c1,1 0xffffe7e4 297 * TCR0 cp6 c2,1 0xffffe7e8 298 * TCR1 cp6 c3,1 0xffffe7ec 299 * TRR0 cp6 c4,1 0xffffe7f0 300 * TRR1 cp6 c5,1 0xffffe7f4 301 * TISR cp6 c6,1 0xffffe7f8 302 * WDTCR cp6 c7,1 0xffffe7fc 303 */ 304 305#define TMRx_TC (1U << 0) 306#define TMRx_ENABLE (1U << 1) 307#define TMRx_RELOAD (1U << 2) 308#define TMRx_CSEL_CORE (0 << 4) 309#define TMRx_CSEL_CORE_div4 (1 << 4) 310#define TMRx_CSEL_CORE_div8 (2 << 4) 311#define TMRx_CSEL_CORE_div16 (3 << 4) 312 313#define TISR_TMR0 (1U << 0) 314#define TISR_TMR1 (1U << 1) 315 316#define WDTCR_ENABLE1 0x1e1e1e1e 317#define WDTCR_ENABLE2 0xe1e1e1e1 318 319/* 320 * Interrupt Controller Unit. 321 * 322 * INTCTL cp6 c0,0 0xffffe7d0 323 * INTSTR cp6 c4,0 0xffffe7d4 324 * IINTSRC cp6 c8,0 0xffffe7d8 325 * FINTSRC cp6 c9,0 0xffffe7dc 326 * PIRSR 0xffffe1ec 327 */ 328 329#define ICU_PIRSR 0x01ec 330#define ICU_GPOE 0x07c4 331#define ICU_GPID 0x07c8 332#define ICU_GPOD 0x07cc 333 334/* 335 * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE 336 * INTERRUPTS. See i80321_icu.c 337 */ 338#define ICU_INT_HPI 31 /* high priority interrupt */ 339#define ICU_INT_XINT0 27 /* external interrupts */ 340#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) 341#define ICU_INT_bit26 26 342 343#if defined (CPU_XSCALE_80219) 344#define ICU_INT_bit25 25 /* reserved */ 345#else 346/* CPU_XSCALE_80321 */ 347#define ICU_INT_SSP 25 /* SSP serial port */ 348#endif 349 350#define ICU_INT_MUE 24 /* msg unit error */ 351 352#if defined (CPU_XSCALE_80219) 353#define ICU_INT_bit23 23 /* reserved */ 354#else 355/* CPU_XSCALE_80321 */ 356#define ICU_INT_AAUE 23 /* AAU error */ 357#endif 358 359#define ICU_INT_bit22 22 360#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ 361#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ 362#define ICU_INT_MCUE 19 /* memory controller error */ 363#define ICU_INT_ATUE 18 /* ATU error */ 364#define ICU_INT_BIUE 17 /* bus interface unit error */ 365#define ICU_INT_PMU 16 /* XScale PMU */ 366#define ICU_INT_PPM 15 /* peripheral PMU */ 367#define ICU_INT_BIST 14 /* ATU Start BIST */ 368#define ICU_INT_MU 13 /* messaging unit */ 369#define ICU_INT_I2C1 12 /* i2c unit 1 */ 370#define ICU_INT_I2C0 11 /* i2c unit 0 */ 371#define ICU_INT_TMR1 10 /* timer 1 */ 372#define ICU_INT_TMR0 9 /* timer 0 */ 373#define ICU_INT_CPPM 8 /* core processor PMU */ 374 375#if defined(CPU_XSCALE_80219) 376#define ICU_INT_bit7 7 /* reserved */ 377#define ICU_INT_bit6 6 /* reserved */ 378#else 379/* CPU_XSCALE_80321 */ 380#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ 381#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ 382#endif 383 384#define ICU_INT_bit5 5 385#define ICU_INT_bit4 4 386#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ 387#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ 388#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ 389#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ 390 391#if defined (CPU_XSCALE_80219) 392#define ICU_INT_HWMASK (0xffffffff & \ 393 ~((1 << ICU_INT_bit26) | \ 394 (1 << ICU_INT_bit25) | \ 395 (1 << ICU_INT_bit23) | \ 396 (1 << ICU_INT_bit22) | \ 397 (1 << ICU_INT_bit7) | \ 398 (1 << ICU_INT_bit6) | \ 399 (1 << ICU_INT_bit5) | \ 400 (1 << ICU_INT_bit4))) 401 402#else 403/* CPU_XSCALE_80321 */ 404#define ICU_INT_HWMASK (0xffffffff & \ 405 ~((1 << ICU_INT_bit26) | \ 406 (1 << ICU_INT_bit22) | \ 407 (1 << ICU_INT_bit5) | \ 408 (1 << ICU_INT_bit4))) 409#endif 410 411/* 412 * SSP Serial Port 413 */ 414#if defined (CPU_XSCALE_80321) 415 416#define SSP_SSCR0 0x00 /* SSC control 0 */ 417#define SSP_SSCR1 0x04 /* SSC control 1 */ 418#define SSP_SSSR 0x08 /* SSP status */ 419#define SSP_SSITR 0x0c /* SSP interrupt test */ 420#define SSP_SSDR 0x10 /* SSP data */ 421 422#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */ 423#define SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph Iface */ 424#define SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */ 425#define SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */ 426#define SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */ 427#define SSP_SSCR0_ECS (1U << 6)/* external clock select */ 428#define SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */ 429#define SSP_SSCR0_SCR(x) ((x) << 8)/* serial clock rate */ 430 /* bit rate = 3.6864 * 10e6 / 431 (2 * (SCR + 1)) */ 432 433#define SSP_SSCR1_RIE (1U << 0)/* Rx FIFO interrupt enable */ 434#define SSP_SSCR1_TIE (1U << 1)/* Tx FIFO interrupt enable */ 435#define SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */ 436#define SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 = high) */ 437#define SSP_SSCR1_SPH (1U << 4)/* Moto SPI SSCLK phase: 438 0 = inactive full at start, 439 1/2 at end of frame 440 1 = inactive 1/2 at start, 441 full at end of frame */ 442#define SSP_SSCR1_MWDS (1U << 5)/* Microwire data size: 443 0 = 8 bit 444 1 = 16 bit */ 445#define SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */ 446#define SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */ 447#define SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */ 448#define SSP_SSCR1_STRF (1U << 15)/* FIFO write/read FIFO select: 449 0 = Tx FIFO 450 1 = Rx FIFO */ 451 452#define SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */ 453#define SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */ 454#define SSP_SSSR_BSY (1U << 4)/* SSP is busy */ 455#define SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */ 456#define SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */ 457#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */ 458#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */ 459#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */ 460 461#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */ 462#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */ 463#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */ 464 465#endif /* CPU_XSCALE_80321 */ 466 467/* 468 * Peripheral Bus Interface Unit 469 */ 470 471#define PBIU_PBCR 0x00 /* PBIU Control Register */ 472#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ 473#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ 474#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ 475#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ 476#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ 477#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ 478#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ 479#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ 480#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ 481#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ 482#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ 483#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ 484#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ 485#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ 486#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ 487#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ 488 489#define PBIU_PBCR_PBIEN (1 << 0) 490#define PBIU_PBCR_PBI100 (1 << 1) 491#define PBIU_PBCR_PBI66 (2 << 1) 492#define PBIU_PBCR_PBI33 (3 << 1) 493#define PBIU_PBCR_PBBEN (1 << 3) 494 495#define PBIU_PBARx_WIDTH8 (0 << 0) 496#define PBIU_PBARx_WIDTH16 (1 << 0) 497#define PBIU_PBARx_WIDTH32 (2 << 0) 498#define PBIU_PBARx_ADWAIT4 (0 << 2) 499#define PBIU_PBARx_ADWAIT8 (1 << 2) 500#define PBIU_PBARx_ADWAIT12 (2 << 2) 501#define PBIU_PBARx_ADWAIT16 (3 << 2) 502#define PBIU_PBARx_ADWAIT20 (4 << 2) 503#define PBIU_PBARx_RCWAIT1 (0 << 6) 504#define PBIU_PBARx_RCWAIT4 (1 << 6) 505#define PBIU_PBARx_RCWAIT8 (2 << 6) 506#define PBIU_PBARx_RCWAIT12 (3 << 6) 507#define PBIU_PBARx_RCWAIT16 (4 << 6) 508#define PBIU_PBARx_RCWAIT20 (5 << 6) 509#define PBIU_PBARx_FWE (1 << 9) 510#define PBIU_BASE_MASK 0xfffff000U 511 512#define PBIU_PBLRx_SIZE(x) (~((x) - 1)) 513 514/* 515 * Messaging Unit 516 */ 517#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ 518#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ 519#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ 520#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */ 521#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */ 522#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ 523#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ 524#define MU_ODR 0x002c /* MU Outbound Doorbell Register */ 525#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ 526#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ 527#define MU_MUCR 0x0050 /* MU Configuration Register */ 528#define MU_QBAR 0x0054 /* MU Queue Base Address Register */ 529#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ 530#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ 531#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ 532#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ 533#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ 534#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ 535#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ 536#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ 537#define MU_IAR 0x0080 /* MU Index Address Register */ 538 539#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ 540#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ 541#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ 542#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ 543#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ 544#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ 545#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ 546 547#endif /* _ARM_XSCALE_I80321REG_H_ */ 548