mvreg.h revision 294436
1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 294436 2016-01-20 14:23:57Z zbb $ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#include <arm/mv/mvwin.h> 38 39#if defined(SOC_MV_DISCOVERY) 40#define IRQ_CAUSE_ERROR 0x0 41#define IRQ_CAUSE 0x4 42#define IRQ_CAUSE_HI 0x8 43#define IRQ_MASK_ERROR 0xC 44#define IRQ_MASK 0x10 45#define IRQ_MASK_HI 0x14 46#define IRQ_CAUSE_SELECT 0x18 47#define FIQ_MASK_ERROR 0x1C 48#define FIQ_MASK 0x20 49#define FIQ_MASK_HI 0x24 50#define FIQ_CAUSE_SELECT 0x28 51#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 52#define ENDPOINT_IRQ_MASK(n) 0x30 53#define ENDPOINT_IRQ_MASK_HI(n) 0x34 54#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 55#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 56#define IRQ_CAUSE 0x0 57#define IRQ_MASK 0x4 58#define FIQ_MASK 0x8 59#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 60#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 61#define IRQ_MASK_HI (-1) /* interrupt controller code */ 62#define FIQ_MASK_HI (-1) 63#define ENDPOINT_IRQ_MASK_HI(n) (-1) 64#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 65#define IRQ_CAUSE_ERROR (-1) 66#define IRQ_MASK_ERROR (-1) 67#elif defined (SOC_MV_ARMADAXP) 68#define IRQ_CAUSE 0x18 69#define IRQ_MASK 0x30 70#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 71#define IRQ_CAUSE 0x0 72#define IRQ_MASK 0x4 73#define FIQ_MASK 0x8 74#define ENDPOINT_IRQ_MASK(n) 0xC 75#define IRQ_CAUSE_HI 0x10 76#define IRQ_MASK_HI 0x14 77#define FIQ_MASK_HI 0x18 78#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 79#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 80#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 81#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 82#endif 83 84#if defined(SOC_MV_FREY) 85#define BRIDGE_IRQ_CAUSE 0x118 86#define IRQ_TIMER0 0x00000002 87#define IRQ_TIMER1 0x00000004 88#define IRQ_TIMER_WD 0x00000008 89 90#define BRIDGE_IRQ_MASK 0x11c 91#define IRQ_TIMER0_MASK 0x00000002 92#define IRQ_TIMER1_MASK 0x00000004 93#define IRQ_TIMER_WD_MASK 0x00000008 94#elif defined(SOC_MV_ARMADAXP) 95#define BRIDGE_IRQ_CAUSE 0x68 96#define IRQ_TIMER0 0x00000001 97#define IRQ_TIMER1 0x00000002 98#define IRQ_TIMER_WD 0x00000004 99#else 100#define BRIDGE_IRQ_CAUSE 0x10 101#define IRQ_CPU_SELF 0x00000001 102#define IRQ_TIMER0 0x00000002 103#define IRQ_TIMER1 0x00000004 104#define IRQ_TIMER_WD 0x00000008 105 106#define BRIDGE_IRQ_MASK 0x14 107#define IRQ_CPU_MASK 0x00000001 108#define IRQ_TIMER0_MASK 0x00000002 109#define IRQ_TIMER1_MASK 0x00000004 110#define IRQ_TIMER_WD_MASK 0x00000008 111#endif 112 113#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 114#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 115#define IRQ_TIMER0_CLR IRQ_TIMER0 116#define IRQ_TIMER1_CLR IRQ_TIMER1 117#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 118#else 119#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 120#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 121#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 122#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 123#endif 124 125/* 126 * System reset 127 */ 128#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 129#define RSTOUTn_MASK 0x60 130#define RSTOUTn_MASK_WD 0x400 131#define SYSTEM_SOFT_RESET 0x64 132#define WD_RSTOUTn_MASK 0x4 133#define WD_GLOBAL_MASK 0x00000100 134#define WD_CPU0_MASK 0x00000001 135#define SOFT_RST_OUT_EN 0x00000001 136#define SYS_SOFT_RST 0x00000001 137#else 138#define RSTOUTn_MASK 0x8 139#define WD_RST_OUT_EN 0x00000002 140#define SOFT_RST_OUT_EN 0x00000004 141#define SYSTEM_SOFT_RESET 0xc 142#define SYS_SOFT_RST 0x00000001 143#endif 144 145/* 146 * Power Control 147 */ 148#if defined(SOC_MV_KIRKWOOD) 149#define CPU_PM_CTRL 0x18 150#else 151#define CPU_PM_CTRL 0x1C 152#endif 153#define CPU_PM_CTRL_NONE 0 154#define CPU_PM_CTRL_ALL ~0x0 155 156#if defined(SOC_MV_KIRKWOOD) 157#define CPU_PM_CTRL_GE0 (1 << 0) 158#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 159#define CPU_PM_CTRL_PEX0 (1 << 2) 160#define CPU_PM_CTRL_USB0 (1 << 3) 161#define CPU_PM_CTRL_SDIO (1 << 4) 162#define CPU_PM_CTRL_TSU (1 << 5) 163#define CPU_PM_CTRL_DUNIT (1 << 6) 164#define CPU_PM_CTRL_RUNIT (1 << 7) 165#define CPU_PM_CTRL_XOR0 (1 << 8) 166#define CPU_PM_CTRL_AUDIO (1 << 9) 167#define CPU_PM_CTRL_SATA0 (1 << 14) 168#define CPU_PM_CTRL_SATA1 (1 << 15) 169#define CPU_PM_CTRL_XOR1 (1 << 16) 170#define CPU_PM_CTRL_CRYPTO (1 << 17) 171#define CPU_PM_CTRL_GE1 (1 << 19) 172#define CPU_PM_CTRL_TDM (1 << 20) 173#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 174#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 175#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 176#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 177 (1 - (u))) 178#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 179#elif defined(SOC_MV_DISCOVERY) 180#define CPU_PM_CTRL_GE0 (1 << 1) 181#define CPU_PM_CTRL_GE1 (1 << 2) 182#define CPU_PM_CTRL_PEX00 (1 << 5) 183#define CPU_PM_CTRL_PEX01 (1 << 6) 184#define CPU_PM_CTRL_PEX02 (1 << 7) 185#define CPU_PM_CTRL_PEX03 (1 << 8) 186#define CPU_PM_CTRL_PEX10 (1 << 9) 187#define CPU_PM_CTRL_PEX11 (1 << 10) 188#define CPU_PM_CTRL_PEX12 (1 << 11) 189#define CPU_PM_CTRL_PEX13 (1 << 12) 190#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 191#define CPU_PM_CTRL_SATA0 (1 << 14) 192#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 193#define CPU_PM_CTRL_SATA1 (1 << 16) 194#define CPU_PM_CTRL_USB0 (1 << 17) 195#define CPU_PM_CTRL_USB1 (1 << 18) 196#define CPU_PM_CTRL_USB2 (1 << 19) 197#define CPU_PM_CTRL_IDMA (1 << 20) 198#define CPU_PM_CTRL_XOR (1 << 21) 199#define CPU_PM_CTRL_CRYPTO (1 << 22) 200#define CPU_PM_CTRL_DEVICE (1 << 23) 201#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 202#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 203#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 204 (1 - (u))) 205#else 206#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 207#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 208#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 209#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 210#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 211#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 212#endif 213 214/* 215 * Timers 216 */ 217#define CPU_TIMERS_BASE 0x300 218#define CPU_TIMER_CONTROL 0x0 219#define CPU_TIMER0_EN 0x00000001 220#define CPU_TIMER0_AUTO 0x00000002 221#define CPU_TIMER1_EN 0x00000004 222#define CPU_TIMER1_AUTO 0x00000008 223#define CPU_TIMER2_EN 0x00000010 224#define CPU_TIMER2_AUTO 0x00000020 225#define CPU_TIMER_WD_EN 0x00000100 226#define CPU_TIMER_WD_AUTO 0x00000200 227/* 25MHz mode is Armada XP - specific */ 228#define CPU_TIMER_WD_25MHZ_EN 0x00000400 229#define CPU_TIMER0_25MHZ_EN 0x00000800 230#define CPU_TIMER1_25MHZ_EN 0x00001000 231#define CPU_TIMER0_REL 0x10 232#define CPU_TIMER0 0x14 233 234/* 235 * SATA 236 */ 237#define SATA_CHAN_NUM 2 238 239#define EDMA_REGISTERS_OFFSET 0x2000 240#define EDMA_REGISTERS_SIZE 0x2000 241#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 242 ((ch) * EDMA_REGISTERS_SIZE)) 243 244/* SATAHC registers */ 245#define SATA_CR 0x000 /* Configuration Reg. */ 246#define SATA_CR_NODMABS (1 << 8) 247#define SATA_CR_NOEDMABS (1 << 9) 248#define SATA_CR_NOPRDPBS (1 << 10) 249#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 250 251/* Interrupt Coalescing Threshold Reg. */ 252#define SATA_ICTR 0x00C 253#define SATA_ICTR_MAX ((1 << 8) - 1) 254 255/* Interrupt Time Threshold Reg. */ 256#define SATA_ITTR 0x010 257#define SATA_ITTR_MAX ((1 << 24) - 1) 258 259#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 260#define SATA_ICR_DMADONE(ch) (1 << (ch)) 261#define SATA_ICR_COAL (1 << 4) 262#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 263 264#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 265#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 266#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 267#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 268#define SATA_MICR_COAL (1 << 8) 269 270#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 271 272/* Shadow registers */ 273#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 274#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 275 276/* SATA registers */ 277#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 278#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 279#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 280#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 281 282/* EDMA registers */ 283#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 284#define SATA_EDMA_CFG_QL128 (1 << 19) 285#define SATA_EDMA_CFG_HQCACHE (1 << 22) 286 287#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 288 289#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 290#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 291#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 292#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 293#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 294#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 295#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 296 297#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 298#define SATA_EDMA_CMD_ENABLE (1 << 0) 299#define SATA_EDMA_CMD_DISABLE (1 << 1) 300#define SATA_EDMA_CMD_RESET (1 << 2) 301 302#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 303#define SATA_EDMA_STATUS_IDLE (1 << 7) 304 305/* Offset to extract input slot from REQIPR register */ 306#define SATA_EDMA_REQIS_OFS 5 307 308/* Offset to extract input slot from RESOPR register */ 309#define SATA_EDMA_RESOS_OFS 3 310 311/* 312 * GPIO 313 */ 314#define GPIO_DATA_OUT 0x00 315#define GPIO_DATA_OUT_EN_CTRL 0x04 316#define GPIO_BLINK_EN 0x08 317#define GPIO_DATA_IN_POLAR 0x0c 318#define GPIO_DATA_IN 0x10 319#define GPIO_INT_CAUSE 0x14 320#define GPIO_INT_EDGE_MASK 0x18 321#define GPIO_INT_LEV_MASK 0x1c 322 323#define GPIO_HI_DATA_OUT 0x40 324#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 325#define GPIO_HI_BLINK_EN 0x48 326#define GPIO_HI_DATA_IN_POLAR 0x4c 327#define GPIO_HI_DATA_IN 0x50 328#define GPIO_HI_INT_CAUSE 0x54 329#define GPIO_HI_INT_EDGE_MASK 0x58 330#define GPIO_HI_INT_LEV_MASK 0x5c 331 332#define GPIO(n) (1 << (n)) 333#define MV_GPIO_MAX_NPINS 64 334 335#define MV_GPIO_IN_NONE 0x0 336#define MV_GPIO_IN_POL_LOW (1 << 16) 337#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 338#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 339#define MV_GPIO_OUT_NONE 0x0 340#define MV_GPIO_OUT_BLINK 0x1 341#define MV_GPIO_OUT_OPEN_DRAIN 0x2 342#define MV_GPIO_OUT_OPEN_SRC 0x4 343 344#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 345#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 346#define IRQ2GPIO(irq) ((irq) - NIRQ) 347 348#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 349#define SAMPLE_AT_RESET 0x10 350#elif defined(SOC_MV_KIRKWOOD) 351#define SAMPLE_AT_RESET 0x30 352#elif defined(SOC_MV_FREY) 353#define SAMPLE_AT_RESET 0x100 354#elif defined(SOC_MV_ARMADA38X) 355#define SAMPLE_AT_RESET 0x400 356#endif 357#if defined(SOC_MV_DISCOVERY) 358#define SAMPLE_AT_RESET_LO 0x30 359#define SAMPLE_AT_RESET_HI 0x34 360#elif defined(SOC_MV_DOVE) 361#define SAMPLE_AT_RESET_LO 0x14 362#define SAMPLE_AT_RESET_HI 0x18 363#elif defined(SOC_MV_ARMADAXP) 364#define SAMPLE_AT_RESET_LO 0x30 365#define SAMPLE_AT_RESET_HI 0x34 366#endif 367 368/* 369 * Clocks 370 */ 371#if defined(SOC_MV_ORION) 372#define TCLK_MASK 0x00000300 373#define TCLK_SHIFT 0x08 374#elif defined(SOC_MV_DISCOVERY) 375#define TCLK_MASK 0x00000180 376#define TCLK_SHIFT 0x07 377#elif defined(SOC_MV_LOKIPLUS) 378#define TCLK_MASK 0x0000F000 379#define TCLK_SHIFT 0x0C 380#elif defined(SOC_MV_ARMADA38X) 381#define TCLK_MASK 0x00008000 382#define TCLK_SHIFT 15 383#endif 384 385#define TCLK_100MHZ 100000000 386#define TCLK_125MHZ 125000000 387#define TCLK_133MHZ 133333333 388#define TCLK_150MHZ 150000000 389#define TCLK_166MHZ 166666667 390#define TCLK_200MHZ 200000000 391#define TCLK_250MHZ 250000000 392#define TCLK_300MHZ 300000000 393#define TCLK_667MHZ 667000000 394 395/* 396 * CPU Cache Configuration 397 */ 398 399#define CPU_CONFIG 0x00000000 400#define CPU_CONFIG_IC_PREF 0x00010000 401#define CPU_CONFIG_DC_PREF 0x00020000 402#define CPU_CONTROL 0x00000004 403#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 404#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 405#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 406#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 407 408/* 409 * PCI Express port control (CPU Control registers) 410 */ 411#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 412 413/* 414 * Vendor ID 415 */ 416#define PCI_VENDORID_MRVL 0x11AB 417#define PCI_VENDORID_MRVL2 0x1B4B 418 419/* 420 * Chip ID 421 */ 422#define MV_DEV_88F5181 0x5181 423#define MV_DEV_88F5182 0x5182 424#define MV_DEV_88F5281 0x5281 425#define MV_DEV_88F6281 0x6281 426#define MV_DEV_88F6282 0x6282 427#define MV_DEV_88F6781 0x6781 428#define MV_DEV_88F6828 0x6828 429#define MV_DEV_88F6820 0x6820 430#define MV_DEV_88F6810 0x6810 431#define MV_DEV_MV78100_Z0 0x6381 432#define MV_DEV_MV78100 0x7810 433#define MV_DEV_MV78130 0x7813 434#define MV_DEV_MV78160 0x7816 435#define MV_DEV_MV78230 0x7823 436#define MV_DEV_MV78260 0x7826 437#define MV_DEV_MV78460 0x7846 438#define MV_DEV_88RC8180 0x8180 439#define MV_DEV_88RC9480 0x9480 440#define MV_DEV_88RC9580 0x9580 441 442#define MV_DEV_FAMILY_MASK 0xff00 443#define MV_DEV_DISCOVERY 0x7800 444#define MV_DEV_ARMADA38X 0x6800 445 446/* 447 * Doorbell register control 448 */ 449#define MV_DRBL_PCIE_TO_CPU 0 450#define MV_DRBL_CPU_TO_PCIE 1 451 452#if defined(SOC_MV_FREY) 453#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 454#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 455#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 456#else 457#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 458#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 459#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 460#endif 461 462/* 463 * SCU 464 */ 465#if defined(SOC_MV_ARMADA38X) 466#define MV_SCU_BASE (MV_BASE + 0xc000) 467#define MV_SCU_REGS_LEN 0x100 468#define MV_SCU_REG_CTRL 0 469#define MV_SCU_ENABLE 1 470#endif 471 472#endif /* _MVREG_H_ */ 473