1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#include <arm/mv/mvwin.h> 38 39#if defined(SOC_MV_DISCOVERY) 40#define IRQ_CAUSE_ERROR 0x0 41#define IRQ_CAUSE 0x4 42#define IRQ_CAUSE_HI 0x8 43#define IRQ_MASK_ERROR 0xC 44#define IRQ_MASK 0x10 45#define IRQ_MASK_HI 0x14 46#define IRQ_CAUSE_SELECT 0x18 47#define FIQ_MASK_ERROR 0x1C 48#define FIQ_MASK 0x20 49#define FIQ_MASK_HI 0x24 50#define FIQ_CAUSE_SELECT 0x28 51#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 52#define ENDPOINT_IRQ_MASK(n) 0x30 53#define ENDPOINT_IRQ_MASK_HI(n) 0x34 54#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 55#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 56#define IRQ_CAUSE 0x0 57#define IRQ_MASK 0x4 58#define FIQ_MASK 0x8 59#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 60#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 61#define IRQ_MASK_HI (-1) /* interrupt controller code */ 62#define FIQ_MASK_HI (-1) 63#define ENDPOINT_IRQ_MASK_HI(n) (-1) 64#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 65#define IRQ_CAUSE_ERROR (-1) 66#define IRQ_MASK_ERROR (-1) 67#elif defined (SOC_MV_ARMADAXP) 68#define IRQ_CAUSE 0x18 69#define IRQ_MASK 0x30 70#elif defined (SOC_MV_ARMADA38X) 71#define MSI_IRQ 0x3ff 72#define ERR_IRQ 0x3ff 73#else 74#define IRQ_CAUSE 0x0 75#define IRQ_MASK 0x4 76#define FIQ_MASK 0x8 77#define ENDPOINT_IRQ_MASK(n) 0xC 78#define IRQ_CAUSE_HI 0x10 79#define IRQ_MASK_HI 0x14 80#define FIQ_MASK_HI 0x18 81#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 82#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 83#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 84#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 85#endif 86 87#if defined(SOC_MV_FREY) 88#define BRIDGE_IRQ_CAUSE 0x118 89#define IRQ_TIMER0 0x00000002 90#define IRQ_TIMER1 0x00000004 91#define IRQ_TIMER_WD 0x00000008 92 93#define BRIDGE_IRQ_MASK 0x11c 94#define IRQ_TIMER0_MASK 0x00000002 95#define IRQ_TIMER1_MASK 0x00000004 96#define IRQ_TIMER_WD_MASK 0x00000008 97#elif defined(SOC_MV_ARMADAXP) 98#define BRIDGE_IRQ_CAUSE 0x68 99#define IRQ_TIMER0 0x00000001 100#define IRQ_TIMER1 0x00000002 101#define IRQ_TIMER_WD 0x00000004 102#else 103#define BRIDGE_IRQ_CAUSE 0x10 104#define IRQ_CPU_SELF 0x00000001 105#define IRQ_TIMER0 0x00000002 106#define IRQ_TIMER1 0x00000004 107#define IRQ_TIMER_WD 0x00000008 108 109#define BRIDGE_IRQ_MASK 0x14 110#define IRQ_CPU_MASK 0x00000001 111#define IRQ_TIMER0_MASK 0x00000002 112#define IRQ_TIMER1_MASK 0x00000004 113#define IRQ_TIMER_WD_MASK 0x00000008 114#endif 115 116#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 117#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 118#define IRQ_TIMER0_CLR IRQ_TIMER0 119#define IRQ_TIMER1_CLR IRQ_TIMER1 120#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 121#else 122#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 123#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 124#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 125#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 126#endif 127 128/* 129 * System reset 130 */ 131#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 132#define RSTOUTn_MASK 0x60 133#define RSTOUTn_MASK_WD 0x400 134#define SYSTEM_SOFT_RESET 0x64 135#define WD_RSTOUTn_MASK 0x4 136#define WD_GLOBAL_MASK 0x00000100 137#define WD_CPU0_MASK 0x00000001 138#define SOFT_RST_OUT_EN 0x00000001 139#define SYS_SOFT_RST 0x00000001 140#else 141#define RSTOUTn_MASK 0x8 142#define WD_RST_OUT_EN 0x00000002 143#define SOFT_RST_OUT_EN 0x00000004 144#define SYSTEM_SOFT_RESET 0xc 145#define SYS_SOFT_RST 0x00000001 146#endif 147 148/* 149 * Power Control 150 */ 151#if defined(SOC_MV_KIRKWOOD) 152#define CPU_PM_CTRL 0x18 153#else 154#define CPU_PM_CTRL 0x1C 155#endif 156#define CPU_PM_CTRL_NONE 0 157#define CPU_PM_CTRL_ALL ~0x0 158 159#if defined(SOC_MV_KIRKWOOD) 160#define CPU_PM_CTRL_GE0 (1 << 0) 161#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 162#define CPU_PM_CTRL_PEX0 (1 << 2) 163#define CPU_PM_CTRL_USB0 (1 << 3) 164#define CPU_PM_CTRL_SDIO (1 << 4) 165#define CPU_PM_CTRL_TSU (1 << 5) 166#define CPU_PM_CTRL_DUNIT (1 << 6) 167#define CPU_PM_CTRL_RUNIT (1 << 7) 168#define CPU_PM_CTRL_XOR0 (1 << 8) 169#define CPU_PM_CTRL_AUDIO (1 << 9) 170#define CPU_PM_CTRL_SATA0 (1 << 14) 171#define CPU_PM_CTRL_SATA1 (1 << 15) 172#define CPU_PM_CTRL_XOR1 (1 << 16) 173#define CPU_PM_CTRL_CRYPTO (1 << 17) 174#define CPU_PM_CTRL_GE1 (1 << 19) 175#define CPU_PM_CTRL_TDM (1 << 20) 176#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 177#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 178#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 179#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 180 (1 - (u))) 181#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 182#elif defined(SOC_MV_DISCOVERY) 183#define CPU_PM_CTRL_GE0 (1 << 1) 184#define CPU_PM_CTRL_GE1 (1 << 2) 185#define CPU_PM_CTRL_PEX00 (1 << 5) 186#define CPU_PM_CTRL_PEX01 (1 << 6) 187#define CPU_PM_CTRL_PEX02 (1 << 7) 188#define CPU_PM_CTRL_PEX03 (1 << 8) 189#define CPU_PM_CTRL_PEX10 (1 << 9) 190#define CPU_PM_CTRL_PEX11 (1 << 10) 191#define CPU_PM_CTRL_PEX12 (1 << 11) 192#define CPU_PM_CTRL_PEX13 (1 << 12) 193#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 194#define CPU_PM_CTRL_SATA0 (1 << 14) 195#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 196#define CPU_PM_CTRL_SATA1 (1 << 16) 197#define CPU_PM_CTRL_USB0 (1 << 17) 198#define CPU_PM_CTRL_USB1 (1 << 18) 199#define CPU_PM_CTRL_USB2 (1 << 19) 200#define CPU_PM_CTRL_IDMA (1 << 20) 201#define CPU_PM_CTRL_XOR (1 << 21) 202#define CPU_PM_CTRL_CRYPTO (1 << 22) 203#define CPU_PM_CTRL_DEVICE (1 << 23) 204#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 205#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 206#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 207 (1 - (u))) 208#else 209#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 210#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 211#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 212#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 213#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 214#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 215#endif 216 217/* 218 * Timers 219 */ 220#define CPU_TIMERS_BASE 0x300 221#define CPU_TIMER_CONTROL 0x0 222#define CPU_TIMER0_EN 0x00000001 223#define CPU_TIMER0_AUTO 0x00000002 224#define CPU_TIMER1_EN 0x00000004 225#define CPU_TIMER1_AUTO 0x00000008 226#define CPU_TIMER2_EN 0x00000010 227#define CPU_TIMER2_AUTO 0x00000020 228#define CPU_TIMER_WD_EN 0x00000100 229#define CPU_TIMER_WD_AUTO 0x00000200 230/* 25MHz mode is Armada XP - specific */ 231#define CPU_TIMER_WD_25MHZ_EN 0x00000400 232#define CPU_TIMER0_25MHZ_EN 0x00000800 233#define CPU_TIMER1_25MHZ_EN 0x00001000 234#define CPU_TIMER0_REL 0x10 235#define CPU_TIMER0 0x14 236 237/* 238 * SATA 239 */ 240#define SATA_CHAN_NUM 2 241 242#define EDMA_REGISTERS_OFFSET 0x2000 243#define EDMA_REGISTERS_SIZE 0x2000 244#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 245 ((ch) * EDMA_REGISTERS_SIZE)) 246 247/* SATAHC registers */ 248#define SATA_CR 0x000 /* Configuration Reg. */ 249#define SATA_CR_NODMABS (1 << 8) 250#define SATA_CR_NOEDMABS (1 << 9) 251#define SATA_CR_NOPRDPBS (1 << 10) 252#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 253 254/* Interrupt Coalescing Threshold Reg. */ 255#define SATA_ICTR 0x00C 256#define SATA_ICTR_MAX ((1 << 8) - 1) 257 258/* Interrupt Time Threshold Reg. */ 259#define SATA_ITTR 0x010 260#define SATA_ITTR_MAX ((1 << 24) - 1) 261 262#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 263#define SATA_ICR_DMADONE(ch) (1 << (ch)) 264#define SATA_ICR_COAL (1 << 4) 265#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 266 267#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 268#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 269#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 270#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 271#define SATA_MICR_COAL (1 << 8) 272 273#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 274 275/* Shadow registers */ 276#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 277#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 278 279/* SATA registers */ 280#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 281#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 282#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 283#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 284 285/* EDMA registers */ 286#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 287#define SATA_EDMA_CFG_QL128 (1 << 19) 288#define SATA_EDMA_CFG_HQCACHE (1 << 22) 289 290#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 291 292#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 293#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 294#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 295#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 296#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 297#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 298#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 299 300#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 301#define SATA_EDMA_CMD_ENABLE (1 << 0) 302#define SATA_EDMA_CMD_DISABLE (1 << 1) 303#define SATA_EDMA_CMD_RESET (1 << 2) 304 305#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 306#define SATA_EDMA_STATUS_IDLE (1 << 7) 307 308/* Offset to extract input slot from REQIPR register */ 309#define SATA_EDMA_REQIS_OFS 5 310 311/* Offset to extract input slot from RESOPR register */ 312#define SATA_EDMA_RESOS_OFS 3 313 314/* 315 * GPIO 316 */ 317#define GPIO_DATA_OUT 0x00 318#define GPIO_DATA_OUT_EN_CTRL 0x04 319#define GPIO_BLINK_EN 0x08 320#define GPIO_DATA_IN_POLAR 0x0c 321#define GPIO_DATA_IN 0x10 322#define GPIO_INT_CAUSE 0x14 323#define GPIO_INT_EDGE_MASK 0x18 324#define GPIO_INT_LEV_MASK 0x1c 325 326#define GPIO_HI_DATA_OUT 0x40 327#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 328#define GPIO_HI_BLINK_EN 0x48 329#define GPIO_HI_DATA_IN_POLAR 0x4c 330#define GPIO_HI_DATA_IN 0x50 331#define GPIO_HI_INT_CAUSE 0x54 332#define GPIO_HI_INT_EDGE_MASK 0x58 333#define GPIO_HI_INT_LEV_MASK 0x5c 334 335#define GPIO(n) (1 << (n)) 336#define MV_GPIO_MAX_NPINS 64 337 338#define MV_GPIO_IN_NONE 0x0 339#define MV_GPIO_IN_POL_LOW (1 << 16) 340#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 341#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 342#define MV_GPIO_OUT_NONE 0x0 343#define MV_GPIO_OUT_BLINK 0x1 344#define MV_GPIO_OUT_OPEN_DRAIN 0x2 345#define MV_GPIO_OUT_OPEN_SRC 0x4 346 347#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 348#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 349#define IRQ2GPIO(irq) ((irq) - NIRQ) 350 351#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 352#define SAMPLE_AT_RESET 0x10 353#elif defined(SOC_MV_KIRKWOOD) 354#define SAMPLE_AT_RESET 0x30 355#elif defined(SOC_MV_FREY) 356#define SAMPLE_AT_RESET 0x100 357#elif defined(SOC_MV_ARMADA38X) 358#define SAMPLE_AT_RESET 0x400 359#endif 360#if defined(SOC_MV_DISCOVERY) 361#define SAMPLE_AT_RESET_LO 0x30 362#define SAMPLE_AT_RESET_HI 0x34 363#elif defined(SOC_MV_DOVE) 364#define SAMPLE_AT_RESET_LO 0x14 365#define SAMPLE_AT_RESET_HI 0x18 366#elif defined(SOC_MV_ARMADAXP) 367#define SAMPLE_AT_RESET_LO 0x30 368#define SAMPLE_AT_RESET_HI 0x34 369#endif 370 371/* 372 * Clocks 373 */ 374#if defined(SOC_MV_ORION) 375#define TCLK_MASK 0x00000300 376#define TCLK_SHIFT 0x08 377#elif defined(SOC_MV_DISCOVERY) 378#define TCLK_MASK 0x00000180 379#define TCLK_SHIFT 0x07 380#elif defined(SOC_MV_LOKIPLUS) 381#define TCLK_MASK 0x0000F000 382#define TCLK_SHIFT 0x0C 383#elif defined(SOC_MV_ARMADA38X) 384#define TCLK_MASK 0x00008000 385#define TCLK_SHIFT 15 386#endif 387 388#define TCLK_100MHZ 100000000 389#define TCLK_125MHZ 125000000 390#define TCLK_133MHZ 133333333 391#define TCLK_150MHZ 150000000 392#define TCLK_166MHZ 166666667 393#define TCLK_200MHZ 200000000 394#define TCLK_250MHZ 250000000 395#define TCLK_300MHZ 300000000 396#define TCLK_667MHZ 667000000 397 398/* 399 * CPU Cache Configuration 400 */ 401 402#define CPU_CONFIG 0x00000000 403#define CPU_CONFIG_IC_PREF 0x00010000 404#define CPU_CONFIG_DC_PREF 0x00020000 405#define CPU_CONTROL 0x00000004 406#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 407#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 408#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 409#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 410 411/* 412 * PCI Express port control (CPU Control registers) 413 */ 414#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 415 416/* 417 * Vendor ID 418 */ 419#define PCI_VENDORID_MRVL 0x11AB 420#define PCI_VENDORID_MRVL2 0x1B4B 421 422/* 423 * Chip ID 424 */ 425#define MV_DEV_88F5181 0x5181 426#define MV_DEV_88F5182 0x5182 427#define MV_DEV_88F5281 0x5281 428#define MV_DEV_88F6281 0x6281 429#define MV_DEV_88F6282 0x6282 430#define MV_DEV_88F6781 0x6781 431#define MV_DEV_88F6828 0x6828 432#define MV_DEV_88F6820 0x6820 433#define MV_DEV_88F6810 0x6810 434#define MV_DEV_MV78100_Z0 0x6381 435#define MV_DEV_MV78100 0x7810 436#define MV_DEV_MV78130 0x7813 437#define MV_DEV_MV78160 0x7816 438#define MV_DEV_MV78230 0x7823 439#define MV_DEV_MV78260 0x7826 440#define MV_DEV_MV78460 0x7846 441#define MV_DEV_88RC8180 0x8180 442#define MV_DEV_88RC9480 0x9480 443#define MV_DEV_88RC9580 0x9580 444 445#define MV_DEV_FAMILY_MASK 0xff00 446#define MV_DEV_DISCOVERY 0x7800 447#define MV_DEV_ARMADA38X 0x6800 448 449/* 450 * Doorbell register control 451 */ 452#define MV_DRBL_PCIE_TO_CPU 0 453#define MV_DRBL_CPU_TO_PCIE 1 454 455#if defined(SOC_MV_FREY) 456#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 457#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 458#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 459#else 460#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 461#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 462#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 463#endif 464 465/* 466 * SCU 467 */ 468#if defined(SOC_MV_ARMADA38X) 469#define MV_SCU_BASE (MV_BASE + 0xc000) 470#define MV_SCU_REGS_LEN 0x100 471#define MV_SCU_REG_CTRL 0x00 472#define MV_SCU_REG_CONFIG 0x04 473#define MV_SCU_ENABLE 1 474#define SCU_CFG_REG_NCPU_MASK 0x3 475#endif 476 477/* 478 * PMSU 479 */ 480#if defined(SOC_MV_ARMADA38X) 481#define MV_PMSU_BASE (MV_BASE + 0x22000) 482#define MV_PMSU_REGS_LEN 0x1000 483#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124) 484#endif 485 486/* 487 * CPU RESET 488 */ 489#if defined(SOC_MV_ARMADA38X) 490#define MV_CPU_RESET_BASE (MV_BASE + 0x20800) 491#define MV_CPU_RESET_REGS_LEN 0x8 492#define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8) 493#define CPU_RESET_ASSERT 0x1 494#endif 495 496#endif /* _MVREG_H_ */ 497