mvreg.h revision 239277
1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 239277 2012-08-15 05:15:49Z gonzo $ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#if defined(SOC_MV_DISCOVERY) 38#define IRQ_CAUSE_ERROR 0x0 39#define IRQ_CAUSE 0x4 40#define IRQ_CAUSE_HI 0x8 41#define IRQ_MASK_ERROR 0xC 42#define IRQ_MASK 0x10 43#define IRQ_MASK_HI 0x14 44#define IRQ_CAUSE_SELECT 0x18 45#define FIQ_MASK_ERROR 0x1C 46#define FIQ_MASK 0x20 47#define FIQ_MASK_HI 0x24 48#define FIQ_CAUSE_SELECT 0x28 49#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 50#define ENDPOINT_IRQ_MASK(n) 0x30 51#define ENDPOINT_IRQ_MASK_HI(n) 0x34 52#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 53#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 54#define IRQ_CAUSE 0x0 55#define IRQ_MASK 0x4 56#define FIQ_MASK 0x8 57#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 58#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 59#define IRQ_MASK_HI (-1) /* interrupt controller code */ 60#define FIQ_MASK_HI (-1) 61#define ENDPOINT_IRQ_MASK_HI(n) (-1) 62#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 63#define IRQ_CAUSE_ERROR (-1) 64#define IRQ_MASK_ERROR (-1) 65#elif defined (SOC_MV_ARMADAXP) 66#define IRQ_CAUSE 0x18 67#define IRQ_MASK 0x30 68#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 69#define IRQ_CAUSE 0x0 70#define IRQ_MASK 0x4 71#define FIQ_MASK 0x8 72#define ENDPOINT_IRQ_MASK(n) 0xC 73#define IRQ_CAUSE_HI 0x10 74#define IRQ_MASK_HI 0x14 75#define FIQ_MASK_HI 0x18 76#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 77#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 78#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 79#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 80#endif 81 82#if defined(SOC_MV_FREY) 83#define BRIDGE_IRQ_CAUSE 0x118 84#define IRQ_TIMER0 0x00000002 85#define IRQ_TIMER1 0x00000004 86#define IRQ_TIMER_WD 0x00000008 87 88#define BRIDGE_IRQ_MASK 0x11c 89#define IRQ_TIMER0_MASK 0x00000002 90#define IRQ_TIMER1_MASK 0x00000004 91#define IRQ_TIMER_WD_MASK 0x00000008 92#elif defined(SOC_MV_ARMADAXP) 93#define BRIDGE_IRQ_CAUSE 0x68 94#define IRQ_TIMER0 0x00000001 95#define IRQ_TIMER1 0x00000002 96#define IRQ_TIMER_WD 0x00000004 97#else 98#define BRIDGE_IRQ_CAUSE 0x10 99#define IRQ_CPU_SELF 0x00000001 100#define IRQ_TIMER0 0x00000002 101#define IRQ_TIMER1 0x00000004 102#define IRQ_TIMER_WD 0x00000008 103 104#define BRIDGE_IRQ_MASK 0x14 105#define IRQ_CPU_MASK 0x00000001 106#define IRQ_TIMER0_MASK 0x00000002 107#define IRQ_TIMER1_MASK 0x00000004 108#define IRQ_TIMER_WD_MASK 0x00000008 109#endif 110 111#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 112#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 113#define IRQ_TIMER0_CLR IRQ_TIMER0 114#define IRQ_TIMER1_CLR IRQ_TIMER1 115#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 116#else 117#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 118#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121#endif 122 123/* 124 * System reset 125 */ 126#define RSTOUTn_MASK 0x8 127#define WD_RST_OUT_EN 0x00000002 128#define SOFT_RST_OUT_EN 0x00000004 129#define SYSTEM_SOFT_RESET 0xc 130#define SYS_SOFT_RST 0x00000001 131 132/* 133 * Power Control 134 */ 135#define CPU_PM_CTRL 0x1C 136#define CPU_PM_CTRL_NONE 0 137#define CPU_PM_CTRL_ALL ~0x0 138 139#if defined(SOC_MV_KIRKWOOD) 140#define CPU_PM_CTRL_GE0 (1 << 0) 141#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 142#define CPU_PM_CTRL_PEX0 (1 << 2) 143#define CPU_PM_CTRL_USB0 (1 << 3) 144#define CPU_PM_CTRL_SDIO (1 << 4) 145#define CPU_PM_CTRL_TSU (1 << 5) 146#define CPU_PM_CTRL_DUNIT (1 << 6) 147#define CPU_PM_CTRL_RUNIT (1 << 7) 148#define CPU_PM_CTRL_XOR0 (1 << 8) 149#define CPU_PM_CTRL_AUDIO (1 << 9) 150#define CPU_PM_CTRL_SATA0 (1 << 14) 151#define CPU_PM_CTRL_SATA1 (1 << 15) 152#define CPU_PM_CTRL_XOR1 (1 << 16) 153#define CPU_PM_CTRL_CRYPTO (1 << 17) 154#define CPU_PM_CTRL_GE1 (1 << 19) 155#define CPU_PM_CTRL_TDM (1 << 20) 156#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 157#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 158#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 159#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 160 (1 - (u))) 161#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 162#elif defined(SOC_MV_DISCOVERY) 163#define CPU_PM_CTRL_GE0 (1 << 1) 164#define CPU_PM_CTRL_GE1 (1 << 2) 165#define CPU_PM_CTRL_PEX00 (1 << 5) 166#define CPU_PM_CTRL_PEX01 (1 << 6) 167#define CPU_PM_CTRL_PEX02 (1 << 7) 168#define CPU_PM_CTRL_PEX03 (1 << 8) 169#define CPU_PM_CTRL_PEX10 (1 << 9) 170#define CPU_PM_CTRL_PEX11 (1 << 10) 171#define CPU_PM_CTRL_PEX12 (1 << 11) 172#define CPU_PM_CTRL_PEX13 (1 << 12) 173#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 174#define CPU_PM_CTRL_SATA0 (1 << 14) 175#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 176#define CPU_PM_CTRL_SATA1 (1 << 16) 177#define CPU_PM_CTRL_USB0 (1 << 17) 178#define CPU_PM_CTRL_USB1 (1 << 18) 179#define CPU_PM_CTRL_USB2 (1 << 19) 180#define CPU_PM_CTRL_IDMA (1 << 20) 181#define CPU_PM_CTRL_XOR (1 << 21) 182#define CPU_PM_CTRL_CRYPTO (1 << 22) 183#define CPU_PM_CTRL_DEVICE (1 << 23) 184#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 185#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 186#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 187 (1 - (u))) 188#else 189#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 190#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 191#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 192#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 193#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 194#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 195#endif 196 197/* 198 * Timers 199 */ 200#define CPU_TIMERS_BASE 0x300 201#define CPU_TIMER_CONTROL 0x0 202#define CPU_TIMER0_EN 0x00000001 203#define CPU_TIMER0_AUTO 0x00000002 204#define CPU_TIMER1_EN 0x00000004 205#define CPU_TIMER1_AUTO 0x00000008 206#define CPU_TIMER_WD_EN 0x00000010 207#define CPU_TIMER_WD_AUTO 0x00000020 208#define CPU_TIMER0_REL 0x10 209#define CPU_TIMER0 0x14 210 211/* 212 * SATA 213 */ 214#define SATA_CHAN_NUM 2 215 216#define EDMA_REGISTERS_OFFSET 0x2000 217#define EDMA_REGISTERS_SIZE 0x2000 218#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 219 ((ch) * EDMA_REGISTERS_SIZE)) 220 221/* SATAHC registers */ 222#define SATA_CR 0x000 /* Configuration Reg. */ 223#define SATA_CR_NODMABS (1 << 8) 224#define SATA_CR_NOEDMABS (1 << 9) 225#define SATA_CR_NOPRDPBS (1 << 10) 226#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 227 228/* Interrupt Coalescing Threshold Reg. */ 229#define SATA_ICTR 0x00C 230#define SATA_ICTR_MAX ((1 << 8) - 1) 231 232/* Interrupt Time Threshold Reg. */ 233#define SATA_ITTR 0x010 234#define SATA_ITTR_MAX ((1 << 24) - 1) 235 236#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 237#define SATA_ICR_DMADONE(ch) (1 << (ch)) 238#define SATA_ICR_COAL (1 << 4) 239#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 240 241#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 242#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 243#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 244#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 245#define SATA_MICR_COAL (1 << 8) 246 247#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 248 249/* Shadow registers */ 250#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 251#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 252 253/* SATA registers */ 254#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 255#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 256#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 257#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 258 259/* EDMA registers */ 260#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 261#define SATA_EDMA_CFG_QL128 (1 << 19) 262#define SATA_EDMA_CFG_HQCACHE (1 << 22) 263 264#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 265 266#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 267#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 268#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 269#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 270#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 271#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 272#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 273 274#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 275#define SATA_EDMA_CMD_ENABLE (1 << 0) 276#define SATA_EDMA_CMD_DISABLE (1 << 1) 277#define SATA_EDMA_CMD_RESET (1 << 2) 278 279#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 280#define SATA_EDMA_STATUS_IDLE (1 << 7) 281 282/* Offset to extract input slot from REQIPR register */ 283#define SATA_EDMA_REQIS_OFS 5 284 285/* Offset to extract input slot from RESOPR register */ 286#define SATA_EDMA_RESOS_OFS 3 287 288/* 289 * GPIO 290 */ 291#define GPIO_DATA_OUT 0x00 292#define GPIO_DATA_OUT_EN_CTRL 0x04 293#define GPIO_BLINK_EN 0x08 294#define GPIO_DATA_IN_POLAR 0x0c 295#define GPIO_DATA_IN 0x10 296#define GPIO_INT_CAUSE 0x14 297#define GPIO_INT_EDGE_MASK 0x18 298#define GPIO_INT_LEV_MASK 0x1c 299 300#define GPIO_HI_DATA_OUT 0x40 301#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 302#define GPIO_HI_BLINK_EN 0x48 303#define GPIO_HI_DATA_IN_POLAR 0x4c 304#define GPIO_HI_DATA_IN 0x50 305#define GPIO_HI_INT_CAUSE 0x54 306#define GPIO_HI_INT_EDGE_MASK 0x58 307#define GPIO_HI_INT_LEV_MASK 0x5c 308 309#define GPIO(n) (1 << (n)) 310#define MV_GPIO_MAX_NPINS 64 311 312#define MV_GPIO_IN_NONE 0x0 313#define MV_GPIO_IN_POL_LOW (1 << 16) 314#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 315#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 316#define MV_GPIO_OUT_NONE 0x0 317#define MV_GPIO_OUT_BLINK 0x1 318#define MV_GPIO_OUT_OPEN_DRAIN 0x2 319#define MV_GPIO_OUT_OPEN_SRC 0x4 320 321#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 322#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 323#define IRQ2GPIO(irq) ((irq) - NIRQ) 324 325#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 326#define SAMPLE_AT_RESET 0x10 327#elif defined(SOC_MV_KIRKWOOD) 328#define SAMPLE_AT_RESET 0x30 329#elif defined(SOC_MV_DISCOVERY) 330#define SAMPLE_AT_RESET_LO 0x30 331#define SAMPLE_AT_RESET_HI 0x34 332#elif defined(SOC_MV_DOVE) 333#define SAMPLE_AT_RESET_LO 0x14 334#define SAMPLE_AT_RESET_HI 0x18 335#elif defined(SOC_MV_FREY) 336#define SAMPLE_AT_RESET 0x100 337#endif 338 339/* 340 * Clocks 341 */ 342#if defined(SOC_MV_ORION) 343#define TCLK_MASK 0x00000300 344#define TCLK_SHIFT 0x08 345#elif defined(SOC_MV_DISCOVERY) 346#define TCLK_MASK 0x00000180 347#define TCLK_SHIFT 0x07 348#elif defined(SOC_MV_LOKIPLUS) 349#define TCLK_MASK 0x0000F000 350#define TCLK_SHIFT 0x0C 351#endif 352 353#define TCLK_100MHZ 100000000 354#define TCLK_125MHZ 125000000 355#define TCLK_133MHZ 133333333 356#define TCLK_150MHZ 150000000 357#define TCLK_166MHZ 166666667 358#define TCLK_200MHZ 200000000 359#define TCLK_250MHZ 250000000 360#define TCLK_300MHZ 300000000 361#define TCLK_667MHZ 667000000 362 363/* 364 * CPU Cache Configuration 365 */ 366 367#define CPU_CONFIG 0x00000000 368#define CPU_CONFIG_IC_PREF 0x00010000 369#define CPU_CONFIG_DC_PREF 0x00020000 370#define CPU_CONTROL 0x00000004 371#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 372#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 373#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 374#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 375 376/* 377 * PCI Express port control (CPU Control registers) 378 */ 379#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 380 381/* 382 * Vendor ID 383 */ 384#define PCI_VENDORID_MRVL 0x11AB 385#define PCI_VENDORID_MRVL2 0x1B4B 386 387/* 388 * Chip ID 389 */ 390#define MV_DEV_88F5181 0x5181 391#define MV_DEV_88F5182 0x5182 392#define MV_DEV_88F5281 0x5281 393#define MV_DEV_88F6281 0x6281 394#define MV_DEV_88F6781 0x6781 395#define MV_DEV_88F6282 0x6282 396#define MV_DEV_MV78100_Z0 0x6381 397#define MV_DEV_MV78100 0x7810 398#define MV_DEV_MV78130 0x7813 399#define MV_DEV_MV78160 0x7816 400#define MV_DEV_MV78230 0x7823 401#define MV_DEV_MV78260 0x7826 402#define MV_DEV_MV78460 0x7846 403#define MV_DEV_88RC8180 0x8180 404#define MV_DEV_88RC9480 0x9480 405#define MV_DEV_88RC9580 0x9580 406 407#define MV_DEV_FAMILY_MASK 0xff00 408#define MV_DEV_DISCOVERY 0x7800 409 410/* 411 * Doorbell register control 412 */ 413#define MV_DRBL_PCIE_TO_CPU 0 414#define MV_DRBL_CPU_TO_PCIE 1 415 416#if defined(SOC_MV_FREY) 417#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 418#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 419#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 420#else 421#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 422#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 423#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 424#endif 425#endif /* _MVREG_H_ */ 426