mvreg.h revision 186909
172445Sassar/*- 272445Sassar * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 390926Snectar * All rights reserved. 472445Sassar * 572445Sassar * Developed by Semihalf. 672445Sassar * 772445Sassar * Redistribution and use in source and binary forms, with or without 872445Sassar * modification, are permitted provided that the following conditions 972445Sassar * are met: 1090926Snectar * 1. Redistributions of source code must retain the above copyright 1172445Sassar * notice, this list of conditions and the following disclaimer. 1272445Sassar * 2. Redistributions in binary form must reproduce the above copyright 1372445Sassar * notice, this list of conditions and the following disclaimer in the 1472445Sassar * documentation and/or other materials provided with the distribution. 1572445Sassar * 3. Neither the name of MARVELL nor the names of contributors 1690926Snectar * may be used to endorse or promote products derived from this software 1790926Snectar * without specific prior written permission. 1872445Sassar * 1990926Snectar * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2072445Sassar * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2172445Sassar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2272445Sassar * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 2372445Sassar * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2472445Sassar * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2572445Sassar * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2672445Sassar * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2790926Snectar * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2890926Snectar * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2990926Snectar * SUCH DAMAGE. 3090926Snectar * 3190926Snectar * $FreeBSD: head/sys/arm/mv/mvreg.h 186909 2009-01-08 18:31:43Z raj $ 3290926Snectar */ 3390926Snectar 3490926Snectar#ifndef _MVREG_H_ 3590926Snectar#define _MVREG_H_ 3690926Snectar 3790926Snectar#include <machine/intr.h> 3890926Snectar 3990926Snectar/* 4090926Snectar * Physical addresses of integrated SoC peripherals 4190926Snectar */ 4290926Snectar#define MV_PHYS_BASE 0xF1000000 4390926Snectar#define MV_SIZE 0x100000 4490926Snectar 4590926Snectar/* 4690926Snectar * Decode windows addresses (physical) 4790926Snectar */ 4890926Snectar#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 4990926Snectar#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 5090926Snectar#define MV_PCIE_IO_SIZE (1024 * 1024) 5190926Snectar#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 5290926Snectar#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 5372445Sassar#define MV_PCI_IO_SIZE (1024 * 1024) 54 55#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 56#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 57#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 58#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 59#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 60#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 61 62/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ 63 64/* 512KB NOR FLASH */ 65#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 66#define MV_DEV_BOOT_SIZE (512 * 1024) 67/* CS0: 7-seg LED */ 68#define MV_DEV_CS0_PHYS_BASE 0xFA000000 69#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 70/* CS1: 32MB NOR FLASH */ 71#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 72#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 73/* CS2: 32MB NAND FLASH */ 74#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 75#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ 76 77#define MV_CESA_SRAM_PHYS_BASE 0xFD000000 78#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ 79#define MV_CESA_SRAM_SIZE (1024 * 1024) 80 81/* XXX this is probably not robust against wraparounds... */ 82#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) 83#error Devices memory layout overlaps reset vectors range! 84#endif 85 86/* 87 * Integrated SoC peripherals addresses 88 */ 89#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 90#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 91#define MV_MPP_BASE (MV_BASE + 0x10000) 92#define MV_GPIO_BASE (MV_BASE + 0x10100) 93#define MV_GPIO_SIZE 0x20 94#define MV_RTC_BASE (MV_BASE + 0x10300) 95#define MV_RTC_SIZE 0x08 96#define MV_TWSI_BASE (MV_BASE + 0x11000) 97#define MV_TWSI_SIZE 0x20 98#define MV_UART0_BASE (MV_BASE + 0x12000) 99#define MV_UART1_BASE (MV_BASE + 0x12100) 100#define MV_UART_SIZE 0x20 101#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 102#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 103#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 104#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 105#define MV_IC_SIZE 0x3C 106#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) 107#define MV_TIMERS_SIZE 0x30 108#define MV_PCI_BASE (MV_BASE + 0x30000) 109#define MV_PCI_SIZE 0x2000 110#if defined (SOC_MV_KIRKWOOD) 111#define MV_CESA_BASE (MV_BASE + 0x30000) /* CESA,PCI don't coexist */ 112#elif defined (SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 113#define MV_CESA_BASE (MV_BASE + 0x90000) 114#endif 115#define MV_CESA_SIZE 0x10000 116#define MV_PCIE_BASE (MV_BASE + 0x40000) 117#define MV_PCIE_SIZE 0x2000 118 119#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 120#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 121#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 122#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 123#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 124#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 125#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 126#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 127 128#define MV_USB0_BASE (MV_BASE + 0x50000) 129#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) 130#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) 131#define MV_USB_SIZE 0x1000 132#define MV_USB_HOST_OFST 0x0100 /* EHCI HC regs start at this offset within USB range */ 133#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) 134#define MV_IDMA_BASE (MV_BASE + 0x60000) 135#define MV_IDMA_SIZE 0x1000 136#define MV_XOR_BASE (MV_BASE + 0x60000) 137#define MV_XOR_SIZE 0x1000 138#define MV_ETH0_BASE (MV_BASE + 0x72000) 139#define MV_ETH1_BASE (MV_BASE + 0x76000) 140#define MV_ETH_SIZE 0x2000 141#if defined(SOC_MV_ORION) || defined(SOC_MV_KIRKWOOD) 142#define MV_SATAHC_BASE (MV_BASE + 0x80000) 143#define MV_SATAHC_SIZE 0x6000 144#elif defined(SOC_MV_DISCOVERY) 145#define MV_SATAHC_BASE (MV_BASE + 0xA0000) 146#define MV_SATAHC_SIZE 0x6000 147#endif 148 149#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 150 151/* 152 * Interrupt sources 153 */ 154#if defined(SOC_MV_ORION) 155 156#define MV_INT_BRIDGE 0 /* AHB-MBus Bridge Interrupt */ 157#define MV_INT_UART0 3 /* UART0 Interrupt */ 158#define MV_INT_UART1 4 159#define MV_INT_GPIO7_0 6 /* GPIO[7:0] Interrupt */ 160#define MV_INT_GPIO15_8 7 /* GPIO[15:8] Interrupt */ 161#define MV_INT_GPIO23_16 8 /* GPIO[23:16] Interrupt */ 162#define MV_INT_GPIO31_24 9 /* GPIO[31:24] Interrupt */ 163#define MV_INT_PEX0_ERR 10 /* PCI Express Error */ 164#define MV_INT_PEX0 11 /* PCI Express INTA,B,C,D Message */ 165#define MV_INT_PCI_ERR 15 /* PCI Error */ 166#define MV_INT_USB_BERR 16 /* USB Bridge Error */ 167#define MV_INT_USB_CI 17 /* USB Controller interrupt */ 168#define MV_INT_GBERX 18 /* GbE receive interrupt */ 169#define MV_INT_GBETX 19 /* GbE transmit interrupt */ 170#define MV_INT_GBEMISC 20 /* GbE misc. interrupt */ 171#define MV_INT_GBESUM 21 /* GbE summary interrupt */ 172#define MV_INT_GBEERR 22 /* GbE error interrupt */ 173#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 174#define MV_INT_IDMA0 24 /* IDMA chan. 0 completion interrupt */ 175#define MV_INT_IDMA1 25 /* IDMA chan. 1 completion interrupt */ 176#define MV_INT_IDMA2 26 /* IDMA chan. 2 completion interrupt */ 177#define MV_INT_IDMA3 27 /* IDMA chan. 3 completion interrupt */ 178#define MV_INT_SATA 29 /* Serial-ATA Interrupt */ 179 180#elif defined(SOC_MV_KIRKWOOD) 181 182#define MV_INT_BRIDGE 1 /* AHB-MBus Bridge Interrupt */ 183#define MV_INT_XOR0_CHAN0 5 /* XOR engine 0 channel 0 Interrupt */ 184#define MV_INT_XOR0_CHAN1 6 /* XOR engine 0 channel 1 Interrupt */ 185#define MV_INT_XOR1_CHAN0 7 /* XOR engine 1 channel 0 Interrupt */ 186#define MV_INT_XOR1_CHAN1 8 /* XOR engine 1 channel 1 Interrupt */ 187#define MV_INT_PEX0 9 /* PCI Express INTA,B,C,D Message */ 188#define MV_INT_GBESUM 11 /* GbE0 summary interrupt */ 189#define MV_INT_GBERX 12 /* GbE0 receive interrupt */ 190#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */ 191#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */ 192#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */ 193#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */ 194#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */ 195#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */ 196#define MV_INT_USB_CI 19 /* USB Controller interrupt */ 197#define MV_INT_SATA 21 /* Serial-ATA Interrupt */ 198#define MV_INT_CESA 22 /* Security engine completion int. */ 199#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 200#define MV_INT_UART0 33 /* UART0 Interrupt */ 201#define MV_INT_UART1 34 202#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */ 203#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */ 204#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */ 205#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */ 206#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */ 207#define MV_INT_GPIOHI15_8 40 /* GPIOHI[15:8] Interrupt */ 208#define MV_INT_GPIOHI23_16 41 /* GPIOHI[23:16] Interrupt */ 209#define MV_INT_XOR0_ERR 42 /* XOR engine 0 error Interrupt */ 210#define MV_INT_XOR1_ERR 43 /* XOR engine 1 error Interrupt */ 211#define MV_INT_PEX0_ERR 44 /* PCI Express Error */ 212#define MV_INT_GBEERR 46 /* GbE0 error interrupt */ 213#define MV_INT_GBE1ERR 47 /* GbE1 error interrupt */ 214#define MV_INT_USB_BERR 48 /* USB Bridge Error */ 215 216#elif defined(SOC_MV_DISCOVERY) 217 218#define MV_INT_ERRSUM 0 /* Summary of error interrupts */ 219#define MV_INT_SPI 1 /* SPI interrupt */ 220#define MV_INT_TWSI0 2 /* TWSI0 interrupt */ 221#define MV_INT_TWSI1 3 /* TWSI1 interrupt */ 222#define MV_INT_IDMA0 4 /* IDMA Channel0 completion */ 223#define MV_INT_IDMA1 5 /* IDMA Channel0 completion */ 224#define MV_INT_IDMA2 6 /* IDMA Channel0 completion */ 225#define MV_INT_IDMA3 7 /* IDMA Channel0 completion */ 226#define MV_INT_TIMER0 8 /* Timer0 interrupt */ 227#define MV_INT_TIMER1 9 /* Timer1 interrupt */ 228#define MV_INT_TIMER2 10 /* Timer2 interrupt */ 229#define MV_INT_TIMER3 11 /* Timer3 interrupt */ 230#define MV_INT_UART0 12 /* UART0 interrupt */ 231#define MV_INT_UART1 13 /* UART1 interrupt */ 232#define MV_INT_UART2 14 /* UART2 interrupt */ 233#define MV_INT_UART3 15 /* UART3 interrupt */ 234#define MV_INT_USB0 16 /* USB0 interrupt */ 235#define MV_INT_USB1 17 /* USB1 interrupt */ 236#define MV_INT_USB2 18 /* USB2 interrupt */ 237#define MV_INT_CESA 19 /* Crypto engine completion interrupt */ 238#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */ 239#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */ 240#define MV_INT_SATA 26 /* SATA interrupt */ 241#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */ 242#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */ 243#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */ 244#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */ 245#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */ 246#define MV_INT_PEX11 37 /* PCI Express port 1.1 INTA/B/C/D */ 247#define MV_INT_PEX12 38 /* PCI Express port 1.2 INTA/B/C/D */ 248#define MV_INT_PEX13 39 /* PCI Express port 1.3 INTA/B/C/D */ 249#define MV_INT_GBESUM 40 /* Gigabit Ethernet Port 0 summary */ 250#define MV_INT_GBERX 41 /* Gigabit Ethernet Port 0 Rx summary */ 251#define MV_INT_GBETX 42 /* Gigabit Ethernet Port 0 Tx summary */ 252#define MV_INT_GBEMISC 43 /* Gigabit Ethernet Port 0 Misc summ. */ 253#define MV_INT_GBE1SUM 44 /* Gigabit Ethernet Port 1 summary */ 254#define MV_INT_GBE1RX 45 /* Gigabit Ethernet Port 1 Rx summary */ 255#define MV_INT_GBE1TX 46 /* Gigabit Ethernet Port 1 Tx summary */ 256#define MV_INT_GBE1MISC 47 /* Gigabit Ethernet Port 1 Misc summ. */ 257#define MV_INT_GPIO7_0 56 /* GPIO[7:0] Interrupt */ 258#define MV_INT_GPIO15_8 57 /* GPIO[15:8] Interrupt */ 259#define MV_INT_GPIO23_16 58 /* GPIO[23:16] Interrupt */ 260#define MV_INT_GPIO31_24 59 /* GPIO[31:24] Interrupt */ 261#define MV_INT_DB_IN 60 /* Inbound Doorbell Cause reg Summary */ 262#define MV_INT_DB_OUT 61 /* Outbound Doorbell Cause reg Summ. */ 263#define MV_INT_CRYPT_ERR 64 /* Crypto engine error */ 264#define MV_INT_DEV_ERR 65 /* Device bus error */ 265#define MV_INT_IDMA_ERR 66 /* DMA error */ 266#define MV_INT_CPU_ERR 67 /* CPU error */ 267#define MV_INT_PEX0_ERR 68 /* PCI-Express port0 error */ 268#define MV_INT_PEX1_ERR 69 /* PCI-Express port1 error */ 269#define MV_INT_GBE_ERR 70 /* Gigabit Ethernet error */ 270#define MV_INT_USB_ERR 72 /* USB error */ 271#define MV_INT_DRAM_ERR 73 /* DRAM ECC error */ 272#define MV_INT_XOR_ERR 74 /* XOR engine error */ 273#define MV_INT_WD 79 /* WD Timer interrupt */ 274 275#endif /* SOC_MV_ORION */ 276 277#define BRIDGE_IRQ_CAUSE 0x10 278#define BRIGDE_IRQ_MASK 0x14 279 280#if defined(SOC_MV_DISCOVERY) 281#define IRQ_CAUSE_ERROR 0x0 282#define IRQ_CAUSE 0x4 283#define IRQ_CAUSE_HI 0x8 284#define IRQ_MASK_ERROR 0xC 285#define IRQ_MASK 0x10 286#define IRQ_MASK_HI 0x14 287#define IRQ_CAUSE_SELECT 0x18 288#define FIQ_MASK_ERROR 0x1C 289#define FIQ_MASK 0x20 290#define FIQ_MASK_HI 0x24 291#define FIQ_CAUSE_SELECT 0x28 292#define ENDPOINT_IRQ_MASK_ERROR 0x2C 293#define ENDPOINT_IRQ_MASK 0x30 294#define ENDPOINT_IRQ_MASK_HI 0x34 295#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 296#else /* !SOC_MV_DISCOVERY */ 297#define IRQ_CAUSE 0x0 298#define IRQ_MASK 0x4 299#define FIQ_MASK 0x8 300#define ENDPOINT_IRQ_MASK 0xC 301#define IRQ_CAUSE_HI 0x10 302#define IRQ_MASK_HI 0x14 303#define FIQ_MASK_HI 0x18 304#define ENDPOINT_IRQ_MASK_HI 0x1C 305#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 306#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 307#endif 308 309#define BRIDGE_IRQ_CAUSE 0x10 310#define IRQ_CPU_SELF 0x00000001 311#define IRQ_TIMER0 0x00000002 312#define IRQ_TIMER1 0x00000004 313#define IRQ_TIMER_WD 0x00000008 314 315#define BRIDGE_IRQ_MASK 0x14 316#define IRQ_CPU_MASK 0x00000001 317#define IRQ_TIMER0_MASK 0x00000002 318#define IRQ_TIMER1_MASK 0x00000004 319#define IRQ_TIMER_WD_MASK 0x00000008 320 321/* 322 * System reset 323 */ 324#define RSTOUTn_MASK 0x8 325#define WD_RST_OUT_EN 0x00000002 326#define SOFT_RST_OUT_EN 0x00000004 327#define SYSTEM_SOFT_RESET 0xc 328#define SYS_SOFT_RST 0x00000001 329 330/* 331 * Power Control 332 */ 333#define CPU_PM_CTRL 0x1C 334#define CPU_PM_CTRL_NONE 0 335 336#if defined(SOC_MV_KIRKWOOD) 337#define CPU_PM_CTRL_GE0 (1 << 0) 338#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 339#define CPU_PM_CTRL_PEX0 (1 << 2) 340#define CPU_PM_CTRL_USB0 (1 << 3) 341#define CPU_PM_CTRL_SDIO (1 << 4) 342#define CPU_PM_CTRL_TSU (1 << 5) 343#define CPU_PM_CTRL_DUNIT (1 << 6) 344#define CPU_PM_CTRL_RUNIT (1 << 7) 345#define CPU_PM_CTRL_XOR0 (1 << 8) 346#define CPU_PM_CTRL_AUDIO (1 << 9) 347#define CPU_PM_CTRL_SATA0 (1 << 14) 348#define CPU_PM_CTRL_SATA1 (1 << 15) 349#define CPU_PM_CTRL_XOR1 (1 << 16) 350#define CPU_PM_CTRL_CRYPTO (1 << 17) 351#define CPU_PM_CTRL_GE1 (1 << 18) 352#define CPU_PM_CTRL_TDM (1 << 19) 353#elif defined(SOC_MV_DISCOVERY) 354#define CPU_PM_CTRL_GE0 (1 << 1) 355#define CPU_PM_CTRL_GE1 (1 << 2) 356#define CPU_PM_CTRL_PEX00 (1 << 5) 357#define CPU_PM_CTRL_PEX01 (1 << 6) 358#define CPU_PM_CTRL_PEX02 (1 << 7) 359#define CPU_PM_CTRL_PEX03 (1 << 8) 360#define CPU_PM_CTRL_PEX10 (1 << 9) 361#define CPU_PM_CTRL_PEX11 (1 << 10) 362#define CPU_PM_CTRL_PEX12 (1 << 11) 363#define CPU_PM_CTRL_PEX13 (1 << 12) 364#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 365#define CPU_PM_CTRL_SATA0 (1 << 14) 366#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 367#define CPU_PM_CTRL_SATA1 (1 << 16) 368#define CPU_PM_CTRL_USB0 (1 << 17) 369#define CPU_PM_CTRL_USB1 (1 << 18) 370#define CPU_PM_CTRL_USB2 (1 << 19) 371#define CPU_PM_CTRL_IDMA (1 << 20) 372#define CPU_PM_CTRL_XOR (1 << 21) 373#define CPU_PM_CTRL_CRYPTO (1 << 22) 374#define CPU_PM_CTRL_DEVICE (1 << 23) 375#endif 376 377/* 378 * Timers 379 */ 380#define CPU_TIMER_CONTROL 0x0 381#define CPU_TIMER0_EN 0x00000001 382#define CPU_TIMER0_AUTO 0x00000002 383#define CPU_TIMER1_EN 0x00000004 384#define CPU_TIMER1_AUTO 0x00000008 385#define CPU_TIMER_WD_EN 0x00000010 386#define CPU_TIMER_WD_AUTO 0x00000020 387#define CPU_TIMER0_REL 0x10 388#define CPU_TIMER0 0x14 389 390/* 391 * GPIO 392 */ 393#define GPIO_DATA_OUT 0x00 394#define GPIO_DATA_OUT_EN_CTRL 0x04 395#define GPIO_BLINK_EN 0x08 396#define GPIO_DATA_IN_POLAR 0x0c 397#define GPIO_DATA_IN 0x10 398#define GPIO_INT_CAUSE 0x14 399#define GPIO_INT_EDGE_MASK 0x18 400#define GPIO_INT_LEV_MASK 0x1c 401 402#define GPIO_HI_DATA_OUT 0x40 403#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 404#define GPIO_HI_BLINK_EN 0x48 405#define GPIO_HI_DATA_IN_POLAR 0x4c 406#define GPIO_HI_DATA_IN 0x50 407#define GPIO_HI_INT_CAUSE 0x54 408#define GPIO_HI_INT_EDGE_MASK 0x58 409#define GPIO_HI_INT_LEV_MASK 0x5c 410 411#define GPIO(n) (1 << (n)) 412#define MV_GPIO_MAX_NPINS 64 413 414#define MV_GPIO_BLINK 0x1 415#define MV_GPIO_POLAR_LOW 0x2 416#define MV_GPIO_EDGE 0x4 417#define MV_GPIO_LEVEL 0x8 418 419#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 420#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 421#define IRQ2GPIO(irq) ((irq) - NIRQ) 422 423/* 424 * MPP 425 */ 426#if defined(SOC_MV_ORION) 427#define MPP_CONTROL0 0x00 428#define MPP_CONTROL1 0x04 429#define MPP_CONTROL2 0x50 430#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 431#define MPP_CONTROL0 0x00 432#define MPP_CONTROL1 0x04 433#define MPP_CONTROL2 0x08 434#define MPP_CONTROL3 0x0C 435#define MPP_CONTROL4 0x10 436#define MPP_CONTROL5 0x14 437#define MPP_CONTROL6 0x18 438#else 439#error SOC_MV_XX not defined 440#endif 441 442#if defined(SOC_MV_ORION) 443#define SAMPLE_AT_RESET 0x10 444#elif defined(SOC_MV_KIRKWOOD) 445#define SAMPLE_AT_RESET 0x30 446#elif defined(SOC_MV_DISCOVERY) 447#define SAMPLE_AT_RESET_LO 0x30 448#define SAMPLE_AT_RESET_HI 0x34 449#else 450#error SOC_MV_XX not defined 451#endif 452 453/* 454 * Clocks 455 */ 456#if defined(SOC_MV_ORION) 457#define TCLK_MASK 0x00000300 458#define TCLK_SHIFT 0x08 459#elif defined(SOC_MV_DISCOVERY) 460#define TCLK_MASK 0x00000180 461#define TCLK_SHIFT 0x07 462#endif 463 464#define TCLK_100MHZ 100000000 465#define TCLK_125MHZ 125000000 466#define TCLK_133MHZ 133333333 467#define TCLK_150MHZ 150000000 468#define TCLK_166MHZ 166666667 469#define TCLK_200MHZ 200000000 470 471/* 472 * Chip ID 473 */ 474#define MV_DEV_88F5181 0x5181 475#define MV_DEV_88F5182 0x5182 476#define MV_DEV_88F5281 0x5281 477#define MV_DEV_88F6281 0x6281 478#define MV_DEV_MV78100 0x6381 479 480/* 481 * Decode windows definitions and macros 482 */ 483#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 484#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 485#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 486#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 487#if defined(SOC_MV_DISCOVERY) 488#define MV_WIN_CPU_MAX 14 489#else 490#define MV_WIN_CPU_MAX 8 491#endif 492 493#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 494#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 495#define MV_WIN_DDR_MAX 4 496 497#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) 498#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) 499#define MV_WIN_CESA_MAX 4 500 501#define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0) 502#define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4) 503#define MV_WIN_USB_MAX 4 504 505#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 506#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 507#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 508#define MV_WIN_ETH_MAX 6 509 510#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 511#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 512#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 513#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 514#define MV_WIN_IDMA_MAX 8 515#define MV_IDMA_CHAN_MAX 4 516 517#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 518#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 519#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 520#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 521#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 522#define MV_WIN_XOR_MAX 8 523#define MV_XOR_CHAN_MAX 2 524#define MV_XOR_NON_REMAP 4 525 526#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 527 (n) + 1) + 0x1820) 528#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 529 (n) + 1) + 0x1824) 530#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 531 (n) + 1) + 0x182C) 532#define MV_WIN_PCIE_MAX 6 533 534#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 535#define MV_PCIE_BAR_MAX 3 536 537#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 538#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 539#define MV_WIN_SATA_MAX 4 540 541#define WIN_REG_IDX_RD(pre,reg,off,base) \ 542 static __inline uint32_t \ 543 pre ## _ ## reg ## _read(int i) \ 544 { \ 545 return (bus_space_read_4(obio_tag, base, off(i))); \ 546 } 547 548#define WIN_REG_IDX_RD2(pre,reg,off,base) \ 549 static __inline uint32_t \ 550 pre ## _ ## reg ## _read(int i, int j) \ 551 { \ 552 return (bus_space_read_4(obio_tag, base, off(i, j))); \ 553 } \ 554 555#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 556 static __inline uint32_t \ 557 pre ## _ ## reg ## _read(uint32_t base, int i) \ 558 { \ 559 return (bus_space_read_4(obio_tag, base, off(i))); \ 560 } 561 562#define WIN_REG_IDX_WR(pre,reg,off,base) \ 563 static __inline void \ 564 pre ## _ ## reg ## _write(int i, uint32_t val) \ 565 { \ 566 bus_space_write_4(obio_tag, base, off(i), val); \ 567 } 568 569#define WIN_REG_IDX_WR2(pre,reg,off,base) \ 570 static __inline void \ 571 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 572 { \ 573 bus_space_write_4(obio_tag, base, off(i, j), val); \ 574 } 575 576#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 577 static __inline void \ 578 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 579 { \ 580 bus_space_write_4(obio_tag, base, off(i), val); \ 581 } 582 583#define WIN_REG_RD(pre,reg,off,base) \ 584 static __inline uint32_t \ 585 pre ## _ ## reg ## _read(void) \ 586 { \ 587 return (bus_space_read_4(obio_tag, base, off)); \ 588 } 589 590#define WIN_REG_BASE_RD(pre,reg,off) \ 591 static __inline uint32_t \ 592 pre ## _ ## reg ## _read(uint32_t base) \ 593 { \ 594 return (bus_space_read_4(obio_tag, base, off)); \ 595 } 596 597#define WIN_REG_WR(pre,reg,off,base) \ 598 static __inline void \ 599 pre ## _ ## reg ## _write(uint32_t val) \ 600 { \ 601 bus_space_write_4(obio_tag, base, off, val); \ 602 } 603 604#define WIN_REG_BASE_WR(pre,reg,off) \ 605 static __inline void \ 606 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 607 { \ 608 bus_space_write_4(obio_tag, base, off, val); \ 609 } 610 611#endif /* _MVREG_H_ */ 612