mvreg.h revision 183840
1/*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 183840 2008-10-13 20:07:13Z raj $ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#include <machine/intr.h> 38 39/* 40 * Physical addresses of integrated SoC peripherals 41 */ 42#define MV_PHYS_BASE 0xF1000000 43#define MV_SIZE 0x100000 44 45/* 46 * Decode windows addresses (physical) 47 */ 48#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 49#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 50#define MV_PCIE_IO_SIZE (1024 * 1024) 51#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 52#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 53#define MV_PCI_IO_SIZE (1024 * 1024) 54 55#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 56#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 57#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 58#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 59#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 60#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 61 62/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ 63 64/* 512KB NOR FLASH */ 65#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 66#define MV_DEV_BOOT_SIZE (512 * 1024) 67/* CS0: 7-seg LED */ 68#define MV_DEV_CS0_PHYS_BASE 0xFA000000 69#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 70/* CS1: 32MB NOR FLASH */ 71#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 72#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 73/* CS2: 32MB NAND FLASH */ 74#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 75#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ 76 77/* XXX this is probably not robust against wraparounds... */ 78#if ((MV_DEV_CS2_PHYS_BASE + MV_DEV_CS2_SIZE) > 0xFFFEFFFF) 79#error Devices memory layout overlaps reset vectors range! 80#endif 81 82/* 83 * Integrated SoC peripherals addresses 84 */ 85#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 86#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 87#define MV_MPP_BASE (MV_BASE + 0x10000) 88#define MV_GPIO_BASE (MV_BASE + 0x10100) 89#define MV_GPIO_SIZE 0x20 90#define MV_RTC_BASE (MV_BASE + 0x10300) 91#define MV_RTC_SIZE 0x08 92#define MV_TWSI_BASE (MV_BASE + 0x11000) 93#define MV_TWSI_SIZE 0x20 94#define MV_UART0_BASE (MV_BASE + 0x12000) 95#define MV_UART1_BASE (MV_BASE + 0x12100) 96#define MV_UART_SIZE 0x20 97#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 98#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 99#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 100#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 101#define MV_IC_SIZE 0x3C 102#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) 103#define MV_TIMERS_SIZE 0x30 104#define MV_PCI_BASE (MV_BASE + 0x30000) 105#define MV_PCI_SIZE 0x2000 106#define MV_PCIE_BASE (MV_BASE + 0x40000) 107#define MV_PCIE_SIZE 0x2000 108#define MV_USB0_BASE (MV_BASE + 0x50000) 109#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) 110#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) 111#define MV_USB_SIZE 0x1000 112#define MV_USB_HOST_OFST 0x0100 /* EHCI HC regs start at this offset within USB range */ 113#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) 114#define MV_IDMA_BASE (MV_BASE + 0x60000) 115#define MV_IDMA_SIZE 0x1000 116#define MV_XOR_BASE (MV_BASE + 0x60000) 117#define MV_XOR_SIZE 0x1000 118#define MV_ETH0_BASE (MV_BASE + 0x72000) 119#define MV_ETH1_BASE (MV_BASE + 0x76000) 120#define MV_ETH_SIZE 0x2000 121 122#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 123 124/* 125 * Interrupt sources 126 */ 127#if defined(SOC_MV_ORION) 128 129#define MV_INT_BRIDGE 0 /* AHB-MBus Bridge Interrupt */ 130#define MV_INT_UART0 3 /* UART0 Interrupt */ 131#define MV_INT_UART1 4 132#define MV_INT_GPIO7_0 6 /* GPIO[7:0] Interrupt */ 133#define MV_INT_GPIO15_8 7 /* GPIO[15:8] Interrupt */ 134#define MV_INT_GPIO23_16 8 /* GPIO[23:16] Interrupt */ 135#define MV_INT_GPIO31_24 9 /* GPIO[31:24] Interrupt */ 136#define MV_INT_PEX0_ERR 10 /* PCI Express Error */ 137#define MV_INT_PEX0 11 /* PCI Express INTA,B,C,D Message */ 138#define MV_INT_PCI_ERR 15 /* PCI Error */ 139#define MV_INT_USB_BERR 16 /* USB Bridge Error */ 140#define MV_INT_USB_CI 17 /* USB Controller interrupt */ 141#define MV_INT_GBERX 18 /* GbE receive interrupt */ 142#define MV_INT_GBETX 19 /* GbE transmit interrupt */ 143#define MV_INT_GBEMISC 20 /* GbE misc. interrupt */ 144#define MV_INT_GBESUM 21 /* GbE summary interrupt */ 145#define MV_INT_GBEERR 22 /* GbE error interrupt */ 146#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 147#define MV_INT_IDMA0 24 /* IDMA chan. 0 completion interrupt */ 148#define MV_INT_IDMA1 25 /* IDMA chan. 1 completion interrupt */ 149#define MV_INT_IDMA2 26 /* IDMA chan. 2 completion interrupt */ 150#define MV_INT_IDMA3 27 /* IDMA chan. 3 completion interrupt */ 151#define MV_INT_SATA 29 /* Serial-ATA Interrupt */ 152 153#elif defined(SOC_MV_KIRKWOOD) 154 155#define MV_INT_BRIDGE 1 /* AHB-MBus Bridge Interrupt */ 156#define MV_INT_XOR0_CHAN0 5 /* XOR engine 0 channel 0 Interrupt */ 157#define MV_INT_XOR0_CHAN1 6 /* XOR engine 0 channel 1 Interrupt */ 158#define MV_INT_XOR1_CHAN0 7 /* XOR engine 1 channel 0 Interrupt */ 159#define MV_INT_XOR1_CHAN1 8 /* XOR engine 1 channel 1 Interrupt */ 160#define MV_INT_PEX0 9 /* PCI Express INTA,B,C,D Message */ 161#define MV_INT_GBESUM 11 /* GbE0 summary interrupt */ 162#define MV_INT_GBERX 12 /* GbE0 receive interrupt */ 163#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */ 164#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */ 165#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */ 166#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */ 167#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */ 168#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */ 169#define MV_INT_USB_CI 19 /* USB Controller interrupt */ 170#define MV_INT_SATA 21 /* Serial-ATA Interrupt */ 171#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 172#define MV_INT_UART0 33 /* UART0 Interrupt */ 173#define MV_INT_UART1 34 174#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */ 175#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */ 176#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */ 177#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */ 178#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */ 179#define MV_INT_GPIOHI15_8 40 /* GPIOHI[15:8] Interrupt */ 180#define MV_INT_GPIOHI23_16 41 /* GPIOHI[23:16] Interrupt */ 181#define MV_INT_XOR0_ERR 42 /* XOR engine 0 error Interrupt */ 182#define MV_INT_XOR1_ERR 43 /* XOR engine 1 error Interrupt */ 183#define MV_INT_PEX0_ERR 44 /* PCI Express Error */ 184#define MV_INT_GBEERR 46 /* GbE0 error interrupt */ 185#define MV_INT_GBE1ERR 47 /* GbE1 error interrupt */ 186#define MV_INT_USB_BERR 48 /* USB Bridge Error */ 187 188#elif defined(SOC_MV_DISCOVERY) 189 190#define MV_INT_ERRSUM 0 /* Summary of error interrupts */ 191#define MV_INT_SPI 1 /* SPI interrupt */ 192#define MV_INT_TWSI0 2 /* TWSI0 interrupt */ 193#define MV_INT_TWSI1 3 /* TWSI1 interrupt */ 194#define MV_INT_IDMA0 4 /* IDMA Channel0 completion */ 195#define MV_INT_IDMA1 5 /* IDMA Channel0 completion */ 196#define MV_INT_IDMA2 6 /* IDMA Channel0 completion */ 197#define MV_INT_IDMA3 7 /* IDMA Channel0 completion */ 198#define MV_INT_TIMER0 8 /* Timer0 interrupt */ 199#define MV_INT_TIMER1 9 /* Timer1 interrupt */ 200#define MV_INT_TIMER2 10 /* Timer2 interrupt */ 201#define MV_INT_TIMER3 11 /* Timer3 interrupt */ 202#define MV_INT_UART0 12 /* UART0 interrupt */ 203#define MV_INT_UART1 13 /* UART1 interrupt */ 204#define MV_INT_UART2 14 /* UART2 interrupt */ 205#define MV_INT_UART3 15 /* UART3 interrupt */ 206#define MV_INT_USB0 16 /* USB0 interrupt */ 207#define MV_INT_USB1 17 /* USB1 interrupt */ 208#define MV_INT_USB2 18 /* USB2 interrupt */ 209#define MV_INT_CRYPTO 19 /* Crypto engine completion interrupt */ 210#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */ 211#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */ 212#define MV_INT_SATA 26 /* SATA interrupt */ 213#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */ 214#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */ 215#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */ 216#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */ 217#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */ 218#define MV_INT_PEX11 37 /* PCI Express port 1.1 INTA/B/C/D */ 219#define MV_INT_PEX12 38 /* PCI Express port 1.2 INTA/B/C/D */ 220#define MV_INT_PEX13 39 /* PCI Express port 1.3 INTA/B/C/D */ 221#define MV_INT_GBESUM 40 /* Gigabit Ethernet Port 0 summary */ 222#define MV_INT_GBERX 41 /* Gigabit Ethernet Port 0 Rx summary */ 223#define MV_INT_GBETX 42 /* Gigabit Ethernet Port 0 Tx summary */ 224#define MV_INT_GBEMISC 43 /* Gigabit Ethernet Port 0 Misc summ. */ 225#define MV_INT_GBE1SUM 44 /* Gigabit Ethernet Port 1 summary */ 226#define MV_INT_GBE1RX 45 /* Gigabit Ethernet Port 1 Rx summary */ 227#define MV_INT_GBE1TX 46 /* Gigabit Ethernet Port 1 Tx summary */ 228#define MV_INT_GBE1MISC 47 /* Gigabit Ethernet Port 1 Misc summ. */ 229#define MV_INT_GPIO7_0 56 /* GPIO[7:0] Interrupt */ 230#define MV_INT_GPIO15_8 57 /* GPIO[15:8] Interrupt */ 231#define MV_INT_GPIO23_16 58 /* GPIO[23:16] Interrupt */ 232#define MV_INT_GPIO31_24 59 /* GPIO[31:24] Interrupt */ 233#define MV_INT_DB_IN 60 /* Inbound Doorbell Cause reg Summary */ 234#define MV_INT_DB_OUT 61 /* Outbound Doorbell Cause reg Summ. */ 235#define MV_INT_CRYPT_ERR 64 /* Crypto engine error */ 236#define MV_INT_DEV_ERR 65 /* Device bus error */ 237#define MV_INT_IDMA_ERR 66 /* DMA error */ 238#define MV_INT_CPU_ERR 67 /* CPU error */ 239#define MV_INT_PEX0_ERR 68 /* PCI-Express port0 error */ 240#define MV_INT_PEX1_ERR 69 /* PCI-Express port1 error */ 241#define MV_INT_GBE_ERR 70 /* Gigabit Ethernet error */ 242#define MV_INT_USB_ERR 72 /* USB error */ 243#define MV_INT_DRAM_ERR 73 /* DRAM ECC error */ 244#define MV_INT_XOR_ERR 74 /* XOR engine error */ 245#define MV_INT_WD 79 /* WD Timer interrupt */ 246 247#endif /* SOC_MV_ORION */ 248 249#define BRIDGE_IRQ_CAUSE 0x10 250#define BRIGDE_IRQ_MASK 0x14 251 252#if defined(SOC_MV_DISCOVERY) 253#define IRQ_CAUSE_ERROR 0x0 254#define IRQ_CAUSE 0x4 255#define IRQ_CAUSE_HI 0x8 256#define IRQ_MASK_ERROR 0xC 257#define IRQ_MASK 0x10 258#define IRQ_MASK_HI 0x14 259#define IRQ_CAUSE_SELECT 0x18 260#define FIQ_MASK_ERROR 0x1C 261#define FIQ_MASK 0x20 262#define FIQ_MASK_HI 0x24 263#define FIQ_CAUSE_SELECT 0x28 264#define ENDPOINT_IRQ_MASK_ERROR 0x2C 265#define ENDPOINT_IRQ_MASK 0x30 266#define ENDPOINT_IRQ_MASK_HI 0x34 267#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 268#else /* !SOC_MV_DISCOVERY */ 269#define IRQ_CAUSE 0x0 270#define IRQ_MASK 0x4 271#define FIQ_MASK 0x8 272#define ENDPOINT_IRQ_MASK 0xC 273#define IRQ_CAUSE_HI 0x10 274#define IRQ_MASK_HI 0x14 275#define FIQ_MASK_HI 0x18 276#define ENDPOINT_IRQ_MASK_HI 0x1C 277#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 278#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 279#endif 280 281#define BRIDGE_IRQ_CAUSE 0x10 282#define IRQ_CPU_SELF 0x00000001 283#define IRQ_TIMER0 0x00000002 284#define IRQ_TIMER1 0x00000004 285#define IRQ_TIMER_WD 0x00000008 286 287#define BRIDGE_IRQ_MASK 0x14 288#define IRQ_CPU_MASK 0x00000001 289#define IRQ_TIMER0_MASK 0x00000002 290#define IRQ_TIMER1_MASK 0x00000004 291#define IRQ_TIMER_WD_MASK 0x00000008 292 293/* 294 * System reset 295 */ 296#define RSTOUTn_MASK 0x8 297#define WD_RST_OUT_EN 0x00000002 298#define SOFT_RST_OUT_EN 0x00000004 299#define SYSTEM_SOFT_RESET 0xc 300#define SYS_SOFT_RST 0x00000001 301 302/* 303 * Power Control 304 */ 305#define CPU_PM_CTRL 0x1C 306#define CPU_PM_CTRL_NONE 0 307 308#if defined(SOC_MV_KIRKWOOD) 309#define CPU_PM_CTRL_GE0 (1 << 0) 310#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 311#define CPU_PM_CTRL_PEX0 (1 << 2) 312#define CPU_PM_CTRL_USB0 (1 << 3) 313#define CPU_PM_CTRL_SDIO (1 << 4) 314#define CPU_PM_CTRL_TSU (1 << 5) 315#define CPU_PM_CTRL_DUNIT (1 << 6) 316#define CPU_PM_CTRL_RUNIT (1 << 7) 317#define CPU_PM_CTRL_XOR0 (1 << 8) 318#define CPU_PM_CTRL_AUDIO (1 << 9) 319#define CPU_PM_CTRL_SATA0 (1 << 14) 320#define CPU_PM_CTRL_SATA1 (1 << 15) 321#define CPU_PM_CTRL_XOR1 (1 << 16) 322#define CPU_PM_CTRL_CRYPTO (1 << 17) 323#define CPU_PM_CTRL_GE1 (1 << 18) 324#define CPU_PM_CTRL_TDM (1 << 19) 325#elif defined(SOC_MV_DISCOVERY) 326#define CPU_PM_CTRL_GE0 (1 << 1) 327#define CPU_PM_CTRL_GE1 (1 << 2) 328#define CPU_PM_CTRL_PEX00 (1 << 5) 329#define CPU_PM_CTRL_PEX01 (1 << 6) 330#define CPU_PM_CTRL_PEX02 (1 << 7) 331#define CPU_PM_CTRL_PEX03 (1 << 8) 332#define CPU_PM_CTRL_PEX10 (1 << 9) 333#define CPU_PM_CTRL_PEX11 (1 << 10) 334#define CPU_PM_CTRL_PEX12 (1 << 11) 335#define CPU_PM_CTRL_PEX13 (1 << 12) 336#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 337#define CPU_PM_CTRL_SATA0 (1 << 14) 338#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 339#define CPU_PM_CTRL_SATA1 (1 << 16) 340#define CPU_PM_CTRL_USB0 (1 << 17) 341#define CPU_PM_CTRL_USB1 (1 << 18) 342#define CPU_PM_CTRL_USB2 (1 << 19) 343#define CPU_PM_CTRL_IDMA (1 << 20) 344#define CPU_PM_CTRL_XOR (1 << 21) 345#define CPU_PM_CTRL_CRYPTO (1 << 22) 346#define CPU_PM_CTRL_DEVICE (1 << 23) 347#endif 348 349/* 350 * Timers 351 */ 352#define CPU_TIMER_CONTROL 0x0 353#define CPU_TIMER0_EN 0x00000001 354#define CPU_TIMER0_AUTO 0x00000002 355#define CPU_TIMER1_EN 0x00000004 356#define CPU_TIMER1_AUTO 0x00000008 357#define CPU_TIMER_WD_EN 0x00000010 358#define CPU_TIMER_WD_AUTO 0x00000020 359#define CPU_TIMER0_REL 0x10 360#define CPU_TIMER0 0x14 361 362/* 363 * GPIO 364 */ 365#define GPIO_DATA_OUT 0x00 366#define GPIO_DATA_OUT_EN_CTRL 0x04 367#define GPIO_BLINK_EN 0x08 368#define GPIO_DATA_IN_POLAR 0x0c 369#define GPIO_DATA_IN 0x10 370#define GPIO_INT_CAUSE 0x14 371#define GPIO_INT_EDGE_MASK 0x18 372#define GPIO_INT_LEV_MASK 0x1c 373 374#define GPIO_HI_DATA_OUT 0x40 375#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 376#define GPIO_HI_BLINK_EN 0x48 377#define GPIO_HI_DATA_IN_POLAR 0x4c 378#define GPIO_HI_DATA_IN 0x50 379#define GPIO_HI_INT_CAUSE 0x54 380#define GPIO_HI_INT_EDGE_MASK 0x58 381#define GPIO_HI_INT_LEV_MASK 0x5c 382 383#define GPIO(n) (1 << (n)) 384#define MV_GPIO_MAX_NPINS 64 385 386#define MV_GPIO_BLINK 0x1 387#define MV_GPIO_POLARITY 0x2 388#define MV_GPIO_EDGE 0x4 389#define MV_GPIO_LEVEL 0x8 390 391#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 392#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 393#define IRQ2GPIO(irq) ((irq) - NIRQ) 394 395/* 396 * MPP 397 */ 398#define MPP_CONTROL0 0x00 399#define MPP_CONTROL1 0x04 400#define MPP_CONTROL2 0x50 401#define DEVICE_MULTIPLEX 0x08 402 403#if defined(SOC_MV_ORION) 404#define SAMPLE_AT_RESET 0x10 405#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 406#define SAMPLE_AT_RESET 0x30 407#else 408#error SOC_MV_XX not defined 409#endif 410 411/* 412 * Clocks 413 */ 414#ifdef SOC_MV_ORION 415#define TCLK_MASK 0x300 416#define TCLK_SHIFT 0x8 417#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 418#define TCLK_MASK 0x30000 419#define TCLK_SHIFT 0x10 420#else 421#error SOC_MV_XX not defined 422#endif 423 424#define TCLK_100MHZ 100000000 425#define TCLK_125MHZ 125000000 426#define TCLK_133MHZ 133333333 427#define TCLK_150MHZ 150000000 428#define TCLK_166MHZ 166666667 429#define TCLK_200MHZ 200000000 430 431/* 432 * Chip ID 433 */ 434#define MV_DEV_88F5181 0x5181 435#define MV_DEV_88F5182 0x5182 436#define MV_DEV_88F5281 0x5281 437#define MV_DEV_88F6281 0x6281 438#define MV_DEV_MV78100 0x6381 439 440/* 441 * Decode windows definitions and macros 442 */ 443#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 444#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 445#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 446#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 447#if defined(SOC_MV_DISCOVERY) 448#define MV_WIN_CPU_MAX 14 449#else 450#define MV_WIN_CPU_MAX 8 451#endif 452 453#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 454#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 455#define MV_WIN_DDR_MAX 4 456 457#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0) 458#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4) 459#define MV_WIN_USB_MAX 4 460 461#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 462#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 463#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 464#define MV_WIN_ETH_MAX 6 465 466#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 467#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 468#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 469#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 470#define MV_WIN_IDMA_MAX 8 471#define MV_IDMA_CHAN_MAX 4 472 473#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 474 (n) + 1) + 0x1820) 475#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 476 (n) + 1) + 0x1824) 477#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 478 (n) + 1) + 0x182C) 479#define MV_WIN_PCIE_MAX 6 480 481#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 482#define MV_PCIE_BAR_MAX 3 483 484#define WIN_REG_IDX_RD(pre,reg,off,base) \ 485 static __inline uint32_t \ 486 pre ## _ ## reg ## _read(int i) \ 487 { \ 488 return (bus_space_read_4(obio_tag, base, off(i))); \ 489 } 490 491#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 492 static __inline uint32_t \ 493 pre ## _ ## reg ## _read(uint32_t base, int i) \ 494 { \ 495 return (bus_space_read_4(obio_tag, base, off(i))); \ 496 } 497 498#define WIN_REG_IDX_WR(pre,reg,off,base) \ 499 static __inline void \ 500 pre ## _ ## reg ## _write(int i, uint32_t val) \ 501 { \ 502 bus_space_write_4(obio_tag, base, off(i), val); \ 503 } 504 505#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 506 static __inline void \ 507 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 508 { \ 509 bus_space_write_4(obio_tag, base, off(i), val); \ 510 } 511 512#define WIN_REG_RD(pre,reg,off,base) \ 513 static __inline uint32_t \ 514 pre ## _ ## reg ## _read(void) \ 515 { \ 516 return (bus_space_read_4(obio_tag, base, off)); \ 517 } 518 519#define WIN_REG_BASE_RD(pre,reg,off) \ 520 static __inline uint32_t \ 521 pre ## _ ## reg ## _read(uint32_t base) \ 522 { \ 523 return (bus_space_read_4(obio_tag, base, off)); \ 524 } 525 526#define WIN_REG_WR(pre,reg,off,base) \ 527 static __inline void \ 528 pre ## _ ## reg ## _write(uint32_t val) \ 529 { \ 530 bus_space_write_4(obio_tag, base, off, val); \ 531 } 532 533#define WIN_REG_BASE_WR(pre,reg,off) \ 534 static __inline void \ 535 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 536 { \ 537 bus_space_write_4(obio_tag, base, off, val); \ 538 } 539 540#endif /* _MVREG_H_ */ 541