armreg.h revision 234006
1172734Simp/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1998, 2001 Ben Harris 5129198Scognet * Copyright (c) 1994-1996 Mark Brinicombe. 6129198Scognet * Copyright (c) 1994 Brini. 7129198Scognet * All rights reserved. 8129198Scognet * 9129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 10129198Scognet * 11129198Scognet * Redistribution and use in source and binary forms, with or without 12129198Scognet * modification, are permitted provided that the following conditions 13129198Scognet * are met: 14129198Scognet * 1. Redistributions of source code must retain the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer. 16129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 17129198Scognet * notice, this list of conditions and the following disclaimer in the 18129198Scognet * documentation and/or other materials provided with the distribution. 19129198Scognet * 3. All advertising materials mentioning features or use of this software 20129198Scognet * must display the following acknowledgement: 21129198Scognet * This product includes software developed by Brini. 22129198Scognet * 4. The name of the company nor the name of the author may be used to 23129198Scognet * endorse or promote products derived from this software without specific 24129198Scognet * prior written permission. 25129198Scognet * 26129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36129198Scognet * SUCH DAMAGE. 37129198Scognet * 38129198Scognet * $FreeBSD: head/sys/arm/include/armreg.h 234006 2012-04-07 23:51:16Z stas $ 39129198Scognet */ 40129198Scognet 41129198Scognet#ifndef MACHINE_ARMREG_H 42129198Scognet#define MACHINE_ARMREG_H 43172734Simp 44129198Scognet#define INSN_SIZE 4 45129198Scognet#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46129198Scognet#define PSR_MODE 0x0000001f /* mode mask */ 47129198Scognet#define PSR_USR26_MODE 0x00000000 48129198Scognet#define PSR_FIQ26_MODE 0x00000001 49129198Scognet#define PSR_IRQ26_MODE 0x00000002 50129198Scognet#define PSR_SVC26_MODE 0x00000003 51129198Scognet#define PSR_USR32_MODE 0x00000010 52129198Scognet#define PSR_FIQ32_MODE 0x00000011 53129198Scognet#define PSR_IRQ32_MODE 0x00000012 54129198Scognet#define PSR_SVC32_MODE 0x00000013 55129198Scognet#define PSR_ABT32_MODE 0x00000017 56129198Scognet#define PSR_UND32_MODE 0x0000001b 57129198Scognet#define PSR_SYS32_MODE 0x0000001f 58129198Scognet#define PSR_32_MODE 0x00000010 59129198Scognet#define PSR_FLAGS 0xf0000000 /* flags */ 60129198Scognet 61129198Scognet#define PSR_C_bit (1 << 29) /* carry */ 62129198Scognet 63129198Scognet/* The high-order byte is always the implementor */ 64129198Scognet#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65129198Scognet#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66129198Scognet#define CPU_ID_DEC 0x44000000 /* 'D' */ 67129198Scognet#define CPU_ID_INTEL 0x69000000 /* 'i' */ 68129198Scognet#define CPU_ID_TI 0x54000000 /* 'T' */ 69172734Simp#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70129198Scognet 71129198Scognet/* How to decide what format the CPUID is in. */ 72129198Scognet#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73129198Scognet#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74129198Scognet#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75129198Scognet 76129198Scognet/* On ARM3 and ARM6, this byte holds the foundry ID. */ 77129198Scognet#define CPU_ID_FOUNDRY_MASK 0x00ff0000 78129198Scognet#define CPU_ID_FOUNDRY_VLSI 0x00560000 79129198Scognet 80129198Scognet/* On ARM7 it holds the architecture and variant (sub-model) */ 81129198Scognet#define CPU_ID_7ARCH_MASK 0x00800000 82129198Scognet#define CPU_ID_7ARCH_V3 0x00000000 83129198Scognet#define CPU_ID_7ARCH_V4T 0x00800000 84129198Scognet#define CPU_ID_7VARIANT_MASK 0x007f0000 85129198Scognet 86129198Scognet/* On more recent ARMs, it does the same, but in a different format */ 87129198Scognet#define CPU_ID_ARCH_MASK 0x000f0000 88129198Scognet#define CPU_ID_ARCH_V3 0x00000000 89129198Scognet#define CPU_ID_ARCH_V4 0x00010000 90129198Scognet#define CPU_ID_ARCH_V4T 0x00020000 91129198Scognet#define CPU_ID_ARCH_V5 0x00030000 92129198Scognet#define CPU_ID_ARCH_V5T 0x00040000 93129198Scognet#define CPU_ID_ARCH_V5TE 0x00050000 94172734Simp#define CPU_ID_ARCH_V5TEJ 0x00060000 95172734Simp#define CPU_ID_ARCH_V6 0x00070000 96129198Scognet#define CPU_ID_VARIANT_MASK 0x00f00000 97129198Scognet 98129198Scognet/* Next three nybbles are part number */ 99129198Scognet#define CPU_ID_PARTNO_MASK 0x0000fff0 100129198Scognet 101129198Scognet/* Intel XScale has sub fields in part number */ 102129198Scognet#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 103129198Scognet#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 104129198Scognet#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 105129198Scognet 106129198Scognet/* And finally, the revision number. */ 107129198Scognet#define CPU_ID_REVISION_MASK 0x0000000f 108129198Scognet 109129198Scognet/* Individual CPUs are probably best IDed by everything but the revision. */ 110129198Scognet#define CPU_ID_CPU_MASK 0xfffffff0 111129198Scognet 112129198Scognet/* Fake CPU IDs for ARMs without CP15 */ 113129198Scognet#define CPU_ID_ARM2 0x41560200 114129198Scognet#define CPU_ID_ARM250 0x41560250 115129198Scognet 116129198Scognet/* Pre-ARM7 CPUs -- [15:12] == 0 */ 117129198Scognet#define CPU_ID_ARM3 0x41560300 118129198Scognet#define CPU_ID_ARM600 0x41560600 119129198Scognet#define CPU_ID_ARM610 0x41560610 120129198Scognet#define CPU_ID_ARM620 0x41560620 121129198Scognet 122129198Scognet/* ARM7 CPUs -- [15:12] == 7 */ 123129198Scognet#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 124129198Scognet#define CPU_ID_ARM710 0x41007100 125172734Simp#define CPU_ID_ARM7500 0x41027100 126129198Scognet#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 127129198Scognet#define CPU_ID_ARM7500FE 0x41077100 128129198Scognet#define CPU_ID_ARM710T 0x41807100 129129198Scognet#define CPU_ID_ARM720T 0x41807200 130129198Scognet#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 131129198Scognet#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 132129198Scognet 133129198Scognet/* Post-ARM7 CPUs */ 134129198Scognet#define CPU_ID_ARM810 0x41018100 135129198Scognet#define CPU_ID_ARM920T 0x41129200 136152653Scognet#define CPU_ID_ARM920T_ALT 0x41009200 137129198Scognet#define CPU_ID_ARM922T 0x41029220 138172734Simp#define CPU_ID_ARM926EJS 0x41069260 139129198Scognet#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 140129198Scognet#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 141129198Scognet#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 142129198Scognet#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 143129198Scognet#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 144129198Scognet#define CPU_ID_ARM1022ES 0x4105a220 145172734Simp#define CPU_ID_ARM1026EJS 0x4106a260 146172734Simp#define CPU_ID_ARM1136JS 0x4107b360 147172734Simp#define CPU_ID_ARM1136JSR1 0x4117b360 148129198Scognet#define CPU_ID_SA110 0x4401a100 149129198Scognet#define CPU_ID_SA1100 0x4401a110 150129198Scognet#define CPU_ID_TI925T 0x54029250 151183835Sraj#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 152183835Sraj#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 153183835Sraj#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 154204121Skevlo#define CPU_ID_FA526 0x66015260 155204121Skevlo#define CPU_ID_FA626TE 0x66056260 156129198Scognet#define CPU_ID_SA1110 0x6901b110 157129198Scognet#define CPU_ID_IXP1200 0x6901c120 158129198Scognet#define CPU_ID_80200 0x69052000 159129198Scognet#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 160129198Scognet#define CPU_ID_PXA210 0x69052120 161129198Scognet#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 162129198Scognet#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 163129198Scognet#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 164129198Scognet#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 165129198Scognet#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 166129198Scognet#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 167172734Simp#define CPU_ID_PXA27X 0x69054110 168129198Scognet#define CPU_ID_80321_400 0x69052420 169129198Scognet#define CPU_ID_80321_600 0x69052430 170129198Scognet#define CPU_ID_80321_400_B0 0x69052c20 171129198Scognet#define CPU_ID_80321_600_B0 0x69052c30 172161592Scognet#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 173161592Scognet#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 174164080Scognet#define CPU_ID_81342 0x69056810 175186417Ssam#define CPU_ID_IXP425 0x690541c0 176129198Scognet#define CPU_ID_IXP425_533 0x690541c0 177129198Scognet#define CPU_ID_IXP425_400 0x690541d0 178129198Scognet#define CPU_ID_IXP425_266 0x690541f0 179186352Ssam#define CPU_ID_IXP435 0x69054040 180186417Ssam#define CPU_ID_IXP465 0x69054200 181129198Scognet 182129198Scognet/* ARM3-specific coprocessor 15 registers */ 183129198Scognet#define ARM3_CP15_FLUSH 1 184129198Scognet#define ARM3_CP15_CONTROL 2 185129198Scognet#define ARM3_CP15_CACHEABLE 3 186129198Scognet#define ARM3_CP15_UPDATEABLE 4 187129198Scognet#define ARM3_CP15_DISRUPTIVE 5 188129198Scognet 189129198Scognet/* ARM3 Control register bits */ 190129198Scognet#define ARM3_CTL_CACHE_ON 0x00000001 191129198Scognet#define ARM3_CTL_SHARED 0x00000002 192129198Scognet#define ARM3_CTL_MONITOR 0x00000004 193129198Scognet 194129198Scognet/* 195129198Scognet * Post-ARM3 CP15 registers: 196129198Scognet * 197129198Scognet * 1 Control register 198129198Scognet * 199129198Scognet * 2 Translation Table Base 200129198Scognet * 201129198Scognet * 3 Domain Access Control 202129198Scognet * 203129198Scognet * 4 Reserved 204129198Scognet * 205129198Scognet * 5 Fault Status 206129198Scognet * 207129198Scognet * 6 Fault Address 208129198Scognet * 209129198Scognet * 7 Cache/write-buffer Control 210129198Scognet * 211129198Scognet * 8 TLB Control 212129198Scognet * 213129198Scognet * 9 Cache Lockdown 214129198Scognet * 215129198Scognet * 10 TLB Lockdown 216129198Scognet * 217129198Scognet * 11 Reserved 218129198Scognet * 219129198Scognet * 12 Reserved 220129198Scognet * 221129198Scognet * 13 Process ID (for FCSE) 222129198Scognet * 223129198Scognet * 14 Reserved 224129198Scognet * 225129198Scognet * 15 Implementation Dependent 226129198Scognet */ 227129198Scognet 228129198Scognet/* Some of the definitions below need cleaning up for V3/V4 architectures */ 229129198Scognet 230129198Scognet/* CPU control register (CP15 register 1) */ 231129198Scognet#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 232129198Scognet#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 233129198Scognet#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 234129198Scognet#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 235129198Scognet#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 236129198Scognet#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 237129198Scognet#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 238129198Scognet#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 239129198Scognet#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 240129198Scognet#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 241129198Scognet#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 242129198Scognet#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 243129198Scognet#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 244129198Scognet#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 245129198Scognet#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 246129198Scognet#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 247171630Scognet#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 248129198Scognet 249129198Scognet#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 250129198Scognet 251129198Scognet/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 252129198Scognet#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 253129198Scognet#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 254171630Scognet/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 255129198Scognet#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 256129198Scognet#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 257129198Scognet#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 258129198Scognet#define XSCALE_AUXCTL_MD_MASK 0x00000030 259129198Scognet 260171630Scognet/* Xscale Core 3 only */ 261171630Scognet#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 262171630Scognet 263183835Sraj/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 264183835Sraj#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 265183835Sraj#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 266183835Sraj#define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 267183835Sraj#define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 268183835Sraj#define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 269183835Sraj#define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 270183835Sraj#define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 271183835Sraj#define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 272183835Sraj#define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 273183835Sraj#define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 274183835Sraj 275129198Scognet/* Cache type register definitions */ 276129198Scognet#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 277129198Scognet#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 278129198Scognet#define CPU_CT_S (1U << 24) /* split cache */ 279129198Scognet#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 280129198Scognet 281129198Scognet#define CPU_CT_CTYPE_WT 0 /* write-through */ 282129198Scognet#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 283129198Scognet#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 284129198Scognet#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 285129198Scognet#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 286129198Scognet 287129198Scognet#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 288129198Scognet#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 289129198Scognet#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 290129198Scognet#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 291129198Scognet 292129198Scognet/* Fault status register definitions */ 293129198Scognet 294129198Scognet#define FAULT_TYPE_MASK 0x0f 295129198Scognet#define FAULT_USER 0x10 296129198Scognet 297129198Scognet#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 298129198Scognet#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 299129198Scognet#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 300129198Scognet#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 301129198Scognet#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 302129198Scognet#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 303129198Scognet#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 304129198Scognet#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 305129198Scognet#define FAULT_ALIGN_0 0x01 /* Alignment */ 306129198Scognet#define FAULT_ALIGN_1 0x03 /* Alignment */ 307129198Scognet#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 308129198Scognet#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 309129198Scognet#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 310129198Scognet#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 311129198Scognet#define FAULT_PERM_S 0x0d /* Permission -- Section */ 312129198Scognet#define FAULT_PERM_P 0x0f /* Permission -- Page */ 313129198Scognet 314129198Scognet#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 315129198Scognet 316129198Scognet/* 317129198Scognet * Address of the vector page, low and high versions. 318129198Scognet */ 319129198Scognet#define ARM_VECTORS_LOW 0x00000000U 320234006Sstas#define ARM_VECTORS_HIGH 0xffff0000U 321129198Scognet 322129198Scognet/* 323129198Scognet * ARM Instructions 324129198Scognet * 325129198Scognet * 3 3 2 2 2 326129198Scognet * 1 0 9 8 7 0 327129198Scognet * +-------+-------------------------------------------------------+ 328129198Scognet * | cond | instruction dependant | 329129198Scognet * |c c c c| | 330129198Scognet * +-------+-------------------------------------------------------+ 331129198Scognet */ 332129198Scognet 333129198Scognet#define INSN_SIZE 4 /* Always 4 bytes */ 334129198Scognet#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 335129198Scognet#define INSN_COND_AL 0xe0000000 /* Always condition */ 336129198Scognet 337172734Simp#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 338172734Simp 339129198Scognet#endif /* !MACHINE_ARMREG_H */ 340