1172734Simp/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1998, 2001 Ben Harris 5129198Scognet * Copyright (c) 1994-1996 Mark Brinicombe. 6129198Scognet * Copyright (c) 1994 Brini. 7129198Scognet * All rights reserved. 8129198Scognet * 9129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 10129198Scognet * 11129198Scognet * Redistribution and use in source and binary forms, with or without 12129198Scognet * modification, are permitted provided that the following conditions 13129198Scognet * are met: 14129198Scognet * 1. Redistributions of source code must retain the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer. 16129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 17129198Scognet * notice, this list of conditions and the following disclaimer in the 18129198Scognet * documentation and/or other materials provided with the distribution. 19129198Scognet * 3. All advertising materials mentioning features or use of this software 20129198Scognet * must display the following acknowledgement: 21129198Scognet * This product includes software developed by Brini. 22129198Scognet * 4. The name of the company nor the name of the author may be used to 23129198Scognet * endorse or promote products derived from this software without specific 24129198Scognet * prior written permission. 25129198Scognet * 26129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36129198Scognet * SUCH DAMAGE. 37129198Scognet * 38129198Scognet * $FreeBSD: stable/11/sys/arm/include/armreg.h 317002 2017-04-16 06:35:09Z mmel $ 39129198Scognet */ 40129198Scognet 41129198Scognet#ifndef MACHINE_ARMREG_H 42129198Scognet#define MACHINE_ARMREG_H 43172734Simp 44129198Scognet#define INSN_SIZE 4 45129198Scognet#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46129198Scognet#define PSR_MODE 0x0000001f /* mode mask */ 47129198Scognet#define PSR_USR32_MODE 0x00000010 48129198Scognet#define PSR_FIQ32_MODE 0x00000011 49129198Scognet#define PSR_IRQ32_MODE 0x00000012 50129198Scognet#define PSR_SVC32_MODE 0x00000013 51271394Sandrew#define PSR_MON32_MODE 0x00000016 52129198Scognet#define PSR_ABT32_MODE 0x00000017 53271394Sandrew#define PSR_HYP32_MODE 0x0000001a 54129198Scognet#define PSR_UND32_MODE 0x0000001b 55129198Scognet#define PSR_SYS32_MODE 0x0000001f 56129198Scognet#define PSR_32_MODE 0x00000010 57271394Sandrew#define PSR_T 0x00000020 /* Instruction set bit */ 58271394Sandrew#define PSR_F 0x00000040 /* FIQ disable bit */ 59271394Sandrew#define PSR_I 0x00000080 /* IRQ disable bit */ 60271394Sandrew#define PSR_A 0x00000100 /* Imprecise abort bit */ 61271394Sandrew#define PSR_E 0x00000200 /* Data endianess bit */ 62271394Sandrew#define PSR_GE 0x000f0000 /* Greater than or equal to bits */ 63271394Sandrew#define PSR_J 0x01000000 /* Java bit */ 64271394Sandrew#define PSR_Q 0x08000000 /* Sticky overflow bit */ 65271394Sandrew#define PSR_V 0x10000000 /* Overflow bit */ 66271394Sandrew#define PSR_C 0x20000000 /* Carry bit */ 67271394Sandrew#define PSR_Z 0x40000000 /* Zero bit */ 68271394Sandrew#define PSR_N 0x80000000 /* Negative bit */ 69271394Sandrew#define PSR_FLAGS 0xf0000000 /* Flags mask. */ 70129198Scognet 71129198Scognet/* The high-order byte is always the implementor */ 72129198Scognet#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 73129198Scognet#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 74129198Scognet#define CPU_ID_DEC 0x44000000 /* 'D' */ 75301561Sandrew#define CPU_ID_MOTOROLA 0x4D000000 /* 'M' */ 76301561Sandrew#define CPU_ID_QUALCOM 0x51000000 /* 'Q' */ 77129198Scognet#define CPU_ID_TI 0x54000000 /* 'T' */ 78301561Sandrew#define CPU_ID_MARVELL 0x56000000 /* 'V' */ 79301561Sandrew#define CPU_ID_INTEL 0x69000000 /* 'i' */ 80172734Simp#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 81129198Scognet 82301561Sandrew#define CPU_ID_VARIANT_SHIFT 20 83301561Sandrew#define CPU_ID_VARIANT_MASK 0x00f00000 84301561Sandrew 85129198Scognet/* How to decide what format the CPUID is in. */ 86129198Scognet#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 87129198Scognet#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 88129198Scognet#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 89129198Scognet 90262958Sian/* On recent ARMs this byte holds the architecture and variant (sub-model) */ 91129198Scognet#define CPU_ID_ARCH_MASK 0x000f0000 92129198Scognet#define CPU_ID_ARCH_V3 0x00000000 93129198Scognet#define CPU_ID_ARCH_V4 0x00010000 94129198Scognet#define CPU_ID_ARCH_V4T 0x00020000 95129198Scognet#define CPU_ID_ARCH_V5 0x00030000 96129198Scognet#define CPU_ID_ARCH_V5T 0x00040000 97129198Scognet#define CPU_ID_ARCH_V5TE 0x00050000 98172734Simp#define CPU_ID_ARCH_V5TEJ 0x00060000 99172734Simp#define CPU_ID_ARCH_V6 0x00070000 100239268Sgonzo#define CPU_ID_CPUID_SCHEME 0x000f0000 101129198Scognet 102129198Scognet/* Next three nybbles are part number */ 103129198Scognet#define CPU_ID_PARTNO_MASK 0x0000fff0 104129198Scognet 105129198Scognet/* Intel XScale has sub fields in part number */ 106129198Scognet#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 107129198Scognet#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 108129198Scognet#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 109129198Scognet 110129198Scognet/* And finally, the revision number. */ 111129198Scognet#define CPU_ID_REVISION_MASK 0x0000000f 112129198Scognet 113129198Scognet/* Individual CPUs are probably best IDed by everything but the revision. */ 114129198Scognet#define CPU_ID_CPU_MASK 0xfffffff0 115129198Scognet 116262958Sian/* ARM9 and later CPUs */ 117129198Scognet#define CPU_ID_ARM920T 0x41129200 118152653Scognet#define CPU_ID_ARM920T_ALT 0x41009200 119129198Scognet#define CPU_ID_ARM922T 0x41029220 120172734Simp#define CPU_ID_ARM926EJS 0x41069260 121129198Scognet#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 122129198Scognet#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 123129198Scognet#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 124129198Scognet#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 125129198Scognet#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 126129198Scognet#define CPU_ID_ARM1022ES 0x4105a220 127172734Simp#define CPU_ID_ARM1026EJS 0x4106a260 128172734Simp#define CPU_ID_ARM1136JS 0x4107b360 129172734Simp#define CPU_ID_ARM1136JSR1 0x4117b360 130244480Sgonzo#define CPU_ID_ARM1176JZS 0x410fb760 131291425Smmel 132301561Sandrew/* CPUs that follow the CPUID scheme */ 133301561Sandrew#define CPU_ID_SCHEME_MASK \ 134301561Sandrew (CPU_ID_IMPLEMENTOR_MASK | CPU_ID_ARCH_MASK | CPU_ID_PARTNO_MASK) 135301561Sandrew 136301561Sandrew#define CPU_ID_CORTEXA5 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc050) 137301561Sandrew#define CPU_ID_CORTEXA7 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc070) 138301561Sandrew#define CPU_ID_CORTEXA8 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc080) 139301561Sandrew#define CPU_ID_CORTEXA8R1 (CPU_ID_CORTEXA8 | (1 << CPU_ID_VARIANT_SHIFT)) 140301561Sandrew#define CPU_ID_CORTEXA8R2 (CPU_ID_CORTEXA8 | (2 << CPU_ID_VARIANT_SHIFT)) 141301561Sandrew#define CPU_ID_CORTEXA8R3 (CPU_ID_CORTEXA8 | (3 << CPU_ID_VARIANT_SHIFT)) 142301561Sandrew#define CPU_ID_CORTEXA9 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc090) 143301561Sandrew#define CPU_ID_CORTEXA9R1 (CPU_ID_CORTEXA9 | (1 << CPU_ID_VARIANT_SHIFT)) 144301561Sandrew#define CPU_ID_CORTEXA9R2 (CPU_ID_CORTEXA9 | (2 << CPU_ID_VARIANT_SHIFT)) 145301561Sandrew#define CPU_ID_CORTEXA9R3 (CPU_ID_CORTEXA9 | (3 << CPU_ID_VARIANT_SHIFT)) 146301561Sandrew#define CPU_ID_CORTEXA9R4 (CPU_ID_CORTEXA9 | (4 << CPU_ID_VARIANT_SHIFT)) 147301561Sandrew/* XXX: Cortx-A12 is the old name for this part, it has been renamed the A17 */ 148301561Sandrew#define CPU_ID_CORTEXA12 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0d0) 149301561Sandrew#define CPU_ID_CORTEXA12R0 (CPU_ID_CORTEXA12 | (0 << CPU_ID_VARIANT_SHIFT)) 150301561Sandrew#define CPU_ID_CORTEXA15 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0f0) 151301561Sandrew#define CPU_ID_CORTEXA15R0 (CPU_ID_CORTEXA15 | (0 << CPU_ID_VARIANT_SHIFT)) 152301561Sandrew#define CPU_ID_CORTEXA15R1 (CPU_ID_CORTEXA15 | (1 << CPU_ID_VARIANT_SHIFT)) 153301561Sandrew#define CPU_ID_CORTEXA15R2 (CPU_ID_CORTEXA15 | (2 << CPU_ID_VARIANT_SHIFT)) 154301561Sandrew#define CPU_ID_CORTEXA15R3 (CPU_ID_CORTEXA15 | (3 << CPU_ID_VARIANT_SHIFT)) 155317002Smmel#define CPU_ID_CORTEXA53 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd030) 156317002Smmel#define CPU_ID_CORTEXA57 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd070) 157317002Smmel#define CPU_ID_CORTEXA72 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd080) 158301561Sandrew 159301561Sandrew#define CPU_ID_KRAIT300 (CPU_ID_QUALCOM | CPU_ID_CPUID_SCHEME | 0x06f0) 160301561Sandrew/* Snapdragon S4 Pro/APQ8064 */ 161301561Sandrew#define CPU_ID_KRAIT300R0 (CPU_ID_KRAIT300 | (0 << CPU_ID_VARIANT_SHIFT)) 162301561Sandrew#define CPU_ID_KRAIT300R1 (CPU_ID_KRAIT300 | (1 << CPU_ID_VARIANT_SHIFT)) 163301561Sandrew 164129198Scognet#define CPU_ID_TI925T 0x54029250 165183835Sraj#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 166239268Sgonzo#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 167183835Sraj#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 168239268Sgonzo 169239268Sgonzo/* 170239268Sgonzo * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 171239268Sgonzo * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 172239268Sgonzo */ 173239268Sgonzo#ifdef SOC_MV_LOKIPLUS 174239268Sgonzo#define CPU_ID_MV88FR571_41 0x00000000 175239268Sgonzo#else 176239268Sgonzo#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 177239268Sgonzo#endif 178239268Sgonzo 179239268Sgonzo#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 180240486Sgber#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 181239268Sgonzo/* Marvell's CPUIDs with ARM ID in implementor field */ 182239268Sgonzo#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 183239268Sgonzo 184204121Skevlo#define CPU_ID_FA526 0x66015260 185204121Skevlo#define CPU_ID_FA626TE 0x66056260 186129198Scognet#define CPU_ID_80200 0x69052000 187129198Scognet#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 188129198Scognet#define CPU_ID_PXA210 0x69052120 189129198Scognet#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 190129198Scognet#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 191129198Scognet#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 192129198Scognet#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 193129198Scognet#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 194129198Scognet#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 195172734Simp#define CPU_ID_PXA27X 0x69054110 196129198Scognet#define CPU_ID_80321_400 0x69052420 197129198Scognet#define CPU_ID_80321_600 0x69052430 198129198Scognet#define CPU_ID_80321_400_B0 0x69052c20 199129198Scognet#define CPU_ID_80321_600_B0 0x69052c30 200161592Scognet#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 201161592Scognet#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 202164080Scognet#define CPU_ID_81342 0x69056810 203186417Ssam#define CPU_ID_IXP425 0x690541c0 204129198Scognet#define CPU_ID_IXP425_533 0x690541c0 205129198Scognet#define CPU_ID_IXP425_400 0x690541d0 206129198Scognet#define CPU_ID_IXP425_266 0x690541f0 207186352Ssam#define CPU_ID_IXP435 0x69054040 208186417Ssam#define CPU_ID_IXP465 0x69054200 209129198Scognet 210239268Sgonzo/* CPUID registers */ 211239268Sgonzo#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 212239268Sgonzo 213239268Sgonzo#define ARM_PFR0_THUMB_MASK 0x000000f0 214239268Sgonzo#define ARM_PFR0_THUMB 0x10 215239268Sgonzo#define ARM_PFR0_THUMB2 0x30 216239268Sgonzo 217239268Sgonzo#define ARM_PFR0_JAZELLE_MASK 0x00000f00 218239268Sgonzo#define ARM_PFR0_THUMBEE_MASK 0x0000f000 219239268Sgonzo 220239268Sgonzo#define ARM_PFR1_ARMV4_MASK 0x0000000f 221239268Sgonzo#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 222239268Sgonzo#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 223239268Sgonzo 224129198Scognet/* 225129198Scognet * Post-ARM3 CP15 registers: 226129198Scognet * 227129198Scognet * 1 Control register 228129198Scognet * 229129198Scognet * 2 Translation Table Base 230129198Scognet * 231129198Scognet * 3 Domain Access Control 232129198Scognet * 233129198Scognet * 4 Reserved 234129198Scognet * 235129198Scognet * 5 Fault Status 236129198Scognet * 237129198Scognet * 6 Fault Address 238129198Scognet * 239129198Scognet * 7 Cache/write-buffer Control 240129198Scognet * 241129198Scognet * 8 TLB Control 242129198Scognet * 243129198Scognet * 9 Cache Lockdown 244129198Scognet * 245129198Scognet * 10 TLB Lockdown 246129198Scognet * 247129198Scognet * 11 Reserved 248129198Scognet * 249129198Scognet * 12 Reserved 250129198Scognet * 251129198Scognet * 13 Process ID (for FCSE) 252129198Scognet * 253129198Scognet * 14 Reserved 254129198Scognet * 255129198Scognet * 15 Implementation Dependent 256129198Scognet */ 257129198Scognet 258129198Scognet/* Some of the definitions below need cleaning up for V3/V4 architectures */ 259129198Scognet 260129198Scognet/* CPU control register (CP15 register 1) */ 261129198Scognet#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 262129198Scognet#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 263129198Scognet#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 264129198Scognet#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 265129198Scognet#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 266129198Scognet#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 267129198Scognet#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 268129198Scognet#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 269129198Scognet#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 270129198Scognet#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 271129198Scognet#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 272271394Sandrew#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ 273129198Scognet#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 274129198Scognet#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 275129198Scognet#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 276129198Scognet#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 277129198Scognet#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 278271394Sandrew#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ 279244480Sgonzo#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 280244480Sgonzo#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 281239268Sgonzo#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 282271394Sandrew#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 283271394Sandrew#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 284171630Scognet#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 285271394Sandrew#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 286271394Sandrew#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ 287271394Sandrew#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ 288271394Sandrew#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 289129198Scognet 290129198Scognet#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 291129198Scognet 292244480Sgonzo/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 293244480Sgonzo#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 294244480Sgonzo#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 295244480Sgonzo#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 296244480Sgonzo#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 297244480Sgonzo#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 298244480Sgonzo#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 299244480Sgonzo#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 300244480Sgonzo#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 301244480Sgonzo 302244480Sgonzo/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 303244480Sgonzo#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 304244480Sgonzo /* This is an undocumented flag 305244480Sgonzo * used to work around a cache bug 306244480Sgonzo * in r0 steppings. See errata 307244480Sgonzo * 364296. 308244480Sgonzo */ 309290648Smmel/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 310244480Sgonzo#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 311244480Sgonzo#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 312244480Sgonzo#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 313244480Sgonzo#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 314244480Sgonzo 315129198Scognet/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 316129198Scognet#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 317129198Scognet#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 318171630Scognet/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 319129198Scognet#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 320129198Scognet#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 321129198Scognet#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 322129198Scognet#define XSCALE_AUXCTL_MD_MASK 0x00000030 323129198Scognet 324171630Scognet/* Xscale Core 3 only */ 325171630Scognet#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 326171630Scognet 327239268Sgonzo/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 328239268Sgonzo#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 329239268Sgonzo#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 330239268Sgonzo#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 331239268Sgonzo#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 332239268Sgonzo#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 333239268Sgonzo#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 334239268Sgonzo#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 335239268Sgonzo#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 336239268Sgonzo#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 337239268Sgonzo#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 338183835Sraj 339129198Scognet/* Cache type register definitions */ 340129198Scognet#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 341129198Scognet#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 342129198Scognet#define CPU_CT_S (1U << 24) /* split cache */ 343129198Scognet#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 344239268Sgonzo#define CPU_CT_FORMAT(x) ((x) >> 29) 345278518Szbb/* Cache type register definitions for ARM v7 */ 346278518Szbb#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ 347278518Szbb#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ 348129198Scognet 349129198Scognet#define CPU_CT_CTYPE_WT 0 /* write-through */ 350129198Scognet#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 351129198Scognet#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 352129198Scognet#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 353129198Scognet#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 354129198Scognet 355129198Scognet#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 356129198Scognet#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 357129198Scognet#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 358129198Scognet#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 359129198Scognet 360239268Sgonzo#define CPU_CT_ARMV7 0x4 361239268Sgonzo/* ARM v7 Cache type definitions */ 362258780Seadler#define CPUV7_CT_CTYPE_WT (1U << 31) 363239268Sgonzo#define CPUV7_CT_CTYPE_WB (1 << 30) 364239268Sgonzo#define CPUV7_CT_CTYPE_RA (1 << 29) 365239268Sgonzo#define CPUV7_CT_CTYPE_WA (1 << 28) 366239268Sgonzo 367239268Sgonzo#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 368239268Sgonzo#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 369239268Sgonzo#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 370239268Sgonzo 371282547Szbb#define CPUV7_L2CTLR_NPROC_SHIFT 24 372282547Szbb#define CPUV7_L2CTLR_NPROC(r) ((((r) >> CPUV7_L2CTLR_NPROC_SHIFT) & 3) + 1) 373282547Szbb 374239268Sgonzo#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 375239268Sgonzo#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 376239268Sgonzo#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 377239268Sgonzo#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 378239268Sgonzo 379239268Sgonzo#define CACHE_ICACHE 1 380239268Sgonzo#define CACHE_DCACHE 2 381239268Sgonzo#define CACHE_SEP_CACHE 3 382239268Sgonzo#define CACHE_UNI_CACHE 4 383239268Sgonzo 384129198Scognet/* Fault status register definitions */ 385276638Sian#define FAULT_USER 0x10 386129198Scognet 387276638Sian#if __ARM_ARCH < 6 388129198Scognet#define FAULT_TYPE_MASK 0x0f 389129198Scognet#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 390129198Scognet#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 391129198Scognet#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 392129198Scognet#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 393129198Scognet#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 394129198Scognet#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 395129198Scognet#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 396129198Scognet#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 397129198Scognet#define FAULT_ALIGN_0 0x01 /* Alignment */ 398129198Scognet#define FAULT_ALIGN_1 0x03 /* Alignment */ 399129198Scognet#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 400250928Sgber#define FAULT_TRANS_F 0x06 /* Translation -- Flag */ 401129198Scognet#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 402129198Scognet#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 403129198Scognet#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 404129198Scognet#define FAULT_PERM_S 0x0d /* Permission -- Section */ 405129198Scognet#define FAULT_PERM_P 0x0f /* Permission -- Page */ 406129198Scognet 407129198Scognet#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 408261808Sian#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ 409261808Sian#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ 410129198Scognet 411276638Sian#else /* __ARM_ARCH < 6 */ 412271394Sandrew 413276638Sian#define FAULT_ALIGN 0x001 /* Alignment Fault */ 414276638Sian#define FAULT_DEBUG 0x002 /* Debug Event */ 415276638Sian#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ 416276638Sian#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ 417276638Sian#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ 418276638Sian#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ 419276638Sian#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ 420276638Sian#define FAULT_EA_PREC 0x008 /* External Abort */ 421276638Sian#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ 422276638Sian#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ 423276638Sian#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ 424276638Sian#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ 425276638Sian#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ 426276638Sian#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ 427290369Sskra#define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */ 428276638Sian#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ 429276638Sian#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ 430276638Sian#define FAULT_PARITY 0x019 /* Parity Error */ 431276638Sian#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ 432276638Sian#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ 433271394Sandrew 434276638Sian#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ 435276638Sian ((((fsr) & (1 << 10)) >> (10 - 4)))) 436276638Sian#define FSR_LPAE (1 << 9) /* LPAE indicator */ 437276638Sian#define FSR_WNR (1 << 11) /* Write-not-Read access */ 438276638Sian#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ 439276638Sian#define FSR_CM (1 << 13) /* Cache maintenance fault */ 440276638Sian#endif /* !__ARM_ARCH < 6 */ 441276638Sian 442129198Scognet/* 443129198Scognet * Address of the vector page, low and high versions. 444129198Scognet */ 445234337Sandrew#ifndef __ASSEMBLER__ 446129198Scognet#define ARM_VECTORS_LOW 0x00000000U 447234006Sstas#define ARM_VECTORS_HIGH 0xffff0000U 448234337Sandrew#else 449234337Sandrew#define ARM_VECTORS_LOW 0 450234337Sandrew#define ARM_VECTORS_HIGH 0xffff0000 451234337Sandrew#endif 452129198Scognet 453129198Scognet/* 454129198Scognet * ARM Instructions 455129198Scognet * 456236992Simp * 3 3 2 2 2 457129198Scognet * 1 0 9 8 7 0 458129198Scognet * +-------+-------------------------------------------------------+ 459129198Scognet * | cond | instruction dependant | 460129198Scognet * |c c c c| | 461129198Scognet * +-------+-------------------------------------------------------+ 462129198Scognet */ 463129198Scognet 464129198Scognet#define INSN_SIZE 4 /* Always 4 bytes */ 465129198Scognet#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 466129198Scognet#define INSN_COND_AL 0xe0000000 /* Always condition */ 467129198Scognet 468290273Szbb/* ARM register defines */ 469290273Szbb#define ARM_REG_SIZE 4 470290273Szbb#define ARM_REG_NUM_PC 15 471290273Szbb#define ARM_REG_NUM_LR 14 472290273Szbb#define ARM_REG_NUM_SP 13 473290273Szbb 474172734Simp#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 475172734Simp 476129198Scognet#endif /* !MACHINE_ARMREG_H */ 477