pmap-v4.c revision 283366
1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 81129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 82129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 83129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 84129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 85129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 86129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 87129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 88129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 89129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 90129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 91129198Scognet * POSSIBILITY OF SUCH DAMAGE. 92129198Scognet */ 93129198Scognet 94139735Simp/*- 95129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 96129198Scognet * Copyright (c) 1994 Brini. 97129198Scognet * All rights reserved. 98139735Simp * 99129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 100129198Scognet * 101129198Scognet * Redistribution and use in source and binary forms, with or without 102129198Scognet * modification, are permitted provided that the following conditions 103129198Scognet * are met: 104129198Scognet * 1. Redistributions of source code must retain the above copyright 105129198Scognet * notice, this list of conditions and the following disclaimer. 106129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 107129198Scognet * notice, this list of conditions and the following disclaimer in the 108129198Scognet * documentation and/or other materials provided with the distribution. 109129198Scognet * 3. All advertising materials mentioning features or use of this software 110129198Scognet * must display the following acknowledgement: 111129198Scognet * This product includes software developed by Mark Brinicombe. 112129198Scognet * 4. The name of the author may not be used to endorse or promote products 113129198Scognet * derived from this software without specific prior written permission. 114129198Scognet * 115129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 116129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 117129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 118129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 119129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 120129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 121129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 122129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 123129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 124129198Scognet * 125129198Scognet * RiscBSD kernel project 126129198Scognet * 127129198Scognet * pmap.c 128129198Scognet * 129129198Scognet * Machine dependant vm stuff 130129198Scognet * 131129198Scognet * Created : 20/09/94 132129198Scognet */ 133129198Scognet 134129198Scognet/* 135129198Scognet * Special compilation symbols 136129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 137257648Sian * 138257648Sian * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c 139129198Scognet */ 140129198Scognet/* Include header files */ 141135641Scognet 142137552Scognet#include "opt_vm.h" 143137552Scognet 144129198Scognet#include <sys/cdefs.h> 145129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 283366 2015-05-24 12:20:11Z andrew $"); 146129198Scognet#include <sys/param.h> 147129198Scognet#include <sys/systm.h> 148129198Scognet#include <sys/kernel.h> 149183838Sraj#include <sys/ktr.h> 150240983Salc#include <sys/lock.h> 151129198Scognet#include <sys/proc.h> 152129198Scognet#include <sys/malloc.h> 153129198Scognet#include <sys/msgbuf.h> 154240983Salc#include <sys/mutex.h> 155129198Scognet#include <sys/vmmeter.h> 156129198Scognet#include <sys/mman.h> 157239934Salc#include <sys/rwlock.h> 158129198Scognet#include <sys/smp.h> 159129198Scognet#include <sys/sched.h> 160129198Scognet 161129198Scognet#include <vm/vm.h> 162239065Skib#include <vm/vm_param.h> 163129198Scognet#include <vm/uma.h> 164129198Scognet#include <vm/pmap.h> 165129198Scognet#include <vm/vm_kern.h> 166129198Scognet#include <vm/vm_object.h> 167129198Scognet#include <vm/vm_map.h> 168129198Scognet#include <vm/vm_page.h> 169129198Scognet#include <vm/vm_pageout.h> 170243132Skib#include <vm/vm_phys.h> 171129198Scognet#include <vm/vm_extern.h> 172240983Salc 173129198Scognet#include <machine/md_var.h> 174129198Scognet#include <machine/cpu.h> 175129198Scognet#include <machine/cpufunc.h> 176129198Scognet#include <machine/pcb.h> 177129198Scognet 178129198Scognet#ifdef PMAP_DEBUG 179129198Scognet#define PDEBUG(_lev_,_stat_) \ 180129198Scognet if (pmap_debug_level >= (_lev_)) \ 181129198Scognet ((_stat_)) 182129198Scognet#define dprintf printf 183129198Scognet 184129198Scognetint pmap_debug_level = 0; 185236991Simp#define PMAP_INLINE 186129198Scognet#else /* PMAP_DEBUG */ 187129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 188129198Scognet#define dprintf(x, arg...) 189135641Scognet#define PMAP_INLINE __inline 190129198Scognet#endif /* PMAP_DEBUG */ 191129198Scognet 192129198Scognetextern struct pv_addr systempage; 193225988Smarcel 194225988Smarcelextern int last_fault_code; 195225988Smarcel 196129198Scognet/* 197129198Scognet * Internal function prototypes 198129198Scognet */ 199135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 200129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 201129198Scognet 202269728Skibstatic int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 203269728Skib vm_prot_t, u_int); 204240983Salcstatic vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va); 205194459Sthompsastatic void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t); 206129198Scognetstatic void pmap_alloc_l1(pmap_t); 207129198Scognetstatic void pmap_free_l1(pmap_t); 208129198Scognet 209135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 210129198Scognet 211129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 212129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 213129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 214129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 215129198Scognet 216129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 217129198Scognet 218129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 219129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 220135641Scognetvm_offset_t pmap_curmaxkvaddr; 221150865Scognetvm_paddr_t kernel_l1pa; 222129198Scognet 223129198Scognetvm_offset_t kernel_vm_end = 0; 224129198Scognet 225246926Salcvm_offset_t vm_max_kernel_address; 226246926Salc 227129198Scognetstruct pmap kernel_pmap_store; 228129198Scognet 229129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 230129198Scognetstatic vm_offset_t csrcp, cdstp; 231159088Scognetstatic struct mtx cmtx; 232159088Scognet 233129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 234129198Scognet/* 235129198Scognet * These routines are called when the CPU type is identified to set up 236129198Scognet * the PTE prototypes, cache modes, etc. 237129198Scognet * 238129198Scognet * The variables are always here, just in case LKMs need to reference 239129198Scognet * them (though, they shouldn't). 240129198Scognet */ 241129198Scognet 242129198Scognetpt_entry_t pte_l1_s_cache_mode; 243129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 244129198Scognetpt_entry_t pte_l1_s_cache_mask; 245129198Scognet 246129198Scognetpt_entry_t pte_l2_l_cache_mode; 247129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 248129198Scognetpt_entry_t pte_l2_l_cache_mask; 249129198Scognet 250129198Scognetpt_entry_t pte_l2_s_cache_mode; 251129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 252129198Scognetpt_entry_t pte_l2_s_cache_mask; 253129198Scognet 254129198Scognetpt_entry_t pte_l2_s_prot_u; 255129198Scognetpt_entry_t pte_l2_s_prot_w; 256129198Scognetpt_entry_t pte_l2_s_prot_mask; 257129198Scognet 258129198Scognetpt_entry_t pte_l1_s_proto; 259129198Scognetpt_entry_t pte_l1_c_proto; 260129198Scognetpt_entry_t pte_l2_s_proto; 261129198Scognet 262129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 263248280Skibvoid (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 264248280Skib vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, 265248280Skib int cnt); 266129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 267129198Scognet 268129198Scognetstruct msgbuf *msgbufp = 0; 269129198Scognet 270184728Sraj/* 271184728Sraj * Crashdump maps. 272184728Sraj */ 273184728Srajstatic caddr_t crashdumpmap; 274184728Sraj 275129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 276129198Scognetextern void bzero_page(vm_offset_t); 277137362Scognet 278164079Scognetextern vm_offset_t alloc_firstaddr; 279164079Scognet 280137362Scognetchar *_tmppt; 281137362Scognet 282129198Scognet/* 283129198Scognet * Metadata for L1 translation tables. 284129198Scognet */ 285129198Scognetstruct l1_ttable { 286129198Scognet /* Entry on the L1 Table list */ 287129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 288129198Scognet 289129198Scognet /* Entry on the L1 Least Recently Used list */ 290129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 291129198Scognet 292129198Scognet /* Track how many domains are allocated from this L1 */ 293129198Scognet volatile u_int l1_domain_use_count; 294129198Scognet 295129198Scognet /* 296129198Scognet * A free-list of domain numbers for this L1. 297129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 298129198Scognet * is slow on ARM. 299129198Scognet */ 300129198Scognet u_int8_t l1_domain_first; 301129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 302129198Scognet 303129198Scognet /* Physical address of this L1 page table */ 304129198Scognet vm_paddr_t l1_physaddr; 305129198Scognet 306129198Scognet /* KVA of this L1 page table */ 307129198Scognet pd_entry_t *l1_kva; 308129198Scognet}; 309129198Scognet 310129198Scognet/* 311129198Scognet * Convert a virtual address into its L1 table index. That is, the 312129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 313129198Scognet * This is basically used to index l1->l1_kva[]. 314129198Scognet * 315129198Scognet * Each L2 descriptor table represents 1MB of VA space. 316129198Scognet */ 317129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 318129198Scognet 319129198Scognet/* 320129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 321129198Scognet * - New L1s are allocated from the HEAD. 322129198Scognet * - Freed L1s are added to the TAIl. 323129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 324129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 325129198Scognet */ 326129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 327135641Scognet/* 328135641Scognet * A list of all L1 tables 329135641Scognet */ 330135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 331129198Scognetstatic struct mtx l1_lru_lock; 332129198Scognet 333129198Scognet/* 334129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 335129198Scognet * 336129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 337129198Scognet * Reference counts are maintained for L2 descriptors so they can be 338129198Scognet * freed when empty. 339129198Scognet */ 340129198Scognetstruct l2_dtable { 341129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 342129198Scognet u_int l2_occupancy; 343129198Scognet 344129198Scognet /* List of L2 page descriptors */ 345129198Scognet struct l2_bucket { 346129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 347129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 348129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 349129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 350129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 351129198Scognet}; 352129198Scognet 353135641Scognet/* pmap_kenter_internal flags */ 354135641Scognet#define KENTER_CACHE 0x1 355142570Scognet#define KENTER_USER 0x2 356135641Scognet 357129198Scognet/* 358129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 359129198Scognet * and bucket index within the l2_dtable. 360129198Scognet */ 361129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 362129198Scognet (L2_SIZE - 1)) 363129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 364129198Scognet 365129198Scognet/* 366129198Scognet * Given a virtual address, this macro returns the 367129198Scognet * virtual address required to drop into the next L2 bucket. 368129198Scognet */ 369129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 370129198Scognet 371129198Scognet/* 372129198Scognet * We try to map the page tables write-through, if possible. However, not 373129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 374129198Scognet * the cache when we frob page tables. 375129198Scognet * 376129198Scognet * We try to evaluate this at compile time, if possible. However, it's 377129198Scognet * not always possible to do that, hence this run-time var. 378129198Scognet */ 379129198Scognetint pmap_needs_pte_sync; 380129198Scognet 381129198Scognet/* 382129198Scognet * Macro to determine if a mapping might be resident in the 383129198Scognet * instruction cache and/or TLB 384129198Scognet */ 385129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 386129198Scognet 387129198Scognet/* 388129198Scognet * Macro to determine if a mapping might be resident in the 389129198Scognet * data cache and/or TLB 390129198Scognet */ 391129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 392129198Scognet 393129198Scognet#ifndef PMAP_SHPGPERPROC 394129198Scognet#define PMAP_SHPGPERPROC 200 395129198Scognet#endif 396129198Scognet 397135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 398135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 399194459Sthompsastatic uma_zone_t pvzone = NULL; 400147114Scognetuma_zone_t l2zone; 401129198Scognetstatic uma_zone_t l2table_zone; 402135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 403135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 404135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 405129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 406239934Salcstatic struct rwlock pvh_global_lock; 407129198Scognet 408248280Skibvoid pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs, 409248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 410248280Skib#if ARM_MMU_XSCALE == 1 411248280Skibvoid pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs, 412248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 413248280Skib#endif 414248280Skib 415129198Scognet/* 416129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 417129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 418129198Scognet * find them as necessary. 419129198Scognet * 420129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 421129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 422129198Scognet */ 423129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 424129198Scognet 425129198Scognetstatic void 426129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 427129198Scognet{ 428129198Scognet int i; 429129198Scognet 430129198Scognet l1->l1_kva = l1pt; 431129198Scognet l1->l1_domain_use_count = 0; 432174181Scognet l1->l1_domain_first = 0; 433129198Scognet 434129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 435174181Scognet l1->l1_domain_free[i] = i + 1; 436129198Scognet 437129198Scognet /* 438129198Scognet * Copy the kernel's L1 entries to each new L1. 439129198Scognet */ 440147249Scognet if (l1pt != pmap_kernel()->pm_l1->l1_kva) 441129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 442129198Scognet 443129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 444129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 445135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 446129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 447129198Scognet} 448129198Scognet 449129198Scognetstatic vm_offset_t 450129198Scognetkernel_pt_lookup(vm_paddr_t pa) 451129198Scognet{ 452129198Scognet struct pv_addr *pv; 453129198Scognet 454129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 455129198Scognet if (pv->pv_pa == pa) 456129198Scognet return (pv->pv_va); 457129198Scognet } 458129198Scognet return (0); 459129198Scognet} 460129198Scognet 461262958Sian#if ARM_MMU_GENERIC != 0 462129198Scognetvoid 463129198Scognetpmap_pte_init_generic(void) 464129198Scognet{ 465129198Scognet 466129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 467129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 468129198Scognet 469129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 470129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 471129198Scognet 472129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 473129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 474129198Scognet 475129198Scognet /* 476129198Scognet * If we have a write-through cache, set B and C. If 477129198Scognet * we have a write-back cache, then we assume setting 478129198Scognet * only C will make those pages write-through. 479129198Scognet */ 480129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 481129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 482129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 483129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 484129198Scognet } else { 485129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 486129198Scognet pte_l2_l_cache_mode_pt = L2_C; 487129198Scognet pte_l2_s_cache_mode_pt = L2_C; 488129198Scognet } 489129198Scognet 490129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 491129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 492129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 493129198Scognet 494129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 495129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 496129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 497129198Scognet 498129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 499248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_generic; 500129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 501129198Scognet} 502129198Scognet 503262958Sian#endif /* ARM_MMU_GENERIC != 0 */ 504129198Scognet 505129198Scognet#if ARM_MMU_XSCALE == 1 506164778Scognet#if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) 507129198Scognetstatic u_int xscale_use_minidata; 508129198Scognet#endif 509129198Scognet 510129198Scognetvoid 511129198Scognetpmap_pte_init_xscale(void) 512129198Scognet{ 513129198Scognet uint32_t auxctl; 514129198Scognet int write_through = 0; 515129198Scognet 516135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 517129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 518129198Scognet 519129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 520129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 521129198Scognet 522129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 523129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 524129198Scognet 525129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 526129198Scognet pte_l2_l_cache_mode_pt = L2_C; 527129198Scognet pte_l2_s_cache_mode_pt = L2_C; 528129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 529129198Scognet /* 530129198Scognet * The XScale core has an enhanced mode where writes that 531129198Scognet * miss the cache cause a cache line to be allocated. This 532129198Scognet * is significantly faster than the traditional, write-through 533129198Scognet * behavior of this case. 534129198Scognet */ 535129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 536129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 537129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 538129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 539129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 540129198Scognet /* 541129198Scognet * Some versions of the XScale core have various bugs in 542129198Scognet * their cache units, the work-around for which is to run 543129198Scognet * the cache in write-through mode. Unfortunately, this 544129198Scognet * has a major (negative) impact on performance. So, we 545129198Scognet * go ahead and run fast-and-loose, in the hopes that we 546129198Scognet * don't line up the planets in a way that will trip the 547129198Scognet * bugs. 548129198Scognet * 549129198Scognet * However, we give you the option to be slow-but-correct. 550129198Scognet */ 551129198Scognet write_through = 1; 552129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 553129198Scognet /* force write back cache mode */ 554129198Scognet write_through = 0; 555129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 556129198Scognet /* 557129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 558129198Scognet * write-back cache on revision 4 and earlier (stepping 559129198Scognet * A[01] and B[012]). Fixed for C0 and later. 560129198Scognet */ 561129198Scognet { 562129198Scognet uint32_t id, type; 563129198Scognet 564129198Scognet id = cpufunc_id(); 565129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 566129198Scognet 567129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 568129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 569129198Scognet /* write through for stepping A0-1 and B0-2 */ 570129198Scognet write_through = 1; 571129198Scognet } 572129198Scognet } 573129198Scognet } 574129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 575129198Scognet 576129198Scognet if (write_through) { 577129198Scognet pte_l1_s_cache_mode = L1_S_C; 578129198Scognet pte_l2_l_cache_mode = L2_C; 579129198Scognet pte_l2_s_cache_mode = L2_C; 580129198Scognet } 581129198Scognet 582129198Scognet#if (ARM_NMMUS > 1) 583129198Scognet xscale_use_minidata = 1; 584129198Scognet#endif 585129198Scognet 586129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 587129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 588129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 589129198Scognet 590129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 591129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 592129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 593129198Scognet 594164778Scognet#ifdef CPU_XSCALE_CORE3 595164778Scognet pmap_copy_page_func = pmap_copy_page_generic; 596248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_generic; 597164778Scognet pmap_zero_page_func = pmap_zero_page_generic; 598164778Scognet xscale_use_minidata = 0; 599171620Scognet /* Make sure it is L2-cachable */ 600171620Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T); 601171620Scognet pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P; 602171620Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ; 603171620Scognet pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode; 604171620Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T); 605171620Scognet pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 606171620Scognet 607164778Scognet#else 608129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 609248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_xscale; 610129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 611164778Scognet#endif 612129198Scognet 613129198Scognet /* 614129198Scognet * Disable ECC protection of page table access, for now. 615129198Scognet */ 616129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 617129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 618129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 619129198Scognet} 620129198Scognet 621129198Scognet/* 622129198Scognet * xscale_setup_minidata: 623129198Scognet * 624129198Scognet * Set up the mini-data cache clean area. We require the 625129198Scognet * caller to allocate the right amount of physically and 626129198Scognet * virtually contiguous space. 627129198Scognet */ 628129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 629129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 630129198Scognetvoid 631129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 632129198Scognet{ 633129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 634129198Scognet pt_entry_t *pte; 635129198Scognet vm_size_t size; 636129198Scognet uint32_t auxctl; 637129198Scognet 638129198Scognet xscale_minidata_clean_addr = va; 639129198Scognet 640129198Scognet /* Round it to page size. */ 641129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 642129198Scognet 643129198Scognet for (; size != 0; 644129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 645129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 646129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 647129198Scognet if (pte == NULL) 648129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 649129198Scognet "VA 0x%08x", (u_int32_t) va); 650129198Scognet pte[l2pte_index(va)] = 651129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 652129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 653129198Scognet } 654129198Scognet 655129198Scognet /* 656129198Scognet * Configure the mini-data cache for write-back with 657129198Scognet * read/write-allocate. 658129198Scognet * 659129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 660129198Scognet * make sure it contains no valid data! In order to do that, 661129198Scognet * we must issue a global data cache invalidate command! 662129198Scognet * 663129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 664129198Scognet * THIS IS VERY IMPORTANT! 665129198Scognet */ 666129198Scognet 667129198Scognet /* Invalidate data and mini-data. */ 668129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 669129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 670129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 671129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 672129198Scognet} 673129198Scognet#endif 674129198Scognet 675129198Scognet/* 676129198Scognet * Allocate an L1 translation table for the specified pmap. 677129198Scognet * This is called at pmap creation time. 678129198Scognet */ 679129198Scognetstatic void 680129198Scognetpmap_alloc_l1(pmap_t pm) 681129198Scognet{ 682129198Scognet struct l1_ttable *l1; 683129198Scognet u_int8_t domain; 684129198Scognet 685129198Scognet /* 686129198Scognet * Remove the L1 at the head of the LRU list 687129198Scognet */ 688129198Scognet mtx_lock(&l1_lru_lock); 689129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 690129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 691129198Scognet 692129198Scognet /* 693129198Scognet * Pick the first available domain number, and update 694129198Scognet * the link to the next number. 695129198Scognet */ 696129198Scognet domain = l1->l1_domain_first; 697129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 698129198Scognet 699129198Scognet /* 700129198Scognet * If there are still free domain numbers in this L1, 701129198Scognet * put it back on the TAIL of the LRU list. 702129198Scognet */ 703129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 704129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 705129198Scognet 706129198Scognet mtx_unlock(&l1_lru_lock); 707129198Scognet 708129198Scognet /* 709129198Scognet * Fix up the relevant bits in the pmap structure 710129198Scognet */ 711129198Scognet pm->pm_l1 = l1; 712174181Scognet pm->pm_domain = domain + 1; 713129198Scognet} 714129198Scognet 715129198Scognet/* 716129198Scognet * Free an L1 translation table. 717129198Scognet * This is called at pmap destruction time. 718129198Scognet */ 719129198Scognetstatic void 720129198Scognetpmap_free_l1(pmap_t pm) 721129198Scognet{ 722129198Scognet struct l1_ttable *l1 = pm->pm_l1; 723129198Scognet 724129198Scognet mtx_lock(&l1_lru_lock); 725129198Scognet 726129198Scognet /* 727129198Scognet * If this L1 is currently on the LRU list, remove it. 728129198Scognet */ 729129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 730129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 731129198Scognet 732129198Scognet /* 733129198Scognet * Free up the domain number which was allocated to the pmap 734129198Scognet */ 735174181Scognet l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 736174181Scognet l1->l1_domain_first = pm->pm_domain - 1; 737129198Scognet l1->l1_domain_use_count--; 738129198Scognet 739129198Scognet /* 740129198Scognet * The L1 now must have at least 1 free domain, so add 741129198Scognet * it back to the LRU list. If the use count is zero, 742129198Scognet * put it at the head of the list, otherwise it goes 743129198Scognet * to the tail. 744129198Scognet */ 745129198Scognet if (l1->l1_domain_use_count == 0) { 746129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 747129198Scognet } else 748129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 749129198Scognet 750129198Scognet mtx_unlock(&l1_lru_lock); 751129198Scognet} 752129198Scognet 753129198Scognet/* 754129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 755129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 756129198Scognet */ 757129198Scognetstatic PMAP_INLINE struct l2_bucket * 758129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 759129198Scognet{ 760129198Scognet struct l2_dtable *l2; 761129198Scognet struct l2_bucket *l2b; 762129198Scognet u_short l1idx; 763129198Scognet 764129198Scognet l1idx = L1_IDX(va); 765129198Scognet 766129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 767129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 768129198Scognet return (NULL); 769129198Scognet 770129198Scognet return (l2b); 771129198Scognet} 772129198Scognet 773129198Scognet/* 774129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 775129198Scognet * and VA. 776129198Scognet * 777129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 778129198Scognet * bucket/page table in place. 779129198Scognet * 780129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 781236991Simp * increment the bucket occupancy counter appropriately *before* 782129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 783129198Scognet * the bucket/page in the meantime. 784129198Scognet */ 785129198Scognetstatic struct l2_bucket * 786129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 787129198Scognet{ 788129198Scognet struct l2_dtable *l2; 789129198Scognet struct l2_bucket *l2b; 790129198Scognet u_short l1idx; 791129198Scognet 792129198Scognet l1idx = L1_IDX(va); 793129198Scognet 794159352Salc PMAP_ASSERT_LOCKED(pm); 795239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 796129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 797129198Scognet /* 798129198Scognet * No mapping at this address, as there is 799129198Scognet * no entry in the L1 table. 800129198Scognet * Need to allocate a new l2_dtable. 801129198Scognet */ 802159352Salc PMAP_UNLOCK(pm); 803239934Salc rw_wunlock(&pvh_global_lock); 804240803Salc if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) { 805239934Salc rw_wlock(&pvh_global_lock); 806159352Salc PMAP_LOCK(pm); 807129198Scognet return (NULL); 808129198Scognet } 809239934Salc rw_wlock(&pvh_global_lock); 810159352Salc PMAP_LOCK(pm); 811159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 812159108Scognet /* 813159108Scognet * Someone already allocated the l2_dtable while 814159108Scognet * we were doing the same. 815159108Scognet */ 816240803Salc uma_zfree(l2table_zone, l2); 817240803Salc l2 = pm->pm_l2[L2_IDX(l1idx)]; 818159108Scognet } else { 819159108Scognet bzero(l2, sizeof(*l2)); 820159108Scognet /* 821159108Scognet * Link it into the parent pmap 822159108Scognet */ 823159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 824159108Scognet } 825236991Simp } 826129198Scognet 827129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 828129198Scognet 829129198Scognet /* 830129198Scognet * Fetch pointer to the L2 page table associated with the address. 831129198Scognet */ 832129198Scognet if (l2b->l2b_kva == NULL) { 833129198Scognet pt_entry_t *ptep; 834129198Scognet 835129198Scognet /* 836129198Scognet * No L2 page table has been allocated. Chances are, this 837129198Scognet * is because we just allocated the l2_dtable, above. 838129198Scognet */ 839280324Scognet l2->l2_occupancy++; 840159352Salc PMAP_UNLOCK(pm); 841239934Salc rw_wunlock(&pvh_global_lock); 842240803Salc ptep = uma_zalloc(l2zone, M_NOWAIT); 843239934Salc rw_wlock(&pvh_global_lock); 844159352Salc PMAP_LOCK(pm); 845159108Scognet if (l2b->l2b_kva != 0) { 846159108Scognet /* We lost the race. */ 847280324Scognet l2->l2_occupancy--; 848159108Scognet uma_zfree(l2zone, ptep); 849159108Scognet return (l2b); 850159108Scognet } 851129198Scognet l2b->l2b_phys = vtophys(ptep); 852129198Scognet if (ptep == NULL) { 853129198Scognet /* 854129198Scognet * Oops, no more L2 page tables available at this 855129198Scognet * time. We may need to deallocate the l2_dtable 856129198Scognet * if we allocated a new one above. 857129198Scognet */ 858280324Scognet l2->l2_occupancy--; 859129198Scognet if (l2->l2_occupancy == 0) { 860129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 861240803Salc uma_zfree(l2table_zone, l2); 862129198Scognet } 863129198Scognet return (NULL); 864129198Scognet } 865129198Scognet 866129198Scognet l2b->l2b_kva = ptep; 867129198Scognet l2b->l2b_l1idx = l1idx; 868129198Scognet } 869129198Scognet 870129198Scognet return (l2b); 871129198Scognet} 872129198Scognet 873129198Scognetstatic PMAP_INLINE void 874129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 875129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 876129198Scognet#else 877129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 878129198Scognet#endif 879129198Scognet{ 880129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 881129198Scognet /* 882129198Scognet * Note: With a write-back cache, we may need to sync this 883129198Scognet * L2 table before re-using it. 884129198Scognet * This is because it may have belonged to a non-current 885129198Scognet * pmap, in which case the cache syncs would have been 886129198Scognet * skipped when the pages were being unmapped. If the 887129198Scognet * L2 table were then to be immediately re-allocated to 888129198Scognet * the *current* pmap, it may well contain stale mappings 889129198Scognet * which have not yet been cleared by a cache write-back 890129198Scognet * and so would still be visible to the mmu. 891129198Scognet */ 892129198Scognet if (need_sync) 893129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 894129198Scognet#endif 895129198Scognet uma_zfree(l2zone, l2); 896129198Scognet} 897129198Scognet/* 898129198Scognet * One or more mappings in the specified L2 descriptor table have just been 899129198Scognet * invalidated. 900129198Scognet * 901129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 902129198Scognet * 903129198Scognet * The pmap lock must be acquired when this is called (not necessary 904129198Scognet * for the kernel pmap). 905129198Scognet */ 906129198Scognetstatic void 907129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 908129198Scognet{ 909129198Scognet struct l2_dtable *l2; 910129198Scognet pd_entry_t *pl1pd, l1pd; 911129198Scognet pt_entry_t *ptep; 912129198Scognet u_short l1idx; 913129198Scognet 914129198Scognet 915129198Scognet /* 916129198Scognet * Update the bucket's reference count according to how many 917129198Scognet * PTEs the caller has just invalidated. 918129198Scognet */ 919129198Scognet l2b->l2b_occupancy -= count; 920129198Scognet 921129198Scognet /* 922129198Scognet * Note: 923129198Scognet * 924129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 925129198Scognet * as that would require checking all Level 1 page tables and 926129198Scognet * removing any references to the Level 2 page table. See also the 927129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 928129198Scognet * 929129198Scognet * We make do with just invalidating the mapping in the L2 table. 930129198Scognet * 931129198Scognet * This isn't really a big deal in practice and, in fact, leads 932129198Scognet * to a performance win over time as we don't need to continually 933129198Scognet * alloc/free. 934129198Scognet */ 935129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 936129198Scognet return; 937129198Scognet 938129198Scognet /* 939129198Scognet * There are no more valid mappings in this level 2 page table. 940129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 941129198Scognet * free the page table. 942129198Scognet */ 943129198Scognet l1idx = l2b->l2b_l1idx; 944129198Scognet ptep = l2b->l2b_kva; 945129198Scognet l2b->l2b_kva = NULL; 946129198Scognet 947129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 948129198Scognet 949129198Scognet /* 950129198Scognet * If the L1 slot matches the pmap's domain 951129198Scognet * number, then invalidate it. 952129198Scognet */ 953129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 954129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 955129198Scognet *pl1pd = 0; 956129198Scognet PTE_SYNC(pl1pd); 957129198Scognet } 958129198Scognet 959129198Scognet /* 960129198Scognet * Release the L2 descriptor table back to the pool cache. 961129198Scognet */ 962129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 963129198Scognet pmap_free_l2_ptp(ptep); 964129198Scognet#else 965135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 966129198Scognet#endif 967129198Scognet 968129198Scognet /* 969129198Scognet * Update the reference count in the associated l2_dtable 970129198Scognet */ 971129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 972129198Scognet if (--l2->l2_occupancy > 0) 973129198Scognet return; 974129198Scognet 975129198Scognet /* 976129198Scognet * There are no more valid mappings in any of the Level 1 977129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 978129198Scognet * the pointer in the parent pmap and free the l2_dtable. 979129198Scognet */ 980129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 981240803Salc uma_zfree(l2table_zone, l2); 982129198Scognet} 983129198Scognet 984129198Scognet/* 985129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 986129198Scognet * structures. 987129198Scognet */ 988133237Scognetstatic int 989133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 990129198Scognet{ 991129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 992129198Scognet struct l2_bucket *l2b; 993129198Scognet pt_entry_t *ptep, pte; 994261642Sian 995129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 996129198Scognet 997129198Scognet /* 998129198Scognet * The mappings for these page tables were initially made using 999135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1000129198Scognet * mode will not be right for page table mappings. To avoid 1001135641Scognet * polluting the pmap_kenter() code with a special case for 1002129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1003129198Scognet * correct. 1004129198Scognet */ 1005147114Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1006147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1007147114Scognet pte = *ptep; 1008283366Sandrew 1009147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1010147114Scognet /* 1011236991Simp * Page tables must have the cache-mode set to 1012147114Scognet * Write-Thru. 1013147114Scognet */ 1014147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1015147114Scognet PTE_SYNC(ptep); 1016147114Scognet cpu_tlb_flushD_SE(va); 1017147114Scognet cpu_cpwait(); 1018147114Scognet } 1019129198Scognet#endif 1020129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1021129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1022133237Scognet return (0); 1023129198Scognet} 1024129198Scognet 1025129198Scognet/* 1026129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1027129198Scognet * on whether the specified pmap actually needs to be flushed at any 1028129198Scognet * given time. 1029129198Scognet */ 1030129198Scognetstatic PMAP_INLINE void 1031129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1032129198Scognet{ 1033129198Scognet 1034135641Scognet if (pmap_is_current(pm)) 1035129198Scognet cpu_tlb_flushID_SE(va); 1036129198Scognet} 1037129198Scognet 1038129198Scognetstatic PMAP_INLINE void 1039129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1040129198Scognet{ 1041129198Scognet 1042135641Scognet if (pmap_is_current(pm)) 1043129198Scognet cpu_tlb_flushD_SE(va); 1044129198Scognet} 1045129198Scognet 1046129198Scognetstatic PMAP_INLINE void 1047129198Scognetpmap_tlb_flushID(pmap_t pm) 1048129198Scognet{ 1049129198Scognet 1050135641Scognet if (pmap_is_current(pm)) 1051129198Scognet cpu_tlb_flushID(); 1052129198Scognet} 1053129198Scognetstatic PMAP_INLINE void 1054129198Scognetpmap_tlb_flushD(pmap_t pm) 1055129198Scognet{ 1056129198Scognet 1057135641Scognet if (pmap_is_current(pm)) 1058129198Scognet cpu_tlb_flushD(); 1059129198Scognet} 1060129198Scognet 1061203637Srajstatic int 1062203637Srajpmap_has_valid_mapping(pmap_t pm, vm_offset_t va) 1063183838Sraj{ 1064183838Sraj pd_entry_t *pde; 1065183838Sraj pt_entry_t *ptep; 1066183838Sraj 1067203637Sraj if (pmap_get_pde_pte(pm, va, &pde, &ptep) && 1068203637Sraj ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV)) 1069203637Sraj return (1); 1070183838Sraj 1071203637Sraj return (0); 1072183838Sraj} 1073183838Sraj 1074183838Srajstatic PMAP_INLINE void 1075129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1076129198Scognet{ 1077183838Sraj vm_size_t rest; 1078129198Scognet 1079203637Sraj CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x" 1080203637Sraj " len 0x%x ", pm, pm == pmap_kernel(), va, len); 1081183838Sraj 1082203637Sraj if (pmap_is_current(pm) || pm == pmap_kernel()) { 1083203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1084203637Sraj while (len > 0) { 1085203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1086203637Sraj cpu_idcache_wbinv_range(va, rest); 1087203637Sraj cpu_l2cache_wbinv_range(va, rest); 1088203637Sraj } 1089203637Sraj len -= rest; 1090203637Sraj va += rest; 1091203637Sraj rest = MIN(PAGE_SIZE, len); 1092203637Sraj } 1093183838Sraj } 1094183838Sraj} 1095183838Sraj 1096183838Srajstatic PMAP_INLINE void 1097183838Srajpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv, 1098183838Sraj boolean_t rd_only) 1099183838Sraj{ 1100203637Sraj vm_size_t rest; 1101184730Sraj 1102183838Sraj CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x " 1103183838Sraj "len 0x%x ", pm, pm == pmap_kernel(), va, len); 1104183838Sraj CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only); 1105183838Sraj 1106135641Scognet if (pmap_is_current(pm)) { 1107203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1108203637Sraj while (len > 0) { 1109203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1110203637Sraj if (do_inv && rd_only) { 1111203637Sraj cpu_dcache_inv_range(va, rest); 1112203637Sraj cpu_l2cache_inv_range(va, rest); 1113203637Sraj } else if (do_inv) { 1114203637Sraj cpu_dcache_wbinv_range(va, rest); 1115203637Sraj cpu_l2cache_wbinv_range(va, rest); 1116203637Sraj } else if (!rd_only) { 1117203637Sraj cpu_dcache_wb_range(va, rest); 1118203637Sraj cpu_l2cache_wb_range(va, rest); 1119203637Sraj } 1120183838Sraj } 1121203637Sraj len -= rest; 1122203637Sraj va += rest; 1123203637Sraj 1124203637Sraj rest = MIN(PAGE_SIZE, len); 1125183838Sraj } 1126129198Scognet } 1127129198Scognet} 1128129198Scognet 1129129198Scognetstatic PMAP_INLINE void 1130129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1131129198Scognet{ 1132129198Scognet 1133183838Sraj if (pmap_is_current(pm)) { 1134129198Scognet cpu_idcache_wbinv_all(); 1135183838Sraj cpu_l2cache_wbinv_all(); 1136183838Sraj } 1137129198Scognet} 1138129198Scognet 1139197770Sstas#ifdef notyet 1140129198Scognetstatic PMAP_INLINE void 1141129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1142129198Scognet{ 1143129198Scognet 1144183838Sraj if (pmap_is_current(pm)) { 1145129198Scognet cpu_dcache_wbinv_all(); 1146183838Sraj cpu_l2cache_wbinv_all(); 1147183838Sraj } 1148129198Scognet} 1149197770Sstas#endif 1150129198Scognet 1151129198Scognet/* 1152129198Scognet * PTE_SYNC_CURRENT: 1153129198Scognet * 1154129198Scognet * Make sure the pte is written out to RAM. 1155129198Scognet * We need to do this for one of two cases: 1156129198Scognet * - We're dealing with the kernel pmap 1157129198Scognet * - There is no pmap active in the cache/tlb. 1158129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1159129198Scognet */ 1160129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1161129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1162129198Scognetdo { \ 1163129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1164135641Scognet pmap_is_current(pm)) \ 1165129198Scognet PTE_SYNC(ptep); \ 1166129198Scognet} while (/*CONSTCOND*/0) 1167129198Scognet#else 1168129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1169129198Scognet#endif 1170129198Scognet 1171129198Scognet/* 1172175840Scognet * cacheable == -1 means we must make the entry uncacheable, 1 means 1173175840Scognet * cacheable; 1174129198Scognet */ 1175129198Scognetstatic __inline void 1176175840Scognetpmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable) 1177129198Scognet{ 1178175840Scognet struct l2_bucket *l2b; 1179175840Scognet pt_entry_t *ptep, pte; 1180129198Scognet 1181175840Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1182175840Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1183129198Scognet 1184175840Scognet if (cacheable == 1) { 1185175840Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1186175840Scognet if (l2pte_valid(pte)) { 1187175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1188175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1189175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1190175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1191175840Scognet } 1192175840Scognet } 1193175840Scognet } else { 1194175840Scognet pte = *ptep &~ L2_S_CACHE_MASK; 1195175840Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1196175840Scognet l2pte_valid(pte)) { 1197175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1198175840Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1199175840Scognet pv->pv_va, PAGE_SIZE); 1200175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1201175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1202175840Scognet pmap_dcache_wb_range(pv->pv_pmap, 1203175840Scognet pv->pv_va, PAGE_SIZE, TRUE, 1204175840Scognet (pv->pv_flags & PVF_WRITE) == 0); 1205175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1206175840Scognet pv->pv_va); 1207175840Scognet } 1208175840Scognet } 1209129198Scognet } 1210175840Scognet *ptep = pte; 1211175840Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1212129198Scognet} 1213129198Scognet 1214129198Scognetstatic void 1215175840Scognetpmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1216129198Scognet{ 1217175840Scognet int pmwc = 0; 1218175840Scognet int writable = 0, kwritable = 0, uwritable = 0; 1219175840Scognet int entries = 0, kentries = 0, uentries = 0; 1220129198Scognet struct pv_entry *pv; 1221129198Scognet 1222239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1223129198Scognet 1224175840Scognet /* the cache gets written back/invalidated on context switch. 1225175840Scognet * therefore, if a user page shares an entry in the same page or 1226175840Scognet * with the kernel map and at least one is writable, then the 1227175840Scognet * cache entry must be set write-through. 1228129198Scognet */ 1229129198Scognet 1230175840Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1231175840Scognet /* generate a count of the pv_entry uses */ 1232175840Scognet if (pv->pv_flags & PVF_WRITE) { 1233175840Scognet if (pv->pv_pmap == pmap_kernel()) 1234175840Scognet kwritable++; 1235175840Scognet else if (pv->pv_pmap == pm) 1236175840Scognet uwritable++; 1237175840Scognet writable++; 1238129198Scognet } 1239175840Scognet if (pv->pv_pmap == pmap_kernel()) 1240175840Scognet kentries++; 1241175840Scognet else { 1242175840Scognet if (pv->pv_pmap == pm) 1243175840Scognet uentries++; 1244175840Scognet entries++; 1245175840Scognet } 1246129198Scognet } 1247175840Scognet /* 1248175840Scognet * check if the user duplicate mapping has 1249175840Scognet * been removed. 1250175840Scognet */ 1251175840Scognet if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) || 1252175840Scognet (uwritable > 1))) 1253175840Scognet pmwc = 1; 1254129198Scognet 1255129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1256175840Scognet /* check for user uncachable conditions - order is important */ 1257175840Scognet if (pm != pmap_kernel() && 1258175840Scognet (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) { 1259129198Scognet 1260175840Scognet if ((uentries > 1 && uwritable) || uwritable > 1) { 1261129198Scognet 1262175840Scognet /* user duplicate mapping */ 1263175840Scognet if (pv->pv_pmap != pmap_kernel()) 1264175840Scognet pv->pv_flags |= PVF_MWC; 1265129198Scognet 1266175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1267175840Scognet pv->pv_flags |= PVF_NC; 1268175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1269175840Scognet } 1270129198Scognet continue; 1271175840Scognet } else /* no longer a duplicate user */ 1272175840Scognet pv->pv_flags &= ~PVF_MWC; 1273175840Scognet } 1274129198Scognet 1275175840Scognet /* 1276175840Scognet * check for kernel uncachable conditions 1277175840Scognet * kernel writable or kernel readable with writable user entry 1278175840Scognet */ 1279209223Scognet if ((kwritable && (entries || kentries > 1)) || 1280194459Sthompsa (kwritable > 1) || 1281175840Scognet ((kwritable != writable) && kentries && 1282175840Scognet (pv->pv_pmap == pmap_kernel() || 1283175840Scognet (pv->pv_flags & PVF_WRITE) || 1284175840Scognet (pv->pv_flags & PVF_MWC)))) { 1285129198Scognet 1286175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1287175840Scognet pv->pv_flags |= PVF_NC; 1288175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1289129198Scognet } 1290175840Scognet continue; 1291129198Scognet } 1292129198Scognet 1293175840Scognet /* kernel and user are cachable */ 1294175840Scognet if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) && 1295175840Scognet (pv->pv_flags & PVF_NC)) { 1296175840Scognet 1297129198Scognet pv->pv_flags &= ~PVF_NC; 1298244574Scognet if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 1299244414Scognet pmap_set_cache_entry(pv, pm, va, 1); 1300175840Scognet continue; 1301175840Scognet } 1302175840Scognet /* user is no longer sharable and writable */ 1303194459Sthompsa if (pm != pmap_kernel() && 1304194459Sthompsa (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) && 1305175840Scognet !pmwc && (pv->pv_flags & PVF_NC)) { 1306129198Scognet 1307175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1308244574Scognet if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 1309244414Scognet pmap_set_cache_entry(pv, pm, va, 1); 1310129198Scognet } 1311129198Scognet } 1312175840Scognet 1313175840Scognet if ((kwritable == 0) && (writable == 0)) { 1314175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1315225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1316175840Scognet return; 1317175840Scognet } 1318129198Scognet} 1319129198Scognet 1320129198Scognet/* 1321129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1322129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1323129198Scognet * constants and the latter would require an extra inversion at run-time. 1324129198Scognet */ 1325236991Simpstatic int 1326129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1327129198Scognet{ 1328129198Scognet struct l2_bucket *l2b; 1329129198Scognet struct pv_entry *pv; 1330129198Scognet pt_entry_t *ptep, npte, opte; 1331129198Scognet pmap_t pm; 1332129198Scognet vm_offset_t va; 1333129198Scognet u_int oflags; 1334135641Scognet int count = 0; 1335129198Scognet 1336239934Salc rw_wlock(&pvh_global_lock); 1337159352Salc 1338175840Scognet if (maskbits & PVF_WRITE) 1339175840Scognet maskbits |= PVF_MOD; 1340129198Scognet /* 1341129198Scognet * Clear saved attributes (modify, reference) 1342129198Scognet */ 1343129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1344129198Scognet 1345129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1346239934Salc rw_wunlock(&pvh_global_lock); 1347135641Scognet return (0); 1348129198Scognet } 1349129198Scognet 1350129198Scognet /* 1351129198Scognet * Loop over all current mappings setting/clearing as appropos 1352129198Scognet */ 1353129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1354129198Scognet va = pv->pv_va; 1355129198Scognet pm = pv->pv_pmap; 1356129198Scognet oflags = pv->pv_flags; 1357175840Scognet 1358175840Scognet if (!(oflags & maskbits)) { 1359175840Scognet if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) { 1360283366Sandrew if (pg->md.pv_memattr != 1361244574Scognet VM_MEMATTR_UNCACHEABLE) { 1362244414Scognet PMAP_LOCK(pm); 1363244414Scognet l2b = pmap_get_l2_bucket(pm, va); 1364244414Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1365244414Scognet *ptep |= pte_l2_s_cache_mode; 1366244414Scognet PTE_SYNC(ptep); 1367244414Scognet PMAP_UNLOCK(pm); 1368244414Scognet } 1369175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1370175840Scognet } 1371175840Scognet continue; 1372175840Scognet } 1373129198Scognet pv->pv_flags &= ~maskbits; 1374129198Scognet 1375159352Salc PMAP_LOCK(pm); 1376129198Scognet 1377129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1378129198Scognet 1379129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1380129198Scognet npte = opte = *ptep; 1381129198Scognet 1382157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1383129198Scognet if ((pv->pv_flags & PVF_NC)) { 1384236991Simp /* 1385129198Scognet * Entry is not cacheable: 1386129198Scognet * 1387236991Simp * Don't turn caching on again if this is a 1388129198Scognet * modified emulation. This would be 1389129198Scognet * inconsitent with the settings created by 1390175840Scognet * pmap_fix_cache(). Otherwise, it's safe 1391129198Scognet * to re-enable cacheing. 1392129198Scognet * 1393175840Scognet * There's no need to call pmap_fix_cache() 1394129198Scognet * here: all pages are losing their write 1395129198Scognet * permission. 1396129198Scognet */ 1397129198Scognet if (maskbits & PVF_WRITE) { 1398244574Scognet if (pg->md.pv_memattr != 1399244574Scognet VM_MEMATTR_UNCACHEABLE) 1400244414Scognet npte |= pte_l2_s_cache_mode; 1401175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1402129198Scognet } 1403129198Scognet } else 1404129198Scognet if (opte & L2_S_PROT_W) { 1405144760Scognet vm_page_dirty(pg); 1406236991Simp /* 1407129198Scognet * Entry is writable/cacheable: check if pmap 1408129198Scognet * is current if it is flush it, otherwise it 1409129198Scognet * won't be in the cache 1410129198Scognet */ 1411129198Scognet if (PV_BEEN_EXECD(oflags)) 1412129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1413129198Scognet PAGE_SIZE); 1414129198Scognet else 1415129198Scognet if (PV_BEEN_REFD(oflags)) 1416129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1417129198Scognet PAGE_SIZE, 1418129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1419129198Scognet FALSE); 1420129198Scognet } 1421129198Scognet 1422129198Scognet /* make the pte read only */ 1423129198Scognet npte &= ~L2_S_PROT_W; 1424129198Scognet } 1425129198Scognet 1426157970Scognet if (maskbits & PVF_REF) { 1427129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1428129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1429129198Scognet /* 1430129198Scognet * Check npte here; we may have already 1431129198Scognet * done the wbinv above, and the validity 1432129198Scognet * of the PTE is the same for opte and 1433129198Scognet * npte. 1434129198Scognet */ 1435129198Scognet if (npte & L2_S_PROT_W) { 1436129198Scognet if (PV_BEEN_EXECD(oflags)) 1437129198Scognet pmap_idcache_wbinv_range(pm, 1438129198Scognet pv->pv_va, PAGE_SIZE); 1439129198Scognet else 1440129198Scognet if (PV_BEEN_REFD(oflags)) 1441129198Scognet pmap_dcache_wb_range(pm, 1442129198Scognet pv->pv_va, PAGE_SIZE, 1443129198Scognet TRUE, FALSE); 1444129198Scognet } else 1445129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1446129198Scognet /* XXXJRT need idcache_inv_range */ 1447129198Scognet if (PV_BEEN_EXECD(oflags)) 1448129198Scognet pmap_idcache_wbinv_range(pm, 1449129198Scognet pv->pv_va, PAGE_SIZE); 1450129198Scognet else 1451129198Scognet if (PV_BEEN_REFD(oflags)) 1452129198Scognet pmap_dcache_wb_range(pm, 1453129198Scognet pv->pv_va, PAGE_SIZE, 1454129198Scognet TRUE, TRUE); 1455129198Scognet } 1456129198Scognet } 1457129198Scognet 1458129198Scognet /* 1459129198Scognet * Make the PTE invalid so that we will take a 1460129198Scognet * page fault the next time the mapping is 1461129198Scognet * referenced. 1462129198Scognet */ 1463129198Scognet npte &= ~L2_TYPE_MASK; 1464129198Scognet npte |= L2_TYPE_INV; 1465129198Scognet } 1466129198Scognet 1467129198Scognet if (npte != opte) { 1468135641Scognet count++; 1469129198Scognet *ptep = npte; 1470129198Scognet PTE_SYNC(ptep); 1471129198Scognet /* Flush the TLB entry if a current pmap. */ 1472129198Scognet if (PV_BEEN_EXECD(oflags)) 1473129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1474129198Scognet else 1475129198Scognet if (PV_BEEN_REFD(oflags)) 1476129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1477129198Scognet } 1478129198Scognet 1479159352Salc PMAP_UNLOCK(pm); 1480129198Scognet 1481129198Scognet } 1482129198Scognet 1483137664Scognet if (maskbits & PVF_WRITE) 1484225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1485239934Salc rw_wunlock(&pvh_global_lock); 1486135641Scognet return (count); 1487129198Scognet} 1488129198Scognet 1489129198Scognet/* 1490129198Scognet * main pv_entry manipulation functions: 1491129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1492129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1493129198Scognet * 1494129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1495240166Salc * pmap_remove_pv expects the caller to lock the pvh before calling 1496129198Scognet */ 1497129198Scognet 1498129198Scognet/* 1499240442Salc * pmap_enter_pv: enter a mapping onto a vm_page's PV list 1500129198Scognet * 1501240166Salc * => caller should hold the proper lock on pvh_global_lock 1502129198Scognet * => caller should have pmap locked 1503240442Salc * => we will (someday) gain the lock on the vm_page's PV list 1504129198Scognet * => caller should adjust ptp's wire_count before calling 1505129198Scognet * => caller should not adjust pmap's wire_count 1506129198Scognet */ 1507129198Scognetstatic void 1508129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1509129198Scognet vm_offset_t va, u_int flags) 1510129198Scognet{ 1511194459Sthompsa 1512239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1513240442Salc PMAP_ASSERT_LOCKED(pm); 1514240166Salc if (pg->md.pv_kva != 0) { 1515240442Salc pve->pv_pmap = kernel_pmap; 1516194459Sthompsa pve->pv_va = pg->md.pv_kva; 1517194459Sthompsa pve->pv_flags = PVF_WRITE | PVF_UNMAN; 1518240442Salc if (pm != kernel_pmap) 1519240442Salc PMAP_LOCK(kernel_pmap); 1520240442Salc TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1521240442Salc TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist); 1522240442Salc if (pm != kernel_pmap) 1523240442Salc PMAP_UNLOCK(kernel_pmap); 1524194459Sthompsa pg->md.pv_kva = 0; 1525194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 1526240166Salc panic("pmap_kenter_pv: no pv entries"); 1527194459Sthompsa } 1528129198Scognet pve->pv_pmap = pm; 1529129198Scognet pve->pv_va = va; 1530129198Scognet pve->pv_flags = flags; 1531129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1532144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1533129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1534129198Scognet if (pve->pv_flags & PVF_WIRED) 1535129198Scognet ++pm->pm_stats.wired_count; 1536225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1537129198Scognet} 1538129198Scognet 1539129198Scognet/* 1540129198Scognet * 1541129198Scognet * pmap_find_pv: Find a pv entry 1542129198Scognet * 1543129198Scognet * => caller should hold lock on vm_page 1544129198Scognet */ 1545129198Scognetstatic PMAP_INLINE struct pv_entry * 1546129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1547129198Scognet{ 1548129198Scognet struct pv_entry *pv; 1549129198Scognet 1550239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1551129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1552129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1553129198Scognet break; 1554129198Scognet return (pv); 1555129198Scognet} 1556129198Scognet 1557129198Scognet/* 1558129198Scognet * vector_page_setprot: 1559129198Scognet * 1560129198Scognet * Manipulate the protection of the vector page. 1561129198Scognet */ 1562129198Scognetvoid 1563129198Scognetvector_page_setprot(int prot) 1564129198Scognet{ 1565129198Scognet struct l2_bucket *l2b; 1566129198Scognet pt_entry_t *ptep; 1567129198Scognet 1568129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1569129198Scognet 1570129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1571129198Scognet 1572129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1573129198Scognet PTE_SYNC(ptep); 1574129198Scognet cpu_tlb_flushD_SE(vector_page); 1575129198Scognet cpu_cpwait(); 1576129198Scognet} 1577129198Scognet 1578129198Scognet/* 1579129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1580129198Scognet * 1581129198Scognet * => caller should hold proper lock on pmap_main_lock 1582129198Scognet * => pmap should be locked 1583129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1584129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1585129198Scognet * => caller should NOT adjust pmap's wire_count 1586129198Scognet * => we return the removed pve 1587129198Scognet */ 1588135641Scognet 1589135641Scognetstatic void 1590135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1591135641Scognet{ 1592135641Scognet 1593194459Sthompsa struct pv_entry *pv; 1594239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1595159352Salc PMAP_ASSERT_LOCKED(pm); 1596135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1597144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1598135641Scognet if (pve->pv_flags & PVF_WIRED) 1599135641Scognet --pm->pm_stats.wired_count; 1600144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1601144760Scognet vm_page_dirty(pg); 1602175840Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1603175840Scognet pg->md.pvh_attrs &= ~PVF_REF; 1604175840Scognet else 1605225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1606175840Scognet if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) || 1607175840Scognet (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC))) 1608175840Scognet pmap_fix_cache(pg, pm, 0); 1609175840Scognet else if (pve->pv_flags & PVF_WRITE) { 1610175840Scognet TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list) 1611175840Scognet if (pve->pv_flags & PVF_WRITE) 1612175840Scognet break; 1613175840Scognet if (!pve) { 1614175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1615225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1616175840Scognet } 1617146647Scognet } 1618194459Sthompsa pv = TAILQ_FIRST(&pg->md.pv_list); 1619194459Sthompsa if (pv != NULL && (pv->pv_flags & PVF_UNMAN) && 1620194459Sthompsa TAILQ_NEXT(pv, pv_list) == NULL) { 1621205425Scognet pm = kernel_pmap; 1622194459Sthompsa pg->md.pv_kva = pv->pv_va; 1623194459Sthompsa /* a recursive pmap_nuke_pv */ 1624194459Sthompsa TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list); 1625194459Sthompsa TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist); 1626194459Sthompsa if (pv->pv_flags & PVF_WIRED) 1627194459Sthompsa --pm->pm_stats.wired_count; 1628194459Sthompsa pg->md.pvh_attrs &= ~PVF_REF; 1629194459Sthompsa pg->md.pvh_attrs &= ~PVF_MOD; 1630225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1631194459Sthompsa pmap_free_pv_entry(pv); 1632194459Sthompsa } 1633135641Scognet} 1634135641Scognet 1635129198Scognetstatic struct pv_entry * 1636129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1637129198Scognet{ 1638135641Scognet struct pv_entry *pve; 1639129198Scognet 1640239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1641135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1642129198Scognet 1643129198Scognet while (pve) { 1644129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1645135641Scognet pmap_nuke_pv(pg, pm, pve); 1646129198Scognet break; 1647129198Scognet } 1648129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1649129198Scognet } 1650129198Scognet 1651194459Sthompsa if (pve == NULL && pg->md.pv_kva == va) 1652194459Sthompsa pg->md.pv_kva = 0; 1653194459Sthompsa 1654129198Scognet return(pve); /* return removed pve */ 1655129198Scognet} 1656129198Scognet/* 1657129198Scognet * 1658129198Scognet * pmap_modify_pv: Update pv flags 1659129198Scognet * 1660129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1661129198Scognet * => caller should NOT adjust pmap's wire_count 1662129198Scognet * => we return the old flags 1663236991Simp * 1664129198Scognet * Modify a physical-virtual mapping in the pv table 1665129198Scognet */ 1666129198Scognetstatic u_int 1667129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1668129198Scognet u_int clr_mask, u_int set_mask) 1669129198Scognet{ 1670129198Scognet struct pv_entry *npv; 1671129198Scognet u_int flags, oflags; 1672129198Scognet 1673159352Salc PMAP_ASSERT_LOCKED(pm); 1674239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1675129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1676129198Scognet return (0); 1677129198Scognet 1678129198Scognet /* 1679129198Scognet * There is at least one VA mapping this page. 1680129198Scognet */ 1681129198Scognet 1682129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1683129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1684129198Scognet 1685129198Scognet oflags = npv->pv_flags; 1686129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1687129198Scognet 1688129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1689129198Scognet if (flags & PVF_WIRED) 1690129198Scognet ++pm->pm_stats.wired_count; 1691129198Scognet else 1692129198Scognet --pm->pm_stats.wired_count; 1693129198Scognet } 1694129198Scognet 1695175840Scognet if ((flags ^ oflags) & PVF_WRITE) 1696175840Scognet pmap_fix_cache(pg, pm, 0); 1697129198Scognet 1698129198Scognet return (oflags); 1699129198Scognet} 1700129198Scognet 1701129198Scognet/* Function to set the debug level of the pmap code */ 1702129198Scognet#ifdef PMAP_DEBUG 1703129198Scognetvoid 1704129198Scognetpmap_debug(int level) 1705129198Scognet{ 1706129198Scognet pmap_debug_level = level; 1707129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1708129198Scognet} 1709129198Scognet#endif /* PMAP_DEBUG */ 1710129198Scognet 1711129198Scognetvoid 1712129198Scognetpmap_pinit0(struct pmap *pmap) 1713129198Scognet{ 1714129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1715129198Scognet 1716135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1717159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1718159325Salc PMAP_LOCK_INIT(pmap); 1719129198Scognet} 1720129198Scognet 1721147217Salc/* 1722147217Salc * Initialize a vm_page's machine-dependent fields. 1723147217Salc */ 1724147217Salcvoid 1725147217Salcpmap_page_init(vm_page_t m) 1726147217Salc{ 1727129198Scognet 1728147217Salc TAILQ_INIT(&m->md.pv_list); 1729244414Scognet m->md.pv_memattr = VM_MEMATTR_DEFAULT; 1730147217Salc} 1731147217Salc 1732129198Scognet/* 1733129198Scognet * Initialize the pmap module. 1734129198Scognet * Called by vm_init, to initialize any structures that the pmap 1735129198Scognet * system needs to map virtual memory. 1736129198Scognet */ 1737129198Scognetvoid 1738129198Scognetpmap_init(void) 1739129198Scognet{ 1740152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1741129198Scognet 1742240803Salc l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1743240803Salc NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1744240803Salc l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL, 1745240803Salc NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1746240803Salc 1747129198Scognet /* 1748240803Salc * Initialize the PV entry allocator. 1749129198Scognet */ 1750236991Simp pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1751129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1752240803Salc TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1753263620Sbdrewery pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1754247360Sattilio uma_zone_reserve_kva(pvzone, pv_entry_max); 1755240803Salc pv_entry_high_water = 9 * (pv_entry_max / 10); 1756240803Salc 1757129198Scognet /* 1758129198Scognet * Now it is safe to enable pv_table recording. 1759129198Scognet */ 1760129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1761129198Scognet} 1762129198Scognet 1763129198Scognetint 1764129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1765129198Scognet{ 1766129198Scognet struct l2_dtable *l2; 1767129198Scognet struct l2_bucket *l2b; 1768129198Scognet pd_entry_t *pl1pd, l1pd; 1769129198Scognet pt_entry_t *ptep, pte; 1770129198Scognet vm_paddr_t pa; 1771129198Scognet u_int l1idx; 1772129198Scognet int rv = 0; 1773129198Scognet 1774129198Scognet l1idx = L1_IDX(va); 1775239934Salc rw_wlock(&pvh_global_lock); 1776159384Salc PMAP_LOCK(pm); 1777129198Scognet 1778129198Scognet /* 1779129198Scognet * If there is no l2_dtable for this address, then the process 1780129198Scognet * has no business accessing it. 1781129198Scognet * 1782129198Scognet * Note: This will catch userland processes trying to access 1783129198Scognet * kernel addresses. 1784129198Scognet */ 1785129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1786129198Scognet if (l2 == NULL) 1787129198Scognet goto out; 1788129198Scognet 1789129198Scognet /* 1790129198Scognet * Likewise if there is no L2 descriptor table 1791129198Scognet */ 1792129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1793129198Scognet if (l2b->l2b_kva == NULL) 1794129198Scognet goto out; 1795129198Scognet 1796129198Scognet /* 1797129198Scognet * Check the PTE itself. 1798129198Scognet */ 1799129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1800129198Scognet pte = *ptep; 1801129198Scognet if (pte == 0) 1802129198Scognet goto out; 1803129198Scognet 1804129198Scognet /* 1805129198Scognet * Catch a userland access to the vector page mapped at 0x0 1806129198Scognet */ 1807129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 1808129198Scognet goto out; 1809157027Scognet if (va == vector_page) 1810157027Scognet goto out; 1811129198Scognet 1812129198Scognet pa = l2pte_pa(pte); 1813129198Scognet 1814129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 1815129198Scognet /* 1816129198Scognet * This looks like a good candidate for "page modified" 1817129198Scognet * emulation... 1818129198Scognet */ 1819129198Scognet struct pv_entry *pv; 1820129198Scognet struct vm_page *pg; 1821129198Scognet 1822129198Scognet /* Extract the physical address of the page */ 1823129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 1824129198Scognet goto out; 1825129198Scognet } 1826129198Scognet /* Get the current flags for this page. */ 1827129198Scognet 1828129198Scognet pv = pmap_find_pv(pg, pm, va); 1829129198Scognet if (pv == NULL) { 1830129198Scognet goto out; 1831129198Scognet } 1832129198Scognet 1833129198Scognet /* 1834129198Scognet * Do the flags say this page is writable? If not then it 1835129198Scognet * is a genuine write fault. If yes then the write fault is 1836129198Scognet * our fault as we did not reflect the write access in the 1837129198Scognet * PTE. Now we know a write has occurred we can correct this 1838129198Scognet * and also set the modified bit 1839129198Scognet */ 1840129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 1841129198Scognet goto out; 1842129198Scognet } 1843129198Scognet 1844157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 1845157970Scognet vm_page_dirty(pg); 1846129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 1847129198Scognet 1848236991Simp /* 1849129198Scognet * Re-enable write permissions for the page. No need to call 1850175840Scognet * pmap_fix_cache(), since this is just a 1851129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 1852129198Scognet * changing. We've already set the cacheable bits based on 1853129198Scognet * the assumption that we can write to this page. 1854129198Scognet */ 1855147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 1856129198Scognet PTE_SYNC(ptep); 1857129198Scognet rv = 1; 1858129198Scognet } else 1859129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 1860129198Scognet /* 1861129198Scognet * This looks like a good candidate for "page referenced" 1862129198Scognet * emulation. 1863129198Scognet */ 1864129198Scognet struct pv_entry *pv; 1865129198Scognet struct vm_page *pg; 1866129198Scognet 1867129198Scognet /* Extract the physical address of the page */ 1868159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 1869129198Scognet goto out; 1870129198Scognet /* Get the current flags for this page. */ 1871129198Scognet 1872129198Scognet pv = pmap_find_pv(pg, pm, va); 1873159384Salc if (pv == NULL) 1874129198Scognet goto out; 1875129198Scognet 1876129198Scognet pg->md.pvh_attrs |= PVF_REF; 1877129198Scognet pv->pv_flags |= PVF_REF; 1878129198Scognet 1879129198Scognet 1880129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 1881129198Scognet PTE_SYNC(ptep); 1882129198Scognet rv = 1; 1883129198Scognet } 1884129198Scognet 1885129198Scognet /* 1886129198Scognet * We know there is a valid mapping here, so simply 1887129198Scognet * fix up the L1 if necessary. 1888129198Scognet */ 1889129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1890129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 1891129198Scognet if (*pl1pd != l1pd) { 1892129198Scognet *pl1pd = l1pd; 1893129198Scognet PTE_SYNC(pl1pd); 1894129198Scognet rv = 1; 1895129198Scognet } 1896129198Scognet 1897129198Scognet#ifdef DEBUG 1898129198Scognet /* 1899129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 1900129198Scognet * stale TLB entry for the faulting address. This happens when two or 1901129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 1902129198Scognet * a context switch between such processes, we can take domain faults 1903129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 1904129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 1905129198Scognet * example. 1906129198Scognet * 1907129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 1908129198Scognet * entry for a recently entered mapping. In this case, the TLB is 1909129198Scognet * flushed for the new mapping, but there may still be TLB entries for 1910129198Scognet * other mappings belonging to other processes in the 1MB range 1911129198Scognet * covered by the L1 entry. 1912129198Scognet * 1913129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 1914129198Scognet * value, so the fault must be due to a stale TLB entry. 1915129198Scognet * 1916129198Scognet * Since we always need to flush the TLB anyway in the case where we 1917129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 1918129198Scognet * stale TLB entries dynamically. 1919129198Scognet * 1920129198Scognet * However, the above condition can ONLY happen if the current L1 is 1921129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 1922129198Scognet * that other parts of the pmap are not doing their job WRT managing 1923129198Scognet * the TLB. 1924129198Scognet */ 1925129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 1926129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 1927225988Smarcel pm, (u_long)va, ftype); 1928129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 1929129198Scognet l2, l2b, ptep, pl1pd); 1930129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 1931129198Scognet pte, l1pd, last_fault_code); 1932129198Scognet#ifdef DDB 1933129198Scognet Debugger(); 1934129198Scognet#endif 1935129198Scognet } 1936129198Scognet#endif 1937129198Scognet 1938129198Scognet cpu_tlb_flushID_SE(va); 1939129198Scognet cpu_cpwait(); 1940129198Scognet 1941129198Scognet rv = 1; 1942129198Scognet 1943129198Scognetout: 1944239934Salc rw_wunlock(&pvh_global_lock); 1945159384Salc PMAP_UNLOCK(pm); 1946129198Scognet return (rv); 1947129198Scognet} 1948129198Scognet 1949129198Scognetvoid 1950152128Scognetpmap_postinit(void) 1951152128Scognet{ 1952129198Scognet struct l2_bucket *l2b; 1953129198Scognet struct l1_ttable *l1; 1954129198Scognet pd_entry_t *pl1pt; 1955129198Scognet pt_entry_t *ptep, pte; 1956129198Scognet vm_offset_t va, eva; 1957129198Scognet u_int loop, needed; 1958283366Sandrew 1959129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 1960129198Scognet needed -= 1; 1961129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 1962129198Scognet 1963129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 1964129198Scognet /* Allocate a L1 page table */ 1965132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 1966132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 1967129198Scognet 1968129198Scognet if (va == 0) 1969129198Scognet panic("Cannot allocate L1 KVM"); 1970129198Scognet 1971129198Scognet eva = va + L1_TABLE_SIZE; 1972129198Scognet pl1pt = (pd_entry_t *)va; 1973283366Sandrew 1974135641Scognet while (va < eva) { 1975129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1976129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1977129198Scognet pte = *ptep; 1978129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1979129198Scognet *ptep = pte; 1980129198Scognet PTE_SYNC(ptep); 1981129198Scognet cpu_tlb_flushD_SE(va); 1982283366Sandrew 1983129198Scognet va += PAGE_SIZE; 1984129198Scognet } 1985129198Scognet pmap_init_l1(l1, pl1pt); 1986129198Scognet } 1987129198Scognet 1988129198Scognet 1989129198Scognet#ifdef DEBUG 1990129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 1991129198Scognet needed); 1992129198Scognet#endif 1993129198Scognet} 1994129198Scognet 1995129198Scognet/* 1996129198Scognet * This is used to stuff certain critical values into the PCB where they 1997129198Scognet * can be accessed quickly from cpu_switch() et al. 1998129198Scognet */ 1999129198Scognetvoid 2000129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2001129198Scognet{ 2002129198Scognet struct l2_bucket *l2b; 2003129198Scognet 2004129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2005129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2006129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2007129198Scognet 2008129198Scognet if (vector_page < KERNBASE) { 2009129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2010129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2011129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2012145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2013129198Scognet } else 2014129198Scognet pcb->pcb_pl1vec = NULL; 2015129198Scognet} 2016129198Scognet 2017129198Scognetvoid 2018129198Scognetpmap_activate(struct thread *td) 2019129198Scognet{ 2020129198Scognet pmap_t pm; 2021129198Scognet struct pcb *pcb; 2022129198Scognet 2023135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2024129198Scognet pcb = td->td_pcb; 2025129198Scognet 2026129198Scognet critical_enter(); 2027129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2028129198Scognet 2029129198Scognet if (td == curthread) { 2030129198Scognet u_int cur_dacr, cur_ttb; 2031129198Scognet 2032129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2033129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2034129198Scognet 2035129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2036129198Scognet 2037129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2038129198Scognet cur_dacr == pcb->pcb_dacr) { 2039129198Scognet /* 2040129198Scognet * No need to switch address spaces. 2041129198Scognet */ 2042129198Scognet critical_exit(); 2043129198Scognet return; 2044129198Scognet } 2045129198Scognet 2046129198Scognet 2047129198Scognet /* 2048129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2049129198Scognet * to 'vector_page' in the incoming L1 table before switching 2050129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2051129198Scognet * domain faults!) will jump into hyperspace. 2052129198Scognet */ 2053129198Scognet if (pcb->pcb_pl1vec) { 2054129198Scognet 2055129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2056129198Scognet /* 2057129198Scognet * Don't need to PTE_SYNC() at this point since 2058129198Scognet * cpu_setttb() is about to flush both the cache 2059129198Scognet * and the TLB. 2060129198Scognet */ 2061129198Scognet } 2062129198Scognet 2063129198Scognet cpu_domains(pcb->pcb_dacr); 2064129198Scognet cpu_setttb(pcb->pcb_pagedir); 2065129198Scognet } 2066129198Scognet critical_exit(); 2067129198Scognet} 2068129198Scognet 2069129198Scognetstatic int 2070129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2071129198Scognet{ 2072129198Scognet pd_entry_t *pdep, pde; 2073129198Scognet pt_entry_t *ptep, pte; 2074129198Scognet vm_offset_t pa; 2075129198Scognet int rv = 0; 2076129198Scognet 2077129198Scognet /* 2078129198Scognet * Make sure the descriptor itself has the correct cache mode 2079129198Scognet */ 2080129198Scognet pdep = &kl1[L1_IDX(va)]; 2081129198Scognet pde = *pdep; 2082129198Scognet 2083129198Scognet if (l1pte_section_p(pde)) { 2084129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2085129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2086129198Scognet pte_l1_s_cache_mode_pt; 2087129198Scognet PTE_SYNC(pdep); 2088129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2089129198Scognet sizeof(*pdep)); 2090183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)pdep, 2091183838Sraj sizeof(*pdep)); 2092129198Scognet rv = 1; 2093129198Scognet } 2094129198Scognet } else { 2095129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2096129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2097129198Scognet if (ptep == NULL) 2098129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2099129198Scognet 2100129198Scognet ptep = &ptep[l2pte_index(va)]; 2101129198Scognet pte = *ptep; 2102129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2103129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2104129198Scognet pte_l2_s_cache_mode_pt; 2105129198Scognet PTE_SYNC(ptep); 2106129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2107129198Scognet sizeof(*ptep)); 2108183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)ptep, 2109183838Sraj sizeof(*ptep)); 2110129198Scognet rv = 1; 2111129198Scognet } 2112129198Scognet } 2113129198Scognet 2114129198Scognet return (rv); 2115129198Scognet} 2116129198Scognet 2117129198Scognetstatic void 2118236991Simppmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2119129198Scognet pt_entry_t **ptep) 2120129198Scognet{ 2121129198Scognet vm_offset_t va = *availp; 2122129198Scognet struct l2_bucket *l2b; 2123129198Scognet 2124129198Scognet if (ptep) { 2125129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2126129198Scognet if (l2b == NULL) 2127129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2128129198Scognet 2129129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2130129198Scognet } 2131129198Scognet 2132129198Scognet *vap = va; 2133129198Scognet *availp = va + (PAGE_SIZE * pages); 2134129198Scognet} 2135129198Scognet 2136129198Scognet/* 2137129198Scognet * Bootstrap the system enough to run with virtual memory. 2138129198Scognet * 2139129198Scognet * On the arm this is called after mapping has already been enabled 2140129198Scognet * and just syncs the pmap module with what has already been done. 2141129198Scognet * [We can't call it easily with mapping off since the kernel is not 2142129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2143129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2144129198Scognet * (physical) address starting relative to 0] 2145129198Scognet */ 2146129198Scognet#define PMAP_STATIC_L2_SIZE 16 2147129198Scognetvoid 2148247046Salcpmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt) 2149129198Scognet{ 2150129198Scognet static struct l1_ttable static_l1; 2151129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2152129198Scognet struct l1_ttable *l1 = &static_l1; 2153129198Scognet struct l2_dtable *l2; 2154129198Scognet struct l2_bucket *l2b; 2155129198Scognet pd_entry_t pde; 2156129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2157129198Scognet pt_entry_t *ptep; 2158129198Scognet vm_paddr_t pa; 2159129198Scognet vm_offset_t va; 2160135641Scognet vm_size_t size; 2161129198Scognet int l1idx, l2idx, l2next = 0; 2162129198Scognet 2163197770Sstas PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", 2164247046Salc firstaddr, vm_max_kernel_address)); 2165283366Sandrew 2166129198Scognet virtual_avail = firstaddr; 2167129198Scognet kernel_pmap->pm_l1 = l1; 2168150865Scognet kernel_l1pa = l1pt->pv_pa; 2169283366Sandrew 2170143192Scognet /* 2171129198Scognet * Scan the L1 translation table created by initarm() and create 2172129198Scognet * the required metadata for all valid mappings found in it. 2173129198Scognet */ 2174129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2175129198Scognet pde = kernel_l1pt[l1idx]; 2176129198Scognet 2177129198Scognet /* 2178129198Scognet * We're only interested in Coarse mappings. 2179129198Scognet * pmap_extract() can deal with section mappings without 2180129198Scognet * recourse to checking L2 metadata. 2181129198Scognet */ 2182129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2183129198Scognet continue; 2184129198Scognet 2185129198Scognet /* 2186129198Scognet * Lookup the KVA of this L2 descriptor table 2187129198Scognet */ 2188129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2189129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2190283366Sandrew 2191129198Scognet if (ptep == NULL) { 2192129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2193129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2194129198Scognet } 2195129198Scognet 2196129198Scognet /* 2197129198Scognet * Fetch the associated L2 metadata structure. 2198129198Scognet * Allocate a new one if necessary. 2199129198Scognet */ 2200129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2201129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2202129198Scognet panic("pmap_bootstrap: out of static L2s"); 2203236991Simp kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2204129198Scognet &static_l2[l2next++]; 2205129198Scognet } 2206129198Scognet 2207129198Scognet /* 2208129198Scognet * One more L1 slot tracked... 2209129198Scognet */ 2210129198Scognet l2->l2_occupancy++; 2211129198Scognet 2212129198Scognet /* 2213129198Scognet * Fill in the details of the L2 descriptor in the 2214129198Scognet * appropriate bucket. 2215129198Scognet */ 2216129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2217129198Scognet l2b->l2b_kva = ptep; 2218129198Scognet l2b->l2b_phys = pa; 2219129198Scognet l2b->l2b_l1idx = l1idx; 2220129198Scognet 2221129198Scognet /* 2222129198Scognet * Establish an initial occupancy count for this descriptor 2223129198Scognet */ 2224129198Scognet for (l2idx = 0; 2225129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2226129198Scognet l2idx++) { 2227129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2228129198Scognet l2b->l2b_occupancy++; 2229129198Scognet } 2230129198Scognet } 2231129198Scognet 2232129198Scognet /* 2233129198Scognet * Make sure the descriptor itself has the correct cache mode. 2234129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2235129198Scognet * should consider this a clue to fix up their initarm() 2236129198Scognet * function. :) 2237129198Scognet */ 2238129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2239129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2240129198Scognet "L2 pte @ %p\n", ptep); 2241129198Scognet } 2242129198Scognet } 2243129198Scognet 2244283366Sandrew 2245129198Scognet /* 2246129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2247129198Scognet * a page table. Bitch if it is not correctly set. 2248129198Scognet */ 2249129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2250129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2251129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2252129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2253129198Scognet "primary L1 @ 0x%x\n", va); 2254129198Scognet } 2255129198Scognet 2256129198Scognet cpu_dcache_wbinv_all(); 2257183838Sraj cpu_l2cache_wbinv_all(); 2258129198Scognet cpu_tlb_flushID(); 2259129198Scognet cpu_cpwait(); 2260129198Scognet 2261159325Salc PMAP_LOCK_INIT(kernel_pmap); 2262222813Sattilio CPU_FILL(&kernel_pmap->pm_active); 2263129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2264144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2265239934Salc 2266239934Salc /* 2267239934Salc * Initialize the global pv list lock. 2268239934Salc */ 2269239934Salc rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE); 2270283366Sandrew 2271129198Scognet /* 2272129198Scognet * Reserve some special page table entries/VA space for temporary 2273129198Scognet * mapping of pages. 2274129198Scognet */ 2275129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2276129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2277129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2278129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2279247046Salc size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) / 2280247046Salc L1_S_SIZE; 2281135641Scognet pmap_alloc_specials(&virtual_avail, 2282135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2283135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2284283366Sandrew 2285135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2286135641Scognet pmap_alloc_specials(&virtual_avail, 2287135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2288135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2289135641Scognet 2290137362Scognet pmap_alloc_specials(&virtual_avail, 2291137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2292184728Sraj pmap_alloc_specials(&virtual_avail, 2293184728Sraj MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL); 2294135641Scognet SLIST_INIT(&l1_list); 2295129198Scognet TAILQ_INIT(&l1_lru_list); 2296129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2297129198Scognet pmap_init_l1(l1, kernel_l1pt); 2298129198Scognet cpu_dcache_wbinv_all(); 2299183838Sraj cpu_l2cache_wbinv_all(); 2300129198Scognet 2301129198Scognet virtual_avail = round_page(virtual_avail); 2302247046Salc virtual_end = vm_max_kernel_address; 2303135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2304159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2305156191Scognet 2306161105Scognet pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 2307129198Scognet} 2308129198Scognet 2309129198Scognet/*************************************************** 2310129198Scognet * Pmap allocation/deallocation routines. 2311129198Scognet ***************************************************/ 2312129198Scognet 2313129198Scognet/* 2314129198Scognet * Release any resources held by the given physical map. 2315129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2316129198Scognet * Should only be called if the map contains no valid mappings. 2317129198Scognet */ 2318129198Scognetvoid 2319129198Scognetpmap_release(pmap_t pmap) 2320129198Scognet{ 2321135641Scognet struct pcb *pcb; 2322283366Sandrew 2323135641Scognet pmap_idcache_wbinv_all(pmap); 2324183838Sraj cpu_l2cache_wbinv_all(); 2325135641Scognet pmap_tlb_flushID(pmap); 2326135641Scognet cpu_cpwait(); 2327135641Scognet if (vector_page < KERNBASE) { 2328135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2329135641Scognet pcb = thread0.td_pcb; 2330135641Scognet if (pmap_is_current(pmap)) { 2331135641Scognet /* 2332135641Scognet * Frob the L1 entry corresponding to the vector 2333135641Scognet * page so that it contains the kernel pmap's domain 2334135641Scognet * number. This will ensure pmap_remove() does not 2335135641Scognet * pull the current vector page out from under us. 2336135641Scognet */ 2337135641Scognet critical_enter(); 2338135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2339135641Scognet cpu_domains(pcb->pcb_dacr); 2340135641Scognet cpu_setttb(pcb->pcb_pagedir); 2341135641Scognet critical_exit(); 2342135641Scognet } 2343135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2344135641Scognet /* 2345135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2346135641Scognet * since this process has no remaining mappings of its own. 2347135641Scognet */ 2348135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2349135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2350135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2351135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2352135641Scognet 2353135641Scognet } 2354129198Scognet pmap_free_l1(pmap); 2355283366Sandrew 2356129198Scognet dprintf("pmap_release()\n"); 2357129198Scognet} 2358129198Scognet 2359129198Scognet 2360135641Scognet 2361129198Scognet/* 2362135641Scognet * Helper function for pmap_grow_l2_bucket() 2363135641Scognet */ 2364135641Scognetstatic __inline int 2365135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2366135641Scognet{ 2367135641Scognet struct l2_bucket *l2b; 2368135641Scognet pt_entry_t *ptep; 2369135641Scognet vm_paddr_t pa; 2370135641Scognet struct vm_page *pg; 2371283366Sandrew 2372150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2373135641Scognet if (pg == NULL) 2374135641Scognet return (1); 2375135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2376135641Scognet 2377135641Scognet if (pap) 2378135641Scognet *pap = pa; 2379135641Scognet 2380135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2381135641Scognet 2382135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2383135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2384135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2385135641Scognet PTE_SYNC(ptep); 2386135641Scognet return (0); 2387135641Scognet} 2388135641Scognet 2389135641Scognet/* 2390135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2391135641Scognet * used by pmap_growkernel(). 2392135641Scognet */ 2393135641Scognetstatic __inline struct l2_bucket * 2394135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2395135641Scognet{ 2396135641Scognet struct l2_dtable *l2; 2397135641Scognet struct l2_bucket *l2b; 2398135641Scognet struct l1_ttable *l1; 2399135641Scognet pd_entry_t *pl1pd; 2400135641Scognet u_short l1idx; 2401135641Scognet vm_offset_t nva; 2402135641Scognet 2403135641Scognet l1idx = L1_IDX(va); 2404135641Scognet 2405135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2406135641Scognet /* 2407135641Scognet * No mapping at this address, as there is 2408135641Scognet * no entry in the L1 table. 2409135641Scognet * Need to allocate a new l2_dtable. 2410135641Scognet */ 2411135641Scognet nva = pmap_kernel_l2dtable_kva; 2412135641Scognet if ((nva & PAGE_MASK) == 0) { 2413135641Scognet /* 2414135641Scognet * Need to allocate a backing page 2415135641Scognet */ 2416135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2417135641Scognet return (NULL); 2418135641Scognet } 2419135641Scognet 2420135641Scognet l2 = (struct l2_dtable *)nva; 2421135641Scognet nva += sizeof(struct l2_dtable); 2422135641Scognet 2423236991Simp if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2424135641Scognet PAGE_MASK)) { 2425135641Scognet /* 2426135641Scognet * The new l2_dtable straddles a page boundary. 2427135641Scognet * Map in another page to cover it. 2428135641Scognet */ 2429135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2430135641Scognet return (NULL); 2431135641Scognet } 2432135641Scognet 2433135641Scognet pmap_kernel_l2dtable_kva = nva; 2434135641Scognet 2435135641Scognet /* 2436135641Scognet * Link it into the parent pmap 2437135641Scognet */ 2438135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2439150865Scognet memset(l2, 0, sizeof(*l2)); 2440135641Scognet } 2441135641Scognet 2442135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2443135641Scognet 2444135641Scognet /* 2445135641Scognet * Fetch pointer to the L2 page table associated with the address. 2446135641Scognet */ 2447135641Scognet if (l2b->l2b_kva == NULL) { 2448135641Scognet pt_entry_t *ptep; 2449135641Scognet 2450135641Scognet /* 2451135641Scognet * No L2 page table has been allocated. Chances are, this 2452135641Scognet * is because we just allocated the l2_dtable, above. 2453135641Scognet */ 2454135641Scognet nva = pmap_kernel_l2ptp_kva; 2455135641Scognet ptep = (pt_entry_t *)nva; 2456135641Scognet if ((nva & PAGE_MASK) == 0) { 2457135641Scognet /* 2458135641Scognet * Need to allocate a backing page 2459135641Scognet */ 2460135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2461135641Scognet &pmap_kernel_l2ptp_phys)) 2462135641Scognet return (NULL); 2463135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2464135641Scognet } 2465150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2466135641Scognet l2->l2_occupancy++; 2467135641Scognet l2b->l2b_kva = ptep; 2468135641Scognet l2b->l2b_l1idx = l1idx; 2469135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2470135641Scognet 2471135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2472135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2473135641Scognet } 2474135641Scognet 2475135641Scognet /* Distribute new L1 entry to all other L1s */ 2476135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2477145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2478135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2479135641Scognet L1_C_PROTO; 2480135641Scognet PTE_SYNC(pl1pd); 2481135641Scognet } 2482135641Scognet 2483135641Scognet return (l2b); 2484135641Scognet} 2485135641Scognet 2486135641Scognet 2487135641Scognet/* 2488129198Scognet * grow the number of kernel page table entries, if needed 2489129198Scognet */ 2490129198Scognetvoid 2491129198Scognetpmap_growkernel(vm_offset_t addr) 2492129198Scognet{ 2493135641Scognet pmap_t kpm = pmap_kernel(); 2494129198Scognet 2495135641Scognet if (addr <= pmap_curmaxkvaddr) 2496135641Scognet return; /* we are OK */ 2497135641Scognet 2498135641Scognet /* 2499135641Scognet * whoops! we need to add kernel PTPs 2500135641Scognet */ 2501135641Scognet 2502135641Scognet /* Map 1MB at a time */ 2503135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2504135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2505135641Scognet 2506135641Scognet /* 2507135641Scognet * flush out the cache, expensive but growkernel will happen so 2508135641Scognet * rarely 2509135641Scognet */ 2510135641Scognet cpu_dcache_wbinv_all(); 2511183838Sraj cpu_l2cache_wbinv_all(); 2512135641Scognet cpu_tlb_flushD(); 2513135641Scognet cpu_cpwait(); 2514135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2515129198Scognet} 2516129198Scognet 2517129198Scognet 2518129198Scognet/* 2519129198Scognet * Remove all pages from specified address space 2520129198Scognet * this aids process exit speeds. Also, this code 2521129198Scognet * is special cased for current process only, but 2522129198Scognet * can have the more generic (and slightly slower) 2523129198Scognet * mode enabled. This is much faster than pmap_remove 2524129198Scognet * in the case of running down an entire address space. 2525129198Scognet */ 2526129198Scognetvoid 2527157443Speterpmap_remove_pages(pmap_t pmap) 2528129198Scognet{ 2529144760Scognet struct pv_entry *pv, *npv; 2530144760Scognet struct l2_bucket *l2b = NULL; 2531144760Scognet vm_page_t m; 2532144760Scognet pt_entry_t *pt; 2533283366Sandrew 2534239934Salc rw_wlock(&pvh_global_lock); 2535159352Salc PMAP_LOCK(pmap); 2536175840Scognet cpu_idcache_wbinv_all(); 2537183838Sraj cpu_l2cache_wbinv_all(); 2538144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2539194459Sthompsa if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) { 2540194459Sthompsa /* Cannot remove wired or unmanaged pages now. */ 2541144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2542144760Scognet continue; 2543144760Scognet } 2544144760Scognet pmap->pm_stats.resident_count--; 2545144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2546144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2547144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2548144760Scognet m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2549164079Scognet KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2550144760Scognet *pt = 0; 2551144760Scognet PTE_SYNC(pt); 2552144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2553144760Scognet pmap_nuke_pv(m, pmap, pv); 2554150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2555225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2556144760Scognet pmap_free_pv_entry(pv); 2557164874Scognet pmap_free_l2_bucket(pmap, l2b, 1); 2558144760Scognet } 2559239934Salc rw_wunlock(&pvh_global_lock); 2560135641Scognet cpu_tlb_flushID(); 2561135641Scognet cpu_cpwait(); 2562159352Salc PMAP_UNLOCK(pmap); 2563129198Scognet} 2564129198Scognet 2565129198Scognet 2566129198Scognet/*************************************************** 2567129198Scognet * Low level mapping routines..... 2568129198Scognet ***************************************************/ 2569129198Scognet 2570171620Scognet#ifdef ARM_HAVE_SUPERSECTIONS 2571170582Scognet/* Map a super section into the KVA. */ 2572170582Scognet 2573170582Scognetvoid 2574170582Scognetpmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags) 2575170582Scognet{ 2576171620Scognet pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) | 2577171620Scognet (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL, 2578170582Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2579283366Sandrew struct l1_ttable *l1; 2580171620Scognet vm_offset_t va0, va_end; 2581170582Scognet 2582170582Scognet KASSERT(((va | pa) & L1_SUP_OFFSET) == 0, 2583171620Scognet ("Not a valid super section mapping")); 2584170582Scognet if (flags & SECTION_CACHE) 2585170582Scognet pd |= pte_l1_s_cache_mode; 2586170582Scognet else if (flags & SECTION_PT) 2587170582Scognet pd |= pte_l1_s_cache_mode_pt; 2588171620Scognet va0 = va & L1_SUP_FRAME; 2589170582Scognet va_end = va + L1_SUP_SIZE; 2590170582Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2591171620Scognet va = va0; 2592170582Scognet for (; va < va_end; va += L1_S_SIZE) { 2593170582Scognet l1->l1_kva[L1_IDX(va)] = pd; 2594170582Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2595170582Scognet } 2596170582Scognet } 2597170582Scognet} 2598171620Scognet#endif 2599170582Scognet 2600147114Scognet/* Map a section into the KVA. */ 2601147114Scognet 2602147114Scognetvoid 2603147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2604147114Scognet{ 2605147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2606147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2607147114Scognet struct l1_ttable *l1; 2608147114Scognet 2609147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2610147114Scognet ("Not a valid section mapping")); 2611147114Scognet if (flags & SECTION_CACHE) 2612147114Scognet pd |= pte_l1_s_cache_mode; 2613147114Scognet else if (flags & SECTION_PT) 2614147114Scognet pd |= pte_l1_s_cache_mode_pt; 2615147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2616147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2617147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2618147114Scognet } 2619147114Scognet} 2620147114Scognet 2621129198Scognet/* 2622184728Sraj * Make a temporary mapping for a physical address. This is only intended 2623184728Sraj * to be used for panic dumps. 2624184728Sraj */ 2625184728Srajvoid * 2626271422Sandrewpmap_kenter_temporary(vm_paddr_t pa, int i) 2627184728Sraj{ 2628184728Sraj vm_offset_t va; 2629184728Sraj 2630184728Sraj va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 2631184728Sraj pmap_kenter(va, pa); 2632184728Sraj return ((void *)crashdumpmap); 2633184728Sraj} 2634184728Sraj 2635184728Sraj/* 2636129198Scognet * add a wired page to the kva 2637129198Scognet * note that in order for the mapping to take effect -- you 2638129198Scognet * should do a invltlb after doing the pmap_kenter... 2639129198Scognet */ 2640135641Scognetstatic PMAP_INLINE void 2641135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2642129198Scognet{ 2643129198Scognet struct l2_bucket *l2b; 2644129198Scognet pt_entry_t *pte; 2645129198Scognet pt_entry_t opte; 2646194459Sthompsa struct pv_entry *pve; 2647194459Sthompsa vm_page_t m; 2648194459Sthompsa 2649129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2650129198Scognet (uint32_t) va, (uint32_t) pa)); 2651129198Scognet 2652129198Scognet 2653129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2654135641Scognet if (l2b == NULL) 2655135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2656129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2657129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2658129198Scognet opte = *pte; 2659129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2660129198Scognet (uint32_t) pte, opte, *pte)); 2661129198Scognet if (l2pte_valid(opte)) { 2662194459Sthompsa pmap_kremove(va); 2663135641Scognet } else { 2664129198Scognet if (opte == 0) 2665129198Scognet l2b->l2b_occupancy++; 2666135641Scognet } 2667236991Simp *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2668135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2669135641Scognet if (flags & KENTER_CACHE) 2670135641Scognet *pte |= pte_l2_s_cache_mode; 2671142570Scognet if (flags & KENTER_USER) 2672142570Scognet *pte |= L2_S_PROT_U; 2673129198Scognet PTE_SYNC(pte); 2674194459Sthompsa 2675240166Salc /* 2676240166Salc * A kernel mapping may not be the page's only mapping, so create a PV 2677240166Salc * entry to ensure proper caching. 2678240166Salc * 2679240166Salc * The existence test for the pvzone is used to delay the recording of 2680240166Salc * kernel mappings until the VM system is fully initialized. 2681240166Salc * 2682240166Salc * This expects the physical memory to have a vm_page_array entry. 2683240166Salc */ 2684240166Salc if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) { 2685239934Salc rw_wlock(&pvh_global_lock); 2686240166Salc if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) { 2687194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 2688283366Sandrew panic("pmap_kenter_internal: no pv entries"); 2689194459Sthompsa PMAP_LOCK(pmap_kernel()); 2690194459Sthompsa pmap_enter_pv(m, pve, pmap_kernel(), va, 2691198341Smarcel PVF_WRITE | PVF_UNMAN); 2692194459Sthompsa pmap_fix_cache(m, pmap_kernel(), va); 2693194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2694194459Sthompsa } else { 2695194459Sthompsa m->md.pv_kva = va; 2696194459Sthompsa } 2697239934Salc rw_wunlock(&pvh_global_lock); 2698194459Sthompsa } 2699135641Scognet} 2700129198Scognet 2701135641Scognetvoid 2702135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2703135641Scognet{ 2704135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2705129198Scognet} 2706129198Scognet 2707142570Scognetvoid 2708156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2709156191Scognet{ 2710156191Scognet 2711156191Scognet pmap_kenter_internal(va, pa, 0); 2712156191Scognet} 2713156191Scognet 2714156191Scognetvoid 2715281369Sianpmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa) 2716257648Sian{ 2717281369Sian vm_offset_t sva; 2718257648Sian 2719283366Sandrew KASSERT((size & PAGE_MASK) == 0, 2720281369Sian ("%s: device mapping not page-sized", __func__)); 2721281369Sian 2722281369Sian sva = va; 2723281369Sian while (size != 0) { 2724281369Sian pmap_kenter_internal(va, pa, 0); 2725281369Sian va += PAGE_SIZE; 2726281369Sian pa += PAGE_SIZE; 2727281369Sian size -= PAGE_SIZE; 2728281369Sian } 2729257648Sian} 2730257648Sian 2731257648Sianvoid 2732281369Sianpmap_kremove_device(vm_offset_t va, vm_size_t size) 2733281369Sian{ 2734281369Sian vm_offset_t sva; 2735281369Sian 2736283366Sandrew KASSERT((size & PAGE_MASK) == 0, 2737281369Sian ("%s: device mapping not page-sized", __func__)); 2738281369Sian 2739281369Sian sva = va; 2740281369Sian while (size != 0) { 2741281369Sian pmap_kremove(va); 2742281369Sian va += PAGE_SIZE; 2743281369Sian size -= PAGE_SIZE; 2744281369Sian } 2745281369Sian} 2746281369Sian 2747281369Sianvoid 2748142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2749142570Scognet{ 2750143192Scognet 2751142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2752143192Scognet /* 2753143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2754143192Scognet * at the first use of the new address, or bad things will happen, 2755143192Scognet * as we use one of these addresses in the exception handlers. 2756143192Scognet */ 2757143192Scognet pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2758142570Scognet} 2759129198Scognet 2760240983Salcvm_paddr_t 2761240983Salcpmap_kextract(vm_offset_t va) 2762240983Salc{ 2763240983Salc 2764240983Salc return (pmap_extract_locked(kernel_pmap, va)); 2765240983Salc} 2766240983Salc 2767129198Scognet/* 2768194908Scognet * remove a page from the kernel pagetables 2769129198Scognet */ 2770169763Scognetvoid 2771129198Scognetpmap_kremove(vm_offset_t va) 2772129198Scognet{ 2773135641Scognet struct l2_bucket *l2b; 2774135641Scognet pt_entry_t *pte, opte; 2775194459Sthompsa struct pv_entry *pve; 2776194459Sthompsa vm_page_t m; 2777194459Sthompsa vm_offset_t pa; 2778283366Sandrew 2779135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2780145071Scognet if (!l2b) 2781145071Scognet return; 2782135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2783135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2784135641Scognet opte = *pte; 2785135641Scognet if (l2pte_valid(opte)) { 2786194459Sthompsa /* pa = vtophs(va) taken from pmap_extract() */ 2787194459Sthompsa switch (opte & L2_TYPE_MASK) { 2788194459Sthompsa case L2_TYPE_L: 2789194459Sthompsa pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET); 2790194459Sthompsa break; 2791194459Sthompsa default: 2792194459Sthompsa pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET); 2793194459Sthompsa break; 2794194459Sthompsa } 2795194459Sthompsa /* note: should never have to remove an allocation 2796194459Sthompsa * before the pvzone is initialized. 2797194459Sthompsa */ 2798239934Salc rw_wlock(&pvh_global_lock); 2799194459Sthompsa PMAP_LOCK(pmap_kernel()); 2800194459Sthompsa if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) && 2801194459Sthompsa (pve = pmap_remove_pv(m, pmap_kernel(), va))) 2802236991Simp pmap_free_pv_entry(pve); 2803194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2804239934Salc rw_wunlock(&pvh_global_lock); 2805195779Sraj va = va & ~PAGE_MASK; 2806135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2807183838Sraj cpu_l2cache_wbinv_range(va, PAGE_SIZE); 2808135641Scognet cpu_tlb_flushD_SE(va); 2809135641Scognet cpu_cpwait(); 2810144760Scognet *pte = 0; 2811135641Scognet } 2812129198Scognet} 2813129198Scognet 2814129198Scognet 2815129198Scognet/* 2816129198Scognet * Used to map a range of physical addresses into kernel 2817129198Scognet * virtual address space. 2818129198Scognet * 2819129198Scognet * The value passed in '*virt' is a suggested virtual address for 2820129198Scognet * the mapping. Architectures which can support a direct-mapped 2821129198Scognet * physical to virtual region can return the appropriate address 2822129198Scognet * within that region, leaving '*virt' unchanged. Other 2823129198Scognet * architectures should map the pages starting at '*virt' and 2824129198Scognet * update '*virt' with the first usable address after the mapped 2825129198Scognet * region. 2826129198Scognet */ 2827129198Scognetvm_offset_t 2828129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2829129198Scognet{ 2830129198Scognet vm_offset_t sva = *virt; 2831129198Scognet vm_offset_t va = sva; 2832129198Scognet 2833129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2834129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2835129198Scognet prot)); 2836236991Simp 2837129198Scognet while (start < end) { 2838129198Scognet pmap_kenter(va, start); 2839129198Scognet va += PAGE_SIZE; 2840129198Scognet start += PAGE_SIZE; 2841129198Scognet } 2842129198Scognet *virt = va; 2843129198Scognet return (sva); 2844129198Scognet} 2845129198Scognet 2846143724Scognetstatic void 2847150865Scognetpmap_wb_page(vm_page_t m) 2848143724Scognet{ 2849143724Scognet struct pv_entry *pv; 2850129198Scognet 2851143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2852150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2853144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2854143724Scognet} 2855143724Scognet 2856150865Scognetstatic void 2857150865Scognetpmap_inv_page(vm_page_t m) 2858150865Scognet{ 2859150865Scognet struct pv_entry *pv; 2860150865Scognet 2861150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2862150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2863150865Scognet} 2864129198Scognet/* 2865129198Scognet * Add a list of wired pages to the kva 2866129198Scognet * this routine is only used for temporary 2867129198Scognet * kernel mappings that do not need to have 2868129198Scognet * page modification or references recorded. 2869129198Scognet * Note that old mappings are simply written 2870129198Scognet * over. The page *must* be wired. 2871129198Scognet */ 2872129198Scognetvoid 2873129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2874129198Scognet{ 2875129198Scognet int i; 2876129198Scognet 2877129198Scognet for (i = 0; i < count; i++) { 2878150865Scognet pmap_wb_page(m[i]); 2879236991Simp pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2880135641Scognet KENTER_CACHE); 2881129198Scognet va += PAGE_SIZE; 2882129198Scognet } 2883129198Scognet} 2884129198Scognet 2885129198Scognet 2886129198Scognet/* 2887129198Scognet * this routine jerks page mappings from the 2888129198Scognet * kernel -- it is meant only for temporary mappings. 2889129198Scognet */ 2890129198Scognetvoid 2891129198Scognetpmap_qremove(vm_offset_t va, int count) 2892129198Scognet{ 2893146596Scognet vm_paddr_t pa; 2894129198Scognet int i; 2895129198Scognet 2896129198Scognet for (i = 0; i < count; i++) { 2897146596Scognet pa = vtophys(va); 2898146596Scognet if (pa) { 2899150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 2900146596Scognet pmap_kremove(va); 2901146596Scognet } 2902129198Scognet va += PAGE_SIZE; 2903129198Scognet } 2904129198Scognet} 2905129198Scognet 2906129198Scognet 2907129198Scognet/* 2908129198Scognet * pmap_object_init_pt preloads the ptes for a given object 2909129198Scognet * into the specified pmap. This eliminates the blast of soft 2910129198Scognet * faults on process startup and immediately after an mmap. 2911129198Scognet */ 2912129198Scognetvoid 2913129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 2914129198Scognet vm_pindex_t pindex, vm_size_t size) 2915129198Scognet{ 2916157156Scognet 2917248084Sattilio VM_OBJECT_ASSERT_WLOCKED(object); 2918195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2919157156Scognet ("pmap_object_init_pt: non-device object")); 2920129198Scognet} 2921129198Scognet 2922129198Scognet 2923129198Scognet/* 2924129198Scognet * pmap_is_prefaultable: 2925129198Scognet * 2926129198Scognet * Return whether or not the specified virtual address is elgible 2927129198Scognet * for prefault. 2928129198Scognet */ 2929129198Scognetboolean_t 2930129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2931129198Scognet{ 2932135641Scognet pd_entry_t *pde; 2933129198Scognet pt_entry_t *pte; 2934129198Scognet 2935135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 2936135641Scognet return (FALSE); 2937159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 2938135641Scognet if (*pte == 0) 2939135641Scognet return (TRUE); 2940135641Scognet return (FALSE); 2941129198Scognet} 2942129198Scognet 2943129198Scognet/* 2944129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 2945129198Scognet * Returns TRUE if the mapping exists, else FALSE. 2946129198Scognet * 2947129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 2948129198Scognet * It is not safe to take any pmap locks here, since we could be right 2949129198Scognet * in the middle of debugging the pmap anyway... 2950129198Scognet * 2951129198Scognet * It is possible for this routine to return FALSE even though a valid 2952129198Scognet * mapping does exist. This is because we don't lock, so the metadata 2953129198Scognet * state may be inconsistent. 2954129198Scognet * 2955129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 2956129198Scognet * a "section" mapping. 2957129198Scognet */ 2958129198Scognetboolean_t 2959129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 2960129198Scognet{ 2961129198Scognet struct l2_dtable *l2; 2962129198Scognet pd_entry_t *pl1pd, l1pd; 2963129198Scognet pt_entry_t *ptep; 2964129198Scognet u_short l1idx; 2965129198Scognet 2966129198Scognet if (pm->pm_l1 == NULL) 2967129198Scognet return (FALSE); 2968129198Scognet 2969129198Scognet l1idx = L1_IDX(va); 2970129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2971129198Scognet l1pd = *pl1pd; 2972129198Scognet 2973129198Scognet if (l1pte_section_p(l1pd)) { 2974129198Scognet *ptp = NULL; 2975129198Scognet return (TRUE); 2976129198Scognet } 2977129198Scognet 2978129198Scognet if (pm->pm_l2 == NULL) 2979129198Scognet return (FALSE); 2980129198Scognet 2981129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 2982129198Scognet 2983129198Scognet if (l2 == NULL || 2984129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2985129198Scognet return (FALSE); 2986129198Scognet } 2987129198Scognet 2988129198Scognet *ptp = &ptep[l2pte_index(va)]; 2989129198Scognet return (TRUE); 2990129198Scognet} 2991129198Scognet 2992129198Scognet/* 2993129198Scognet * Routine: pmap_remove_all 2994129198Scognet * Function: 2995129198Scognet * Removes this physical page from 2996129198Scognet * all physical maps in which it resides. 2997129198Scognet * Reflects back modify bits to the pager. 2998129198Scognet * 2999129198Scognet * Notes: 3000129198Scognet * Original versions of this routine were very 3001129198Scognet * inefficient because they iteratively called 3002129198Scognet * pmap_remove (slow...) 3003129198Scognet */ 3004129198Scognetvoid 3005129198Scognetpmap_remove_all(vm_page_t m) 3006129198Scognet{ 3007129198Scognet pv_entry_t pv; 3008188019Scognet pt_entry_t *ptep; 3009135641Scognet struct l2_bucket *l2b; 3010135641Scognet boolean_t flush = FALSE; 3011135641Scognet pmap_t curpm; 3012135641Scognet int flags = 0; 3013129198Scognet 3014224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3015223677Salc ("pmap_remove_all: page %p is not managed", m)); 3016135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3017135641Scognet return; 3018239934Salc rw_wlock(&pvh_global_lock); 3019267408Sjmg 3020267408Sjmg /* 3021267408Sjmg * XXX This call shouldn't exist. Iterating over the PV list twice, 3022267408Sjmg * once in pmap_clearbit() and again below, is both unnecessary and 3023267408Sjmg * inefficient. The below code should itself write back the cache 3024267408Sjmg * entry before it destroys the mapping. 3025267408Sjmg */ 3026267408Sjmg pmap_clearbit(m, PVF_WRITE); 3027135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3028129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3029135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3030135641Scognet pv->pv_pmap == pmap_kernel())) 3031135641Scognet flush = TRUE; 3032193712Sraj 3033159352Salc PMAP_LOCK(pv->pv_pmap); 3034193712Sraj /* 3035267408Sjmg * Cached contents were written-back in pmap_clearbit(), 3036193712Sraj * but we still have to invalidate the cache entry to make 3037193712Sraj * sure stale data are not retrieved when another page will be 3038193712Sraj * mapped under this virtual address. 3039193712Sraj */ 3040193712Sraj if (pmap_is_current(pv->pv_pmap)) { 3041193712Sraj cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE); 3042203637Sraj if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va)) 3043203637Sraj cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE); 3044193712Sraj } 3045193712Sraj 3046194459Sthompsa if (pv->pv_flags & PVF_UNMAN) { 3047194459Sthompsa /* remove the pv entry, but do not remove the mapping 3048194459Sthompsa * and remember this is a kernel mapped page 3049194459Sthompsa */ 3050194459Sthompsa m->md.pv_kva = pv->pv_va; 3051194459Sthompsa } else { 3052194459Sthompsa /* remove the mapping and pv entry */ 3053194459Sthompsa l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3054194459Sthompsa KASSERT(l2b != NULL, ("No l2 bucket")); 3055194459Sthompsa ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3056194459Sthompsa *ptep = 0; 3057194459Sthompsa PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3058194459Sthompsa pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3059194459Sthompsa pv->pv_pmap->pm_stats.resident_count--; 3060194459Sthompsa flags |= pv->pv_flags; 3061194459Sthompsa } 3062135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3063159352Salc PMAP_UNLOCK(pv->pv_pmap); 3064129198Scognet pmap_free_pv_entry(pv); 3065129198Scognet } 3066129198Scognet 3067135641Scognet if (flush) { 3068135641Scognet if (PV_BEEN_EXECD(flags)) 3069135641Scognet pmap_tlb_flushID(curpm); 3070135641Scognet else 3071135641Scognet pmap_tlb_flushD(curpm); 3072135641Scognet } 3073225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3074239934Salc rw_wunlock(&pvh_global_lock); 3075129198Scognet} 3076129198Scognet 3077129198Scognet 3078129198Scognet/* 3079129198Scognet * Set the physical protection on the 3080129198Scognet * specified range of this map as requested. 3081129198Scognet */ 3082129198Scognetvoid 3083129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3084129198Scognet{ 3085129198Scognet struct l2_bucket *l2b; 3086129198Scognet pt_entry_t *ptep, pte; 3087129198Scognet vm_offset_t next_bucket; 3088129198Scognet u_int flags; 3089129198Scognet int flush; 3090129198Scognet 3091183838Sraj CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x", 3092183838Sraj pm, sva, eva, prot); 3093183838Sraj 3094129198Scognet if ((prot & VM_PROT_READ) == 0) { 3095129198Scognet pmap_remove(pm, sva, eva); 3096129198Scognet return; 3097129198Scognet } 3098129198Scognet 3099129198Scognet if (prot & VM_PROT_WRITE) { 3100129198Scognet /* 3101129198Scognet * If this is a read->write transition, just ignore it and let 3102135641Scognet * vm_fault() take care of it later. 3103129198Scognet */ 3104129198Scognet return; 3105129198Scognet } 3106129198Scognet 3107239934Salc rw_wlock(&pvh_global_lock); 3108159352Salc PMAP_LOCK(pm); 3109129198Scognet 3110129198Scognet /* 3111129198Scognet * OK, at this point, we know we're doing write-protect operation. 3112129198Scognet * If the pmap is active, write-back the range. 3113129198Scognet */ 3114129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3115129198Scognet 3116129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3117129198Scognet flags = 0; 3118129198Scognet 3119129198Scognet while (sva < eva) { 3120129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3121129198Scognet if (next_bucket > eva) 3122129198Scognet next_bucket = eva; 3123129198Scognet 3124129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3125129198Scognet if (l2b == NULL) { 3126129198Scognet sva = next_bucket; 3127129198Scognet continue; 3128129198Scognet } 3129129198Scognet 3130129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3131129198Scognet 3132129198Scognet while (sva < next_bucket) { 3133129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3134129198Scognet struct vm_page *pg; 3135129198Scognet u_int f; 3136129198Scognet 3137129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3138129198Scognet pte &= ~L2_S_PROT_W; 3139129198Scognet *ptep = pte; 3140129198Scognet PTE_SYNC(ptep); 3141129198Scognet 3142239268Sgonzo if (!(pg->oflags & VPO_UNMANAGED)) { 3143239268Sgonzo f = pmap_modify_pv(pg, pm, sva, 3144239268Sgonzo PVF_WRITE, 0); 3145239268Sgonzo if (f & PVF_WRITE) 3146224049Smarcel vm_page_dirty(pg); 3147129198Scognet } else 3148239268Sgonzo f = 0; 3149129198Scognet 3150129198Scognet if (flush >= 0) { 3151129198Scognet flush++; 3152129198Scognet flags |= f; 3153129198Scognet } else 3154129198Scognet if (PV_BEEN_EXECD(f)) 3155129198Scognet pmap_tlb_flushID_SE(pm, sva); 3156129198Scognet else 3157129198Scognet if (PV_BEEN_REFD(f)) 3158129198Scognet pmap_tlb_flushD_SE(pm, sva); 3159129198Scognet } 3160129198Scognet 3161129198Scognet sva += PAGE_SIZE; 3162129198Scognet ptep++; 3163129198Scognet } 3164129198Scognet } 3165129198Scognet 3166129198Scognet 3167129198Scognet if (flush) { 3168129198Scognet if (PV_BEEN_EXECD(flags)) 3169129198Scognet pmap_tlb_flushID(pm); 3170129198Scognet else 3171129198Scognet if (PV_BEEN_REFD(flags)) 3172129198Scognet pmap_tlb_flushD(pm); 3173129198Scognet } 3174239934Salc rw_wunlock(&pvh_global_lock); 3175129198Scognet 3176159352Salc PMAP_UNLOCK(pm); 3177129198Scognet} 3178129198Scognet 3179129198Scognet 3180129198Scognet/* 3181129198Scognet * Insert the given physical page (p) at 3182129198Scognet * the specified virtual address (v) in the 3183129198Scognet * target physical map with the protection requested. 3184129198Scognet * 3185129198Scognet * If specified, the page will be wired down, meaning 3186129198Scognet * that the related pte can not be reclaimed. 3187129198Scognet * 3188129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3189129198Scognet * or lose information. That is, this routine must actually 3190129198Scognet * insert this page into the given map NOW. 3191129198Scognet */ 3192135641Scognet 3193269728Skibint 3194269728Skibpmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3195269728Skib u_int flags, int8_t psind __unused) 3196129198Scognet{ 3197269728Skib int rv; 3198159127Salc 3199239934Salc rw_wlock(&pvh_global_lock); 3200159352Salc PMAP_LOCK(pmap); 3201269728Skib rv = pmap_enter_locked(pmap, va, m, prot, flags); 3202239934Salc rw_wunlock(&pvh_global_lock); 3203159352Salc PMAP_UNLOCK(pmap); 3204269728Skib return (rv); 3205159127Salc} 3206159127Salc 3207159127Salc/* 3208240803Salc * The pvh global and pmap locks must be held. 3209159127Salc */ 3210269728Skibstatic int 3211159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3212269728Skib u_int flags) 3213159127Salc{ 3214135641Scognet struct l2_bucket *l2b = NULL; 3215129198Scognet struct vm_page *opg; 3216144760Scognet struct pv_entry *pve = NULL; 3217129198Scognet pt_entry_t *ptep, npte, opte; 3218129198Scognet u_int nflags; 3219129198Scognet u_int oflags; 3220129198Scognet vm_paddr_t pa; 3221129198Scognet 3222159325Salc PMAP_ASSERT_LOCKED(pmap); 3223239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 3224129198Scognet if (va == vector_page) { 3225129198Scognet pa = systempage.pv_pa; 3226129198Scognet m = NULL; 3227208688Salc } else { 3228269728Skib if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 3229269728Skib VM_OBJECT_ASSERT_LOCKED(m->object); 3230129198Scognet pa = VM_PAGE_TO_PHYS(m); 3231208688Salc } 3232129198Scognet nflags = 0; 3233129198Scognet if (prot & VM_PROT_WRITE) 3234129198Scognet nflags |= PVF_WRITE; 3235129198Scognet if (prot & VM_PROT_EXECUTE) 3236129198Scognet nflags |= PVF_EXEC; 3237269728Skib if ((flags & PMAP_ENTER_WIRED) != 0) 3238129198Scognet nflags |= PVF_WIRED; 3239129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3240269728Skib "flags = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, flags)); 3241236991Simp 3242135641Scognet if (pmap == pmap_kernel()) { 3243129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3244135641Scognet if (l2b == NULL) 3245135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3246160260Scognet } else { 3247160260Scognetdo_l2b_alloc: 3248129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3249160260Scognet if (l2b == NULL) { 3250269728Skib if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 3251160260Scognet PMAP_UNLOCK(pmap); 3252239934Salc rw_wunlock(&pvh_global_lock); 3253160260Scognet VM_WAIT; 3254239934Salc rw_wlock(&pvh_global_lock); 3255160260Scognet PMAP_LOCK(pmap); 3256160260Scognet goto do_l2b_alloc; 3257160260Scognet } 3258269728Skib return (KERN_RESOURCE_SHORTAGE); 3259160260Scognet } 3260160260Scognet } 3261160260Scognet 3262129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3263236991Simp 3264135641Scognet opte = *ptep; 3265129198Scognet npte = pa; 3266129198Scognet oflags = 0; 3267129198Scognet if (opte) { 3268129198Scognet /* 3269129198Scognet * There is already a mapping at this address. 3270129198Scognet * If the physical address is different, lookup the 3271129198Scognet * vm_page. 3272129198Scognet */ 3273129198Scognet if (l2pte_pa(opte) != pa) 3274129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3275129198Scognet else 3276129198Scognet opg = m; 3277129198Scognet } else 3278129198Scognet opg = NULL; 3279129198Scognet 3280135641Scognet if ((prot & (VM_PROT_ALL)) || 3281135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3282129198Scognet /* 3283135641Scognet * - The access type indicates that we don't need 3284135641Scognet * to do referenced emulation. 3285135641Scognet * OR 3286135641Scognet * - The physical page has already been referenced 3287135641Scognet * so no need to re-do referenced emulation here. 3288129198Scognet */ 3289135641Scognet npte |= L2_S_PROTO; 3290283366Sandrew 3291135641Scognet nflags |= PVF_REF; 3292283366Sandrew 3293144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3294144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3295129198Scognet /* 3296135641Scognet * This is a writable mapping, and the 3297135641Scognet * page's mod state indicates it has 3298135641Scognet * already been modified. Make it 3299135641Scognet * writable from the outset. 3300129198Scognet */ 3301135641Scognet nflags |= PVF_MOD; 3302157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3303144760Scognet vm_page_dirty(m); 3304129198Scognet } 3305144760Scognet if (m && opte) 3306225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 3307135641Scognet } else { 3308135641Scognet /* 3309135641Scognet * Need to do page referenced emulation. 3310135641Scognet */ 3311135641Scognet npte |= L2_TYPE_INV; 3312135641Scognet } 3313283366Sandrew 3314164229Salc if (prot & VM_PROT_WRITE) { 3315135641Scognet npte |= L2_S_PROT_W; 3316208846Salc if (m != NULL && 3317224746Skib (m->oflags & VPO_UNMANAGED) == 0) 3318225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 3319164229Salc } 3320244574Scognet if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 3321244414Scognet npte |= pte_l2_s_cache_mode; 3322135641Scognet if (m && m == opg) { 3323135641Scognet /* 3324135641Scognet * We're changing the attrs of an existing mapping. 3325135641Scognet */ 3326135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3327135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3328135641Scognet PVF_MOD | PVF_REF, nflags); 3329283366Sandrew 3330135641Scognet /* 3331135641Scognet * We may need to flush the cache if we're 3332135641Scognet * doing rw-ro... 3333135641Scognet */ 3334135641Scognet if (pmap_is_current(pmap) && 3335135641Scognet (oflags & PVF_NC) == 0 && 3336183838Sraj (opte & L2_S_PROT_W) != 0 && 3337203637Sraj (prot & VM_PROT_WRITE) == 0 && 3338203637Sraj (opte & L2_TYPE_MASK) != L2_TYPE_INV) { 3339135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3340203637Sraj cpu_l2cache_wb_range(va, PAGE_SIZE); 3341183838Sraj } 3342129198Scognet } else { 3343129198Scognet /* 3344135641Scognet * New mapping, or changing the backing page 3345135641Scognet * of an existing mapping. 3346129198Scognet */ 3347129198Scognet if (opg) { 3348129198Scognet /* 3349135641Scognet * Replacing an existing mapping with a new one. 3350135641Scognet * It is part of our managed memory so we 3351135641Scognet * must remove it from the PV list 3352129198Scognet */ 3353194459Sthompsa if ((pve = pmap_remove_pv(opg, pmap, va))) { 3354194459Sthompsa 3355194459Sthompsa /* note for patch: the oflags/invalidation was moved 3356194459Sthompsa * because PG_FICTITIOUS pages could free the pve 3357194459Sthompsa */ 3358194459Sthompsa oflags = pve->pv_flags; 3359135641Scognet /* 3360135641Scognet * If the old mapping was valid (ref/mod 3361135641Scognet * emulation creates 'invalid' mappings 3362135641Scognet * initially) then make sure to frob 3363135641Scognet * the cache. 3364135641Scognet */ 3365194459Sthompsa if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 3366135641Scognet if (PV_BEEN_EXECD(oflags)) { 3367129198Scognet pmap_idcache_wbinv_range(pmap, va, 3368129198Scognet PAGE_SIZE); 3369135641Scognet } else 3370135641Scognet if (PV_BEEN_REFD(oflags)) { 3371135641Scognet pmap_dcache_wb_range(pmap, va, 3372135641Scognet PAGE_SIZE, TRUE, 3373135641Scognet (oflags & PVF_WRITE) == 0); 3374135641Scognet } 3375194459Sthompsa } 3376194459Sthompsa 3377194459Sthompsa /* free/allocate a pv_entry for UNMANAGED pages if 3378194459Sthompsa * this physical page is not/is already mapped. 3379194459Sthompsa */ 3380194459Sthompsa 3381224746Skib if (m && (m->oflags & VPO_UNMANAGED) && 3382194459Sthompsa !m->md.pv_kva && 3383224746Skib TAILQ_EMPTY(&m->md.pv_list)) { 3384194459Sthompsa pmap_free_pv_entry(pve); 3385194459Sthompsa pve = NULL; 3386194459Sthompsa } 3387224746Skib } else if (m && 3388224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3389194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3390194459Sthompsa pve = pmap_get_pv_entry(); 3391224746Skib } else if (m && 3392224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3393194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3394194459Sthompsa pve = pmap_get_pv_entry(); 3395194459Sthompsa 3396224746Skib if (m) { 3397224746Skib if ((m->oflags & VPO_UNMANAGED)) { 3398194459Sthompsa if (!TAILQ_EMPTY(&m->md.pv_list) || 3399224746Skib m->md.pv_kva) { 3400194459Sthompsa KASSERT(pve != NULL, ("No pv")); 3401194459Sthompsa nflags |= PVF_UNMAN; 3402194459Sthompsa pmap_enter_pv(m, pve, pmap, va, nflags); 3403194459Sthompsa } else 3404194459Sthompsa m->md.pv_kva = va; 3405194459Sthompsa } else { 3406224746Skib KASSERT(va < kmi.clean_sva || 3407224746Skib va >= kmi.clean_eva, 3408224746Skib ("pmap_enter: managed mapping within the clean submap")); 3409224746Skib KASSERT(pve != NULL, ("No pv")); 3410224746Skib pmap_enter_pv(m, pve, pmap, va, nflags); 3411129198Scognet } 3412157970Scognet } 3413129198Scognet } 3414129198Scognet /* 3415129198Scognet * Make sure userland mappings get the right permissions 3416129198Scognet */ 3417129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3418129198Scognet npte |= L2_S_PROT_U; 3419129198Scognet } 3420129198Scognet 3421129198Scognet /* 3422129198Scognet * Keep the stats up to date 3423129198Scognet */ 3424129198Scognet if (opte == 0) { 3425129198Scognet l2b->l2b_occupancy++; 3426129198Scognet pmap->pm_stats.resident_count++; 3427236991Simp } 3428129198Scognet 3429129198Scognet /* 3430129198Scognet * If this is just a wiring change, the two PTEs will be 3431129198Scognet * identical, so there's no need to update the page table. 3432129198Scognet */ 3433129198Scognet if (npte != opte) { 3434135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3435129198Scognet 3436129198Scognet *ptep = npte; 3437129198Scognet if (is_cached) { 3438129198Scognet /* 3439129198Scognet * We only need to frob the cache/tlb if this pmap 3440129198Scognet * is current 3441129198Scognet */ 3442129198Scognet PTE_SYNC(ptep); 3443236991Simp if (L1_IDX(va) != L1_IDX(vector_page) && 3444129198Scognet l2pte_valid(npte)) { 3445129198Scognet /* 3446129198Scognet * This mapping is likely to be accessed as 3447129198Scognet * soon as we return to userland. Fix up the 3448129198Scognet * L1 entry to avoid taking another 3449129198Scognet * page/domain fault. 3450129198Scognet */ 3451129198Scognet pd_entry_t *pl1pd, l1pd; 3452129198Scognet 3453129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3454129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3455144760Scognet L1_C_PROTO; 3456129198Scognet if (*pl1pd != l1pd) { 3457129198Scognet *pl1pd = l1pd; 3458129198Scognet PTE_SYNC(pl1pd); 3459129198Scognet } 3460129198Scognet } 3461129198Scognet } 3462129198Scognet 3463129198Scognet if (PV_BEEN_EXECD(oflags)) 3464129198Scognet pmap_tlb_flushID_SE(pmap, va); 3465135641Scognet else if (PV_BEEN_REFD(oflags)) 3466129198Scognet pmap_tlb_flushD_SE(pmap, va); 3467129198Scognet 3468129198Scognet 3469157025Scognet if (m) 3470175840Scognet pmap_fix_cache(m, pmap, va); 3471129198Scognet } 3472269728Skib return (KERN_SUCCESS); 3473129198Scognet} 3474129198Scognet 3475129198Scognet/* 3476159303Salc * Maps a sequence of resident pages belonging to the same object. 3477159303Salc * The sequence begins with the given page m_start. This page is 3478159303Salc * mapped at the given virtual address start. Each subsequent page is 3479159303Salc * mapped at a virtual address that is offset from start by the same 3480159303Salc * amount as the page is offset from m_start within the object. The 3481159303Salc * last page in the sequence is the page with the largest offset from 3482159303Salc * m_start that can be mapped at a virtual address less than the given 3483159303Salc * virtual address end. Not every virtual page between start and end 3484159303Salc * is mapped; only those for which a resident page exists with the 3485159303Salc * corresponding offset from m_start are mapped. 3486159303Salc */ 3487159303Salcvoid 3488159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3489159303Salc vm_page_t m_start, vm_prot_t prot) 3490159303Salc{ 3491159303Salc vm_page_t m; 3492159303Salc vm_pindex_t diff, psize; 3493159303Salc 3494250884Sattilio VM_OBJECT_ASSERT_LOCKED(m_start->object); 3495250884Sattilio 3496159303Salc psize = atop(end - start); 3497159303Salc m = m_start; 3498239934Salc rw_wlock(&pvh_global_lock); 3499159325Salc PMAP_LOCK(pmap); 3500159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3501159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3502269728Skib (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP); 3503159303Salc m = TAILQ_NEXT(m, listq); 3504159303Salc } 3505239934Salc rw_wunlock(&pvh_global_lock); 3506159325Salc PMAP_UNLOCK(pmap); 3507159303Salc} 3508159303Salc 3509159303Salc/* 3510129198Scognet * this code makes some *MAJOR* assumptions: 3511129198Scognet * 1. Current pmap & pmap exists. 3512129198Scognet * 2. Not wired. 3513129198Scognet * 3. Read access. 3514129198Scognet * 4. No page table pages. 3515129198Scognet * but is *MUCH* faster than pmap_enter... 3516129198Scognet */ 3517129198Scognet 3518159627Supsvoid 3519159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3520129198Scognet{ 3521138897Salc 3522239934Salc rw_wlock(&pvh_global_lock); 3523159325Salc PMAP_LOCK(pmap); 3524159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3525269728Skib PMAP_ENTER_NOSLEEP); 3526239934Salc rw_wunlock(&pvh_global_lock); 3527159325Salc PMAP_UNLOCK(pmap); 3528129198Scognet} 3529129198Scognet 3530129198Scognet/* 3531268776Salc * Clear the wired attribute from the mappings for the specified range of 3532268776Salc * addresses in the given pmap. Every valid mapping within that range 3533268776Salc * must have the wired attribute set. In contrast, invalid mappings 3534268776Salc * cannot have the wired attribute set, so they are ignored. 3535268776Salc * 3536268776Salc * XXX Wired mappings of unmanaged pages cannot be counted by this pmap 3537268776Salc * implementation. 3538268776Salc */ 3539268776Salcvoid 3540268776Salcpmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3541268776Salc{ 3542268776Salc struct l2_bucket *l2b; 3543268776Salc pt_entry_t *ptep, pte; 3544268776Salc pv_entry_t pv; 3545268776Salc vm_offset_t next_bucket; 3546268776Salc vm_page_t m; 3547283366Sandrew 3548268776Salc rw_wlock(&pvh_global_lock); 3549268776Salc PMAP_LOCK(pmap); 3550268776Salc while (sva < eva) { 3551268776Salc next_bucket = L2_NEXT_BUCKET(sva); 3552268776Salc if (next_bucket > eva) 3553268776Salc next_bucket = eva; 3554268776Salc l2b = pmap_get_l2_bucket(pmap, sva); 3555268776Salc if (l2b == NULL) { 3556268776Salc sva = next_bucket; 3557268776Salc continue; 3558268776Salc } 3559268776Salc for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket; 3560268776Salc sva += PAGE_SIZE, ptep++) { 3561268776Salc if ((pte = *ptep) == 0 || 3562268776Salc (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL || 3563268776Salc (m->oflags & VPO_UNMANAGED) != 0) 3564268776Salc continue; 3565268776Salc pv = pmap_find_pv(m, pmap, sva); 3566268776Salc if ((pv->pv_flags & PVF_WIRED) == 0) 3567268776Salc panic("pmap_unwire: pv %p isn't wired", pv); 3568268776Salc pv->pv_flags &= ~PVF_WIRED; 3569268776Salc pmap->pm_stats.wired_count--; 3570268776Salc } 3571268776Salc } 3572268776Salc rw_wunlock(&pvh_global_lock); 3573268776Salc PMAP_UNLOCK(pmap); 3574268776Salc} 3575129198Scognet 3576268776Salc 3577129198Scognet/* 3578129198Scognet * Copy the range specified by src_addr/len 3579129198Scognet * from the source map to the range dst_addr/len 3580129198Scognet * in the destination map. 3581129198Scognet * 3582129198Scognet * This routine is only advisory and need not do anything. 3583129198Scognet */ 3584129198Scognetvoid 3585129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3586129198Scognet vm_size_t len, vm_offset_t src_addr) 3587129198Scognet{ 3588129198Scognet} 3589129198Scognet 3590129198Scognet 3591129198Scognet/* 3592129198Scognet * Routine: pmap_extract 3593129198Scognet * Function: 3594129198Scognet * Extract the physical page address associated 3595129198Scognet * with the given map/virtual_address pair. 3596129198Scognet */ 3597131658Salcvm_paddr_t 3598240983Salcpmap_extract(pmap_t pmap, vm_offset_t va) 3599129198Scognet{ 3600240983Salc vm_paddr_t pa; 3601240983Salc 3602240983Salc PMAP_LOCK(pmap); 3603240983Salc pa = pmap_extract_locked(pmap, va); 3604240983Salc PMAP_UNLOCK(pmap); 3605240983Salc return (pa); 3606240983Salc} 3607240983Salc 3608240983Salcstatic vm_paddr_t 3609240983Salcpmap_extract_locked(pmap_t pmap, vm_offset_t va) 3610240983Salc{ 3611129198Scognet struct l2_dtable *l2; 3612159450Salc pd_entry_t l1pd; 3613129198Scognet pt_entry_t *ptep, pte; 3614129198Scognet vm_paddr_t pa; 3615129198Scognet u_int l1idx; 3616240983Salc 3617240983Salc if (pmap != kernel_pmap) 3618240983Salc PMAP_ASSERT_LOCKED(pmap); 3619129198Scognet l1idx = L1_IDX(va); 3620240983Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3621129198Scognet if (l1pte_section_p(l1pd)) { 3622129198Scognet /* 3623240983Salc * These should only happen for the kernel pmap. 3624129198Scognet */ 3625240983Salc KASSERT(pmap == kernel_pmap, ("unexpected section")); 3626171620Scognet /* XXX: what to do about the bits > 32 ? */ 3627236991Simp if (l1pd & L1_S_SUPERSEC) 3628171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3629171620Scognet else 3630171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3631129198Scognet } else { 3632129198Scognet /* 3633129198Scognet * Note that we can't rely on the validity of the L1 3634129198Scognet * descriptor as an indication that a mapping exists. 3635129198Scognet * We have to look it up in the L2 dtable. 3636129198Scognet */ 3637240983Salc l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3638129198Scognet if (l2 == NULL || 3639240983Salc (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) 3640129198Scognet return (0); 3641240983Salc pte = ptep[l2pte_index(va)]; 3642240983Salc if (pte == 0) 3643129198Scognet return (0); 3644129198Scognet switch (pte & L2_TYPE_MASK) { 3645129198Scognet case L2_TYPE_L: 3646129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3647129198Scognet break; 3648129198Scognet default: 3649129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3650129198Scognet break; 3651129198Scognet } 3652129198Scognet } 3653129198Scognet return (pa); 3654129198Scognet} 3655129198Scognet 3656133453Salc/* 3657133453Salc * Atomically extract and hold the physical page with the given 3658133453Salc * pmap and virtual address pair if that mapping permits the given 3659133453Salc * protection. 3660133453Salc * 3661133453Salc */ 3662129198Scognetvm_page_t 3663129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3664129198Scognet{ 3665135641Scognet struct l2_dtable *l2; 3666159378Salc pd_entry_t l1pd; 3667135641Scognet pt_entry_t *ptep, pte; 3668207410Skmacy vm_paddr_t pa, paddr; 3669135641Scognet vm_page_t m = NULL; 3670135641Scognet u_int l1idx; 3671135641Scognet l1idx = L1_IDX(va); 3672207410Skmacy paddr = 0; 3673129198Scognet 3674159325Salc PMAP_LOCK(pmap); 3675207410Skmacyretry: 3676159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3677135641Scognet if (l1pte_section_p(l1pd)) { 3678135641Scognet /* 3679135641Scognet * These should only happen for pmap_kernel() 3680135641Scognet */ 3681135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3682171620Scognet /* XXX: what to do about the bits > 32 ? */ 3683236991Simp if (l1pd & L1_S_SUPERSEC) 3684171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3685171620Scognet else 3686171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3687207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3688207410Skmacy goto retry; 3689135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3690135641Scognet m = PHYS_TO_VM_PAGE(pa); 3691135641Scognet vm_page_hold(m); 3692135641Scognet } 3693283366Sandrew 3694135641Scognet } else { 3695135641Scognet /* 3696135641Scognet * Note that we can't rely on the validity of the L1 3697135641Scognet * descriptor as an indication that a mapping exists. 3698135641Scognet * We have to look it up in the L2 dtable. 3699135641Scognet */ 3700135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3701135641Scognet 3702135641Scognet if (l2 == NULL || 3703135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3704159325Salc PMAP_UNLOCK(pmap); 3705135641Scognet return (NULL); 3706135641Scognet } 3707135641Scognet 3708135641Scognet ptep = &ptep[l2pte_index(va)]; 3709135641Scognet pte = *ptep; 3710135641Scognet 3711150865Scognet if (pte == 0) { 3712159325Salc PMAP_UNLOCK(pmap); 3713135641Scognet return (NULL); 3714150865Scognet } 3715135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3716135641Scognet switch (pte & L2_TYPE_MASK) { 3717135641Scognet case L2_TYPE_L: 3718135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3719135641Scognet break; 3720283366Sandrew 3721135641Scognet default: 3722135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3723135641Scognet break; 3724135641Scognet } 3725207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3726283366Sandrew goto retry; 3727135641Scognet m = PHYS_TO_VM_PAGE(pa); 3728135641Scognet vm_page_hold(m); 3729135641Scognet } 3730129198Scognet } 3731135641Scognet 3732159325Salc PMAP_UNLOCK(pmap); 3733207410Skmacy PA_UNLOCK_COND(paddr); 3734129198Scognet return (m); 3735129198Scognet} 3736129198Scognet 3737129198Scognet/* 3738129198Scognet * Initialize a preallocated and zeroed pmap structure, 3739129198Scognet * such as one in a vmspace structure. 3740129198Scognet */ 3741129198Scognet 3742173361Skibint 3743129198Scognetpmap_pinit(pmap_t pmap) 3744129198Scognet{ 3745129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3746283366Sandrew 3747129198Scognet pmap_alloc_l1(pmap); 3748129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3749129198Scognet 3750222813Sattilio CPU_ZERO(&pmap->pm_active); 3751283366Sandrew 3752144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3753129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3754129198Scognet pmap->pm_stats.resident_count = 1; 3755129198Scognet if (vector_page < KERNBASE) { 3756269728Skib pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3757269728Skib VM_PROT_READ, PMAP_ENTER_WIRED | VM_PROT_READ, 0); 3758236991Simp } 3759173361Skib return (1); 3760129198Scognet} 3761129198Scognet 3762129198Scognet 3763129198Scognet/*************************************************** 3764129198Scognet * page management routines. 3765129198Scognet ***************************************************/ 3766129198Scognet 3767129198Scognet 3768135641Scognetstatic void 3769129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3770129198Scognet{ 3771129198Scognet pv_entry_count--; 3772129198Scognet uma_zfree(pvzone, pv); 3773129198Scognet} 3774129198Scognet 3775129198Scognet 3776129198Scognet/* 3777129198Scognet * get a new pv_entry, allocating a block from the system 3778129198Scognet * when needed. 3779129198Scognet * the memory allocation is performed bypassing the malloc code 3780129198Scognet * because of the possibility of allocations at interrupt time. 3781129198Scognet */ 3782129198Scognetstatic pv_entry_t 3783129198Scognetpmap_get_pv_entry(void) 3784129198Scognet{ 3785129198Scognet pv_entry_t ret_value; 3786283366Sandrew 3787129198Scognet pv_entry_count++; 3788159500Salc if (pv_entry_count > pv_entry_high_water) 3789159500Salc pagedaemon_wakeup(); 3790129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3791129198Scognet return ret_value; 3792129198Scognet} 3793129198Scognet 3794129198Scognet/* 3795129198Scognet * Remove the given range of addresses from the specified map. 3796129198Scognet * 3797129198Scognet * It is assumed that the start and end are properly 3798129198Scognet * rounded to the page size. 3799129198Scognet */ 3800175840Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3801129198Scognetvoid 3802129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3803129198Scognet{ 3804129198Scognet struct l2_bucket *l2b; 3805129198Scognet vm_offset_t next_bucket; 3806129198Scognet pt_entry_t *ptep; 3807175840Scognet u_int total; 3808129198Scognet u_int mappings, is_exec, is_refd; 3809135641Scognet int flushall = 0; 3810129198Scognet 3811129198Scognet 3812129198Scognet /* 3813129198Scognet * we lock in the pmap => pv_head direction 3814129198Scognet */ 3815129198Scognet 3816239934Salc rw_wlock(&pvh_global_lock); 3817159352Salc PMAP_LOCK(pm); 3818129198Scognet total = 0; 3819129198Scognet while (sva < eva) { 3820129198Scognet /* 3821129198Scognet * Do one L2 bucket's worth at a time. 3822129198Scognet */ 3823129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3824129198Scognet if (next_bucket > eva) 3825129198Scognet next_bucket = eva; 3826129198Scognet 3827129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3828129198Scognet if (l2b == NULL) { 3829129198Scognet sva = next_bucket; 3830129198Scognet continue; 3831129198Scognet } 3832129198Scognet 3833129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3834129198Scognet mappings = 0; 3835129198Scognet 3836129198Scognet while (sva < next_bucket) { 3837129198Scognet struct vm_page *pg; 3838129198Scognet pt_entry_t pte; 3839129198Scognet vm_paddr_t pa; 3840129198Scognet 3841129198Scognet pte = *ptep; 3842129198Scognet 3843129198Scognet if (pte == 0) { 3844129198Scognet /* 3845129198Scognet * Nothing here, move along 3846129198Scognet */ 3847129198Scognet sva += PAGE_SIZE; 3848129198Scognet ptep++; 3849129198Scognet continue; 3850129198Scognet } 3851129198Scognet 3852129198Scognet pm->pm_stats.resident_count--; 3853129198Scognet pa = l2pte_pa(pte); 3854129198Scognet is_exec = 0; 3855129198Scognet is_refd = 1; 3856129198Scognet 3857129198Scognet /* 3858129198Scognet * Update flags. In a number of circumstances, 3859129198Scognet * we could cluster a lot of these and do a 3860129198Scognet * number of sequential pages in one go. 3861129198Scognet */ 3862129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3863129198Scognet struct pv_entry *pve; 3864159474Salc 3865129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3866135641Scognet if (pve) { 3867159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3868159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3869129198Scognet pmap_free_pv_entry(pve); 3870129198Scognet } 3871129198Scognet } 3872129198Scognet 3873175840Scognet if (l2pte_valid(pte) && pmap_is_current(pm)) { 3874175840Scognet if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3875175840Scognet total++; 3876175840Scognet if (is_exec) { 3877175840Scognet cpu_idcache_wbinv_range(sva, 3878183838Sraj PAGE_SIZE); 3879183838Sraj cpu_l2cache_wbinv_range(sva, 3880183838Sraj PAGE_SIZE); 3881175840Scognet cpu_tlb_flushID_SE(sva); 3882175840Scognet } else if (is_refd) { 3883175840Scognet cpu_dcache_wbinv_range(sva, 3884183838Sraj PAGE_SIZE); 3885183838Sraj cpu_l2cache_wbinv_range(sva, 3886183838Sraj PAGE_SIZE); 3887175840Scognet cpu_tlb_flushD_SE(sva); 3888175840Scognet } 3889175840Scognet } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3890175840Scognet /* flushall will also only get set for 3891175840Scognet * for a current pmap 3892175840Scognet */ 3893175840Scognet cpu_idcache_wbinv_all(); 3894183838Sraj cpu_l2cache_wbinv_all(); 3895175840Scognet flushall = 1; 3896175840Scognet total++; 3897129198Scognet } 3898129198Scognet } 3899175840Scognet *ptep = 0; 3900175840Scognet PTE_SYNC(ptep); 3901129198Scognet 3902129198Scognet sva += PAGE_SIZE; 3903129198Scognet ptep++; 3904129198Scognet mappings++; 3905129198Scognet } 3906129198Scognet 3907129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 3908129198Scognet } 3909129198Scognet 3910239934Salc rw_wunlock(&pvh_global_lock); 3911135641Scognet if (flushall) 3912135641Scognet cpu_tlb_flushID(); 3913159352Salc PMAP_UNLOCK(pm); 3914129198Scognet} 3915129198Scognet 3916129198Scognet/* 3917129198Scognet * pmap_zero_page() 3918236991Simp * 3919129198Scognet * Zero a given physical page by mapping it at a page hook point. 3920129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 3921129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 3922129198Scognet * _any_ bulk data very slow. 3923129198Scognet */ 3924262958Sian#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3) 3925129198Scognetvoid 3926129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 3927129198Scognet{ 3928161105Scognet 3929172300Scognet if (_arm_bzero && size >= _min_bzero_size && 3930150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 3931150865Scognet return; 3932129198Scognet 3933159088Scognet mtx_lock(&cmtx); 3934129198Scognet /* 3935183836Sraj * Hook in the page, zero it, invalidate the TLB as needed. 3936183836Sraj * 3937183836Sraj * Note the temporary zero-page mapping must be a non-cached page in 3938184730Sraj * order to work without corruption when write-allocate is enabled. 3939129198Scognet */ 3940183836Sraj *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 3941228530Sraj PTE_SYNC(cdst_pte); 3942129198Scognet cpu_tlb_flushD_SE(cdstp); 3943129198Scognet cpu_cpwait(); 3944183836Sraj if (off || size != PAGE_SIZE) 3945129198Scognet bzero((void *)(cdstp + off), size); 3946183836Sraj else 3947129198Scognet bzero_page(cdstp); 3948183836Sraj 3949159088Scognet mtx_unlock(&cmtx); 3950129198Scognet} 3951262958Sian#endif /* ARM_MMU_GENERIC != 0 */ 3952129198Scognet 3953129198Scognet#if ARM_MMU_XSCALE == 1 3954129198Scognetvoid 3955129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 3956129198Scognet{ 3957172713Scognet 3958172300Scognet if (_arm_bzero && size >= _min_bzero_size && 3959150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 3960150865Scognet return; 3961261642Sian 3962159088Scognet mtx_lock(&cmtx); 3963129198Scognet /* 3964129198Scognet * Hook in the page, zero it, and purge the cache for that 3965129198Scognet * zeroed page. Invalidate the TLB as needed. 3966129198Scognet */ 3967129198Scognet *cdst_pte = L2_S_PROTO | phys | 3968129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3969129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3970129198Scognet PTE_SYNC(cdst_pte); 3971129198Scognet cpu_tlb_flushD_SE(cdstp); 3972129198Scognet cpu_cpwait(); 3973135641Scognet if (off || size != PAGE_SIZE) 3974129198Scognet bzero((void *)(cdstp + off), size); 3975129198Scognet else 3976129198Scognet bzero_page(cdstp); 3977159088Scognet mtx_unlock(&cmtx); 3978129198Scognet xscale_cache_clean_minidata(); 3979129198Scognet} 3980129198Scognet 3981129198Scognet/* 3982129198Scognet * Change the PTEs for the specified kernel mappings such that they 3983129198Scognet * will use the mini data cache instead of the main data cache. 3984129198Scognet */ 3985129198Scognetvoid 3986135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 3987129198Scognet{ 3988129198Scognet struct l2_bucket *l2b; 3989129198Scognet pt_entry_t *ptep, *sptep, pte; 3990129198Scognet vm_offset_t next_bucket, eva; 3991129198Scognet 3992164778Scognet#if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3) 3993129198Scognet if (xscale_use_minidata == 0) 3994129198Scognet return; 3995129198Scognet#endif 3996129198Scognet 3997135641Scognet eva = va + size; 3998129198Scognet 3999129198Scognet while (va < eva) { 4000129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4001129198Scognet if (next_bucket > eva) 4002129198Scognet next_bucket = eva; 4003129198Scognet 4004129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4005129198Scognet 4006129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4007129198Scognet 4008129198Scognet while (va < next_bucket) { 4009129198Scognet pte = *ptep; 4010129198Scognet if (!l2pte_minidata(pte)) { 4011129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4012129198Scognet cpu_tlb_flushD_SE(va); 4013129198Scognet *ptep = pte & ~L2_B; 4014129198Scognet } 4015129198Scognet ptep++; 4016129198Scognet va += PAGE_SIZE; 4017129198Scognet } 4018129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4019129198Scognet } 4020129198Scognet cpu_cpwait(); 4021129198Scognet} 4022129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4023129198Scognet 4024129198Scognet/* 4025236991Simp * pmap_zero_page zeros the specified hardware page by mapping 4026129198Scognet * the page into KVM and using bzero to clear its contents. 4027129198Scognet */ 4028129198Scognetvoid 4029129198Scognetpmap_zero_page(vm_page_t m) 4030129198Scognet{ 4031135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4032129198Scognet} 4033129198Scognet 4034129198Scognet 4035129198Scognet/* 4036236991Simp * pmap_zero_page_area zeros the specified hardware page by mapping 4037129198Scognet * the page into KVM and using bzero to clear its contents. 4038129198Scognet * 4039129198Scognet * off and size may not cover an area beyond a single hardware page. 4040129198Scognet */ 4041129198Scognetvoid 4042129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4043129198Scognet{ 4044129198Scognet 4045129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4046129198Scognet} 4047129198Scognet 4048129198Scognet 4049129198Scognet/* 4050236991Simp * pmap_zero_page_idle zeros the specified hardware page by mapping 4051129198Scognet * the page into KVM and using bzero to clear its contents. This 4052129198Scognet * is intended to be called from the vm_pagezero process only and 4053129198Scognet * outside of Giant. 4054129198Scognet */ 4055129198Scognetvoid 4056129198Scognetpmap_zero_page_idle(vm_page_t m) 4057129198Scognet{ 4058129198Scognet 4059129198Scognet pmap_zero_page(m); 4060129198Scognet} 4061129198Scognet 4062150865Scognet#if 0 4063129198Scognet/* 4064129198Scognet * pmap_clean_page() 4065129198Scognet * 4066129198Scognet * This is a local function used to work out the best strategy to clean 4067197770Sstas * a single page referenced by its entry in the PV table. It should be used by 4068129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4069129198Scognet * 4070129198Scognet * Its policy is effectively: 4071129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4072129198Scognet * o If there is one mapping, we clean just that page. 4073129198Scognet * o If there are multiple mappings, we clean the entire cache. 4074129198Scognet * 4075129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4076129198Scognet * clean the entire cache, or 1 if it did. 4077129198Scognet * 4078129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4079129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4080129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4081129198Scognet * it will just result in not the most efficient clean for the page. 4082197770Sstas * 4083197770Sstas * We don't yet use this function but may want to. 4084129198Scognet */ 4085129198Scognetstatic int 4086129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4087129198Scognet{ 4088129198Scognet pmap_t pm, pm_to_clean = NULL; 4089129198Scognet struct pv_entry *npv; 4090129198Scognet u_int cache_needs_cleaning = 0; 4091129198Scognet u_int flags = 0; 4092129198Scognet vm_offset_t page_to_clean = 0; 4093129198Scognet 4094129198Scognet if (pv == NULL) { 4095129198Scognet /* nothing mapped in so nothing to flush */ 4096129198Scognet return (0); 4097129198Scognet } 4098129198Scognet 4099129198Scognet /* 4100129198Scognet * Since we flush the cache each time we change to a different 4101129198Scognet * user vmspace, we only need to flush the page if it is in the 4102129198Scognet * current pmap. 4103129198Scognet */ 4104135641Scognet if (curthread) 4105135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4106129198Scognet else 4107129198Scognet pm = pmap_kernel(); 4108129198Scognet 4109129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4110129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4111129198Scognet flags |= npv->pv_flags; 4112129198Scognet /* 4113236991Simp * The page is mapped non-cacheable in 4114129198Scognet * this map. No need to flush the cache. 4115129198Scognet */ 4116129198Scognet if (npv->pv_flags & PVF_NC) { 4117129198Scognet#ifdef DIAGNOSTIC 4118129198Scognet if (cache_needs_cleaning) 4119129198Scognet panic("pmap_clean_page: " 4120129198Scognet "cache inconsistency"); 4121129198Scognet#endif 4122129198Scognet break; 4123129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4124129198Scognet continue; 4125129198Scognet if (cache_needs_cleaning) { 4126129198Scognet page_to_clean = 0; 4127129198Scognet break; 4128129198Scognet } else { 4129129198Scognet page_to_clean = npv->pv_va; 4130129198Scognet pm_to_clean = npv->pv_pmap; 4131129198Scognet } 4132129198Scognet cache_needs_cleaning = 1; 4133129198Scognet } 4134129198Scognet } 4135129198Scognet if (page_to_clean) { 4136129198Scognet if (PV_BEEN_EXECD(flags)) 4137129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4138129198Scognet PAGE_SIZE); 4139129198Scognet else 4140129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4141129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4142129198Scognet } else if (cache_needs_cleaning) { 4143129198Scognet if (PV_BEEN_EXECD(flags)) 4144129198Scognet pmap_idcache_wbinv_all(pm); 4145129198Scognet else 4146129198Scognet pmap_dcache_wbinv_all(pm); 4147129198Scognet return (1); 4148129198Scognet } 4149129198Scognet return (0); 4150129198Scognet} 4151150865Scognet#endif 4152129198Scognet 4153129198Scognet/* 4154129198Scognet * pmap_copy_page copies the specified (machine independent) 4155129198Scognet * page by mapping the page into virtual memory and using 4156129198Scognet * bcopy to copy the page, one machine dependent page at a 4157129198Scognet * time. 4158129198Scognet */ 4159129198Scognet 4160129198Scognet/* 4161129198Scognet * pmap_copy_page() 4162129198Scognet * 4163129198Scognet * Copy one physical page into another, by mapping the pages into 4164129198Scognet * hook points. The same comment regarding cachability as in 4165129198Scognet * pmap_zero_page also applies here. 4166129198Scognet */ 4167262958Sian#if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3) 4168129198Scognetvoid 4169129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4170129198Scognet{ 4171151596Scognet#if 0 4172129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4173151596Scognet#endif 4174129198Scognet 4175129198Scognet /* 4176129198Scognet * Clean the source page. Hold the source page's lock for 4177129198Scognet * the duration of the copy so that no other mappings can 4178129198Scognet * be created while we have a potentially aliased mapping. 4179129198Scognet */ 4180129198Scognet#if 0 4181150865Scognet /* 4182150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4183150865Scognet * pmap_copy_page(). 4184150865Scognet */ 4185129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4186150865Scognet#endif 4187129198Scognet /* 4188129198Scognet * Map the pages into the page hook points, copy them, and purge 4189129198Scognet * the cache for the appropriate page. Invalidate the TLB 4190129198Scognet * as required. 4191129198Scognet */ 4192159088Scognet mtx_lock(&cmtx); 4193129198Scognet *csrc_pte = L2_S_PROTO | src | 4194129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4195129198Scognet PTE_SYNC(csrc_pte); 4196129198Scognet *cdst_pte = L2_S_PROTO | dst | 4197129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4198129198Scognet PTE_SYNC(cdst_pte); 4199129198Scognet cpu_tlb_flushD_SE(csrcp); 4200129198Scognet cpu_tlb_flushD_SE(cdstp); 4201129198Scognet cpu_cpwait(); 4202129198Scognet bcopy_page(csrcp, cdstp); 4203159088Scognet mtx_unlock(&cmtx); 4204129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4205129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4206183838Sraj cpu_l2cache_inv_range(csrcp, PAGE_SIZE); 4207183838Sraj cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE); 4208129198Scognet} 4209248280Skib 4210248280Skibvoid 4211248280Skibpmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs, 4212248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt) 4213248280Skib{ 4214248280Skib 4215248280Skib mtx_lock(&cmtx); 4216248280Skib *csrc_pte = L2_S_PROTO | a_phys | 4217248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4218248280Skib PTE_SYNC(csrc_pte); 4219248280Skib *cdst_pte = L2_S_PROTO | b_phys | 4220248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4221248280Skib PTE_SYNC(cdst_pte); 4222248280Skib cpu_tlb_flushD_SE(csrcp); 4223248280Skib cpu_tlb_flushD_SE(cdstp); 4224248280Skib cpu_cpwait(); 4225248280Skib bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt); 4226248280Skib mtx_unlock(&cmtx); 4227248280Skib cpu_dcache_inv_range(csrcp + a_offs, cnt); 4228248280Skib cpu_dcache_wbinv_range(cdstp + b_offs, cnt); 4229248280Skib cpu_l2cache_inv_range(csrcp + a_offs, cnt); 4230248280Skib cpu_l2cache_wbinv_range(cdstp + b_offs, cnt); 4231248280Skib} 4232262958Sian#endif /* ARM_MMU_GENERIC != 0 */ 4233129198Scognet 4234129198Scognet#if ARM_MMU_XSCALE == 1 4235129198Scognetvoid 4236129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4237129198Scognet{ 4238150865Scognet#if 0 4239150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4240129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4241150865Scognet#endif 4242129198Scognet 4243129198Scognet /* 4244129198Scognet * Clean the source page. Hold the source page's lock for 4245129198Scognet * the duration of the copy so that no other mappings can 4246129198Scognet * be created while we have a potentially aliased mapping. 4247129198Scognet */ 4248150865Scognet#if 0 4249150865Scognet /* 4250150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4251150865Scognet * pmap_copy_page(). 4252150865Scognet */ 4253130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4254150865Scognet#endif 4255129198Scognet /* 4256129198Scognet * Map the pages into the page hook points, copy them, and purge 4257129198Scognet * the cache for the appropriate page. Invalidate the TLB 4258129198Scognet * as required. 4259129198Scognet */ 4260159088Scognet mtx_lock(&cmtx); 4261129198Scognet *csrc_pte = L2_S_PROTO | src | 4262129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4263129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4264129198Scognet PTE_SYNC(csrc_pte); 4265129198Scognet *cdst_pte = L2_S_PROTO | dst | 4266129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4267129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4268129198Scognet PTE_SYNC(cdst_pte); 4269129198Scognet cpu_tlb_flushD_SE(csrcp); 4270129198Scognet cpu_tlb_flushD_SE(cdstp); 4271129198Scognet cpu_cpwait(); 4272129198Scognet bcopy_page(csrcp, cdstp); 4273159088Scognet mtx_unlock(&cmtx); 4274129198Scognet xscale_cache_clean_minidata(); 4275129198Scognet} 4276248280Skib 4277248280Skibvoid 4278248280Skibpmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs, 4279248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt) 4280248280Skib{ 4281248280Skib 4282248280Skib mtx_lock(&cmtx); 4283248280Skib *csrc_pte = L2_S_PROTO | a_phys | 4284248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4285248280Skib L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4286248280Skib PTE_SYNC(csrc_pte); 4287248280Skib *cdst_pte = L2_S_PROTO | b_phys | 4288248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4289248280Skib L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4290248280Skib PTE_SYNC(cdst_pte); 4291248280Skib cpu_tlb_flushD_SE(csrcp); 4292248280Skib cpu_tlb_flushD_SE(cdstp); 4293248280Skib cpu_cpwait(); 4294248280Skib bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt); 4295248280Skib mtx_unlock(&cmtx); 4296248280Skib xscale_cache_clean_minidata(); 4297248280Skib} 4298129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4299129198Scognet 4300129198Scognetvoid 4301129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4302129198Scognet{ 4303161105Scognet 4304146596Scognet cpu_dcache_wbinv_all(); 4305183838Sraj cpu_l2cache_wbinv_all(); 4306172300Scognet if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size && 4307236991Simp _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4308150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4309150865Scognet return; 4310129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4311129198Scognet} 4312129198Scognet 4313283014Simp/* 4314283126Simp * We have code to do unmapped I/O. However, it isn't quite right and 4315283126Simp * causes un-page-aligned I/O to devices to fail (most notably newfs 4316283126Simp * or fsck). We give up a little performance to not allow unmapped I/O 4317283126Simp * to gain stability. 4318283014Simp */ 4319283014Simpint unmapped_buf_allowed = 0; 4320248508Skib 4321248280Skibvoid 4322248280Skibpmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4323248280Skib vm_offset_t b_offset, int xfersize) 4324248280Skib{ 4325248280Skib vm_page_t a_pg, b_pg; 4326248280Skib vm_offset_t a_pg_offset, b_pg_offset; 4327248280Skib int cnt; 4328129198Scognet 4329248280Skib cpu_dcache_wbinv_all(); 4330248280Skib cpu_l2cache_wbinv_all(); 4331248280Skib while (xfersize > 0) { 4332248280Skib a_pg = ma[a_offset >> PAGE_SHIFT]; 4333248280Skib a_pg_offset = a_offset & PAGE_MASK; 4334248280Skib cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4335248280Skib b_pg = mb[b_offset >> PAGE_SHIFT]; 4336248280Skib b_pg_offset = b_offset & PAGE_MASK; 4337248280Skib cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4338248280Skib pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset, 4339248280Skib VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt); 4340248280Skib xfersize -= cnt; 4341248280Skib a_offset += cnt; 4342248280Skib b_offset += cnt; 4343248280Skib } 4344248280Skib} 4345129198Scognet 4346129198Scognet/* 4347129198Scognet * this routine returns true if a physical page resides 4348129198Scognet * in the given pmap. 4349129198Scognet */ 4350129198Scognetboolean_t 4351129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4352129198Scognet{ 4353129198Scognet pv_entry_t pv; 4354129198Scognet int loops = 0; 4355208990Salc boolean_t rv; 4356283366Sandrew 4357224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4358208990Salc ("pmap_page_exists_quick: page %p is not managed", m)); 4359208990Salc rv = FALSE; 4360239934Salc rw_wlock(&pvh_global_lock); 4361208990Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4362129198Scognet if (pv->pv_pmap == pmap) { 4363208990Salc rv = TRUE; 4364208990Salc break; 4365129198Scognet } 4366129198Scognet loops++; 4367129198Scognet if (loops >= 16) 4368129198Scognet break; 4369129198Scognet } 4370239934Salc rw_wunlock(&pvh_global_lock); 4371208990Salc return (rv); 4372129198Scognet} 4373129198Scognet 4374173708Salc/* 4375173708Salc * pmap_page_wired_mappings: 4376173708Salc * 4377173708Salc * Return the number of managed mappings to the given physical page 4378173708Salc * that are wired. 4379173708Salc */ 4380173708Salcint 4381173708Salcpmap_page_wired_mappings(vm_page_t m) 4382173708Salc{ 4383173708Salc pv_entry_t pv; 4384173708Salc int count; 4385129198Scognet 4386173708Salc count = 0; 4387224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 4388173708Salc return (count); 4389239934Salc rw_wlock(&pvh_global_lock); 4390173708Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 4391173708Salc if ((pv->pv_flags & PVF_WIRED) != 0) 4392173708Salc count++; 4393239934Salc rw_wunlock(&pvh_global_lock); 4394173708Salc return (count); 4395173708Salc} 4396173708Salc 4397129198Scognet/* 4398255028Salc * This function is advisory. 4399255028Salc */ 4400255028Salcvoid 4401255028Salcpmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4402255028Salc{ 4403255028Salc} 4404255028Salc 4405255028Salc/* 4406129198Scognet * pmap_ts_referenced: 4407129198Scognet * 4408129198Scognet * Return the count of reference bits for a page, clearing all of them. 4409129198Scognet */ 4410129198Scognetint 4411129198Scognetpmap_ts_referenced(vm_page_t m) 4412129198Scognet{ 4413164778Scognet 4414224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4415208990Salc ("pmap_ts_referenced: page %p is not managed", m)); 4416135641Scognet return (pmap_clearbit(m, PVF_REF)); 4417129198Scognet} 4418129198Scognet 4419129198Scognet 4420129198Scognetboolean_t 4421129198Scognetpmap_is_modified(vm_page_t m) 4422129198Scognet{ 4423135641Scognet 4424224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4425208504Salc ("pmap_is_modified: page %p is not managed", m)); 4426135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4427135641Scognet return (TRUE); 4428283366Sandrew 4429129198Scognet return(FALSE); 4430129198Scognet} 4431129198Scognet 4432129198Scognet 4433129198Scognet/* 4434129198Scognet * Clear the modify bits on the specified physical page. 4435129198Scognet */ 4436129198Scognetvoid 4437129198Scognetpmap_clear_modify(vm_page_t m) 4438129198Scognet{ 4439129198Scognet 4440224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4441208504Salc ("pmap_clear_modify: page %p is not managed", m)); 4442248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 4443254138Sattilio KASSERT(!vm_page_xbusied(m), 4444254138Sattilio ("pmap_clear_modify: page %p is exclusive busied", m)); 4445208504Salc 4446208504Salc /* 4447225418Skib * If the page is not PGA_WRITEABLE, then no mappings can be modified. 4448208504Salc * If the object containing the page is locked and the page is not 4449254138Sattilio * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4450208504Salc */ 4451225418Skib if ((m->aflags & PGA_WRITEABLE) == 0) 4452208504Salc return; 4453129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4454129198Scognet pmap_clearbit(m, PVF_MOD); 4455129198Scognet} 4456129198Scognet 4457129198Scognet 4458129198Scognet/* 4459207155Salc * pmap_is_referenced: 4460207155Salc * 4461207155Salc * Return whether or not the specified physical page was referenced 4462207155Salc * in any physical maps. 4463207155Salc */ 4464207155Salcboolean_t 4465207155Salcpmap_is_referenced(vm_page_t m) 4466207155Salc{ 4467207155Salc 4468224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4469208574Salc ("pmap_is_referenced: page %p is not managed", m)); 4470208574Salc return ((m->md.pvh_attrs & PVF_REF) != 0); 4471207155Salc} 4472207155Salc 4473129198Scognet 4474129198Scognet/* 4475160537Salc * Clear the write and modified bits in each of the given page's mappings. 4476160537Salc */ 4477160537Salcvoid 4478160889Salcpmap_remove_write(vm_page_t m) 4479160537Salc{ 4480160537Salc 4481224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4482208175Salc ("pmap_remove_write: page %p is not managed", m)); 4483208175Salc 4484208175Salc /* 4485254138Sattilio * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4486254138Sattilio * set by another thread while the object is locked. Thus, 4487254138Sattilio * if PGA_WRITEABLE is clear, no page table entries need updating. 4488208175Salc */ 4489248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 4490254138Sattilio if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0) 4491160537Salc pmap_clearbit(m, PVF_WRITE); 4492160537Salc} 4493160537Salc 4494160537Salc 4495160537Salc/* 4496129198Scognet * perform the pmap work for mincore 4497129198Scognet */ 4498129198Scognetint 4499208504Salcpmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4500129198Scognet{ 4501235717Simp struct l2_bucket *l2b; 4502235717Simp pt_entry_t *ptep, pte; 4503235717Simp vm_paddr_t pa; 4504235717Simp vm_page_t m; 4505235717Simp int val; 4506235717Simp boolean_t managed; 4507235717Simp 4508235717Simp PMAP_LOCK(pmap); 4509235717Simpretry: 4510235717Simp l2b = pmap_get_l2_bucket(pmap, addr); 4511235717Simp if (l2b == NULL) { 4512235717Simp val = 0; 4513235717Simp goto out; 4514235717Simp } 4515235717Simp ptep = &l2b->l2b_kva[l2pte_index(addr)]; 4516235717Simp pte = *ptep; 4517235717Simp if (!l2pte_valid(pte)) { 4518235717Simp val = 0; 4519235717Simp goto out; 4520235717Simp } 4521235717Simp val = MINCORE_INCORE; 4522235717Simp if (pte & L2_S_PROT_W) 4523235717Simp val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4524235717Simp managed = false; 4525235717Simp pa = l2pte_pa(pte); 4526235717Simp m = PHYS_TO_VM_PAGE(pa); 4527235717Simp if (m != NULL && !(m->oflags & VPO_UNMANAGED)) 4528235717Simp managed = true; 4529235717Simp if (managed) { 4530235717Simp /* 4531241044Salc * The ARM pmap tries to maintain a per-mapping 4532235717Simp * reference bit. The trouble is that it's kept in 4533235717Simp * the PV entry, not the PTE, so it's costly to access 4534241044Salc * here. You would need to acquire the pvh global 4535235717Simp * lock, call pmap_find_pv(), and introduce a custom 4536235717Simp * version of vm_page_pa_tryrelock() that releases and 4537241044Salc * reacquires the pvh global lock. In the end, I 4538235717Simp * doubt it's worthwhile. This may falsely report 4539235717Simp * the given address as referenced. 4540235717Simp */ 4541235717Simp if ((m->md.pvh_attrs & PVF_REF) != 0) 4542235717Simp val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4543235717Simp } 4544235717Simp if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4545235717Simp (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 4546235717Simp /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4547235717Simp if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4548235717Simp goto retry; 4549235717Simp } else 4550235717Simpout: 4551235717Simp PA_UNLOCK_COND(*locked_pa); 4552235717Simp PMAP_UNLOCK(pmap); 4553235717Simp return (val); 4554129198Scognet} 4555129198Scognet 4556129198Scognet 4557198341Smarcelvoid 4558198341Smarcelpmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4559198341Smarcel{ 4560198341Smarcel} 4561198341Smarcel 4562198341Smarcel 4563178893Salc/* 4564178893Salc * Increase the starting virtual address of the given mapping if a 4565178893Salc * different alignment might result in more superpage mappings. 4566178893Salc */ 4567178893Salcvoid 4568178893Salcpmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4569178893Salc vm_offset_t *addr, vm_size_t size) 4570178893Salc{ 4571178893Salc} 4572129198Scognet 4573129198Scognet#define BOOTSTRAP_DEBUG 4574129198Scognet 4575129198Scognet/* 4576129198Scognet * pmap_map_section: 4577129198Scognet * 4578129198Scognet * Create a single section mapping. 4579129198Scognet */ 4580129198Scognetvoid 4581129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4582129198Scognet int prot, int cache) 4583129198Scognet{ 4584129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4585129198Scognet pd_entry_t fl; 4586129198Scognet 4587129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4588129198Scognet 4589129198Scognet switch (cache) { 4590129198Scognet case PTE_NOCACHE: 4591129198Scognet default: 4592129198Scognet fl = 0; 4593129198Scognet break; 4594129198Scognet 4595129198Scognet case PTE_CACHE: 4596129198Scognet fl = pte_l1_s_cache_mode; 4597129198Scognet break; 4598129198Scognet 4599129198Scognet case PTE_PAGETABLE: 4600129198Scognet fl = pte_l1_s_cache_mode_pt; 4601129198Scognet break; 4602129198Scognet } 4603129198Scognet 4604129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4605129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4606129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4607129198Scognet 4608129198Scognet} 4609129198Scognet 4610129198Scognet/* 4611129198Scognet * pmap_link_l2pt: 4612129198Scognet * 4613164079Scognet * Link the L2 page table specified by l2pv.pv_pa into the L1 4614129198Scognet * page table at the slot for "va". 4615129198Scognet */ 4616129198Scognetvoid 4617129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4618129198Scognet{ 4619129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4620129198Scognet u_int slot = va >> L1_S_SHIFT; 4621129198Scognet 4622129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4623129198Scognet 4624236991Simp#ifdef VERBOSE_INIT_ARM 4625164079Scognet printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 4626164079Scognet#endif 4627164079Scognet 4628129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4629164079Scognet 4630129198Scognet PTE_SYNC(&pde[slot]); 4631129198Scognet 4632129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4633129198Scognet 4634283366Sandrew 4635129198Scognet} 4636129198Scognet 4637129198Scognet/* 4638129198Scognet * pmap_map_entry 4639129198Scognet * 4640129198Scognet * Create a single page mapping. 4641129198Scognet */ 4642129198Scognetvoid 4643129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4644129198Scognet int cache) 4645129198Scognet{ 4646129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4647129198Scognet pt_entry_t fl; 4648129198Scognet pt_entry_t *pte; 4649129198Scognet 4650129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4651129198Scognet 4652129198Scognet switch (cache) { 4653129198Scognet case PTE_NOCACHE: 4654129198Scognet default: 4655129198Scognet fl = 0; 4656129198Scognet break; 4657129198Scognet 4658129198Scognet case PTE_CACHE: 4659129198Scognet fl = pte_l2_s_cache_mode; 4660129198Scognet break; 4661129198Scognet 4662129198Scognet case PTE_PAGETABLE: 4663129198Scognet fl = pte_l2_s_cache_mode_pt; 4664129198Scognet break; 4665129198Scognet } 4666129198Scognet 4667129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4668129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4669129198Scognet 4670129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4671129198Scognet 4672129198Scognet if (pte == NULL) 4673129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4674129198Scognet 4675129198Scognet pte[l2pte_index(va)] = 4676129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4677129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4678129198Scognet} 4679129198Scognet 4680129198Scognet/* 4681129198Scognet * pmap_map_chunk: 4682129198Scognet * 4683129198Scognet * Map a chunk of memory using the most efficient mappings 4684129198Scognet * possible (section. large page, small page) into the 4685129198Scognet * provided L1 and L2 tables at the specified virtual address. 4686129198Scognet */ 4687129198Scognetvm_size_t 4688129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4689129198Scognet vm_size_t size, int prot, int cache) 4690129198Scognet{ 4691129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4692129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4693236991Simp vm_size_t resid; 4694129198Scognet int i; 4695129198Scognet 4696129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4697129198Scognet 4698129198Scognet if (l1pt == 0) 4699129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4700129198Scognet 4701236991Simp#ifdef VERBOSE_INIT_ARM 4702159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4703129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4704129198Scognet#endif 4705129198Scognet 4706129198Scognet switch (cache) { 4707129198Scognet case PTE_NOCACHE: 4708129198Scognet default: 4709129198Scognet f1 = 0; 4710129198Scognet f2l = 0; 4711129198Scognet f2s = 0; 4712129198Scognet break; 4713129198Scognet 4714129198Scognet case PTE_CACHE: 4715129198Scognet f1 = pte_l1_s_cache_mode; 4716129198Scognet f2l = pte_l2_l_cache_mode; 4717129198Scognet f2s = pte_l2_s_cache_mode; 4718129198Scognet break; 4719129198Scognet 4720129198Scognet case PTE_PAGETABLE: 4721129198Scognet f1 = pte_l1_s_cache_mode_pt; 4722129198Scognet f2l = pte_l2_l_cache_mode_pt; 4723129198Scognet f2s = pte_l2_s_cache_mode_pt; 4724129198Scognet break; 4725129198Scognet } 4726129198Scognet 4727129198Scognet size = resid; 4728129198Scognet 4729129198Scognet while (resid > 0) { 4730129198Scognet /* See if we can use a section mapping. */ 4731129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4732129198Scognet#ifdef VERBOSE_INIT_ARM 4733129198Scognet printf("S"); 4734129198Scognet#endif 4735129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4736129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4737129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4738129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4739129198Scognet va += L1_S_SIZE; 4740129198Scognet pa += L1_S_SIZE; 4741129198Scognet resid -= L1_S_SIZE; 4742129198Scognet continue; 4743129198Scognet } 4744129198Scognet 4745129198Scognet /* 4746129198Scognet * Ok, we're going to use an L2 table. Make sure 4747129198Scognet * one is actually in the corresponding L1 slot 4748129198Scognet * for the current VA. 4749129198Scognet */ 4750129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4751129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4752129198Scognet 4753129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4754129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4755129198Scognet if (pte == NULL) 4756129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4757129198Scognet "0x%08x", va); 4758129198Scognet /* See if we can use a L2 large page mapping. */ 4759129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4760129198Scognet#ifdef VERBOSE_INIT_ARM 4761129198Scognet printf("L"); 4762129198Scognet#endif 4763129198Scognet for (i = 0; i < 16; i++) { 4764129198Scognet pte[l2pte_index(va) + i] = 4765129198Scognet L2_L_PROTO | pa | 4766129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4767129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4768129198Scognet } 4769129198Scognet va += L2_L_SIZE; 4770129198Scognet pa += L2_L_SIZE; 4771129198Scognet resid -= L2_L_SIZE; 4772129198Scognet continue; 4773129198Scognet } 4774129198Scognet 4775129198Scognet /* Use a small page mapping. */ 4776129198Scognet#ifdef VERBOSE_INIT_ARM 4777129198Scognet printf("P"); 4778129198Scognet#endif 4779129198Scognet pte[l2pte_index(va)] = 4780129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4781129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4782129198Scognet va += PAGE_SIZE; 4783129198Scognet pa += PAGE_SIZE; 4784129198Scognet resid -= PAGE_SIZE; 4785129198Scognet } 4786129198Scognet#ifdef VERBOSE_INIT_ARM 4787129198Scognet printf("\n"); 4788129198Scognet#endif 4789129198Scognet return (size); 4790129198Scognet 4791129198Scognet} 4792129198Scognet 4793135641Scognetvoid 4794244414Scognetpmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4795244414Scognet{ 4796283366Sandrew /* 4797244414Scognet * Remember the memattr in a field that gets used to set the appropriate 4798244414Scognet * bits in the PTEs as mappings are established. 4799244414Scognet */ 4800244414Scognet m->md.pv_memattr = ma; 4801244414Scognet 4802244414Scognet /* 4803244414Scognet * It appears that this function can only be called before any mappings 4804244414Scognet * for the page are established on ARM. If this ever changes, this code 4805244414Scognet * will need to walk the pv_list and make each of the existing mappings 4806244414Scognet * uncacheable, being careful to sync caches and PTEs (and maybe 4807244414Scognet * invalidate TLB?) for any current mapping it modifies. 4808244414Scognet */ 4809244414Scognet if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL) 4810244414Scognet panic("Can't change memattr on page with existing mappings"); 4811244414Scognet} 4812244414Scognet 4813244414Scognet 4814