1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/10.3/sys/dev/cxgbe/common/common.h 275092 2014-11-26 00:44:48Z np $ 27 * 28 */ 29 30#ifndef __CHELSIO_COMMON_H 31#define __CHELSIO_COMMON_H 32 33#include "t4_hw.h" 34 35 36enum { 37 MAX_NPORTS = 4, /* max # of ports */ 38 SERNUM_LEN = 24, /* Serial # length */ 39 EC_LEN = 16, /* E/C length */ 40 ID_LEN = 16, /* ID length */ 41 PN_LEN = 16, /* Part Number length */ 42 MACADDR_LEN = 12, /* MAC Address length */ 43}; 44 45enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 46 47enum { 48 MEMWIN0_APERTURE = 2048, 49 MEMWIN0_BASE = 0x1b800, 50 MEMWIN1_APERTURE = 32768, 51 MEMWIN1_BASE = 0x28000, 52 53 MEMWIN2_APERTURE_T4 = 65536, 54 MEMWIN2_BASE_T4 = 0x30000, 55 56 MEMWIN2_APERTURE_T5 = 128 * 1024, 57 MEMWIN2_BASE_T5 = 0x60000, 58}; 59 60enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 61 62enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 63 64enum { 65 PAUSE_RX = 1 << 0, 66 PAUSE_TX = 1 << 1, 67 PAUSE_AUTONEG = 1 << 2 68}; 69 70struct memwin { 71 uint32_t base; 72 uint32_t aperture; 73}; 74 75struct port_stats { 76 u64 tx_octets; /* total # of octets in good frames */ 77 u64 tx_frames; /* all good frames */ 78 u64 tx_bcast_frames; /* all broadcast frames */ 79 u64 tx_mcast_frames; /* all multicast frames */ 80 u64 tx_ucast_frames; /* all unicast frames */ 81 u64 tx_error_frames; /* all error frames */ 82 83 u64 tx_frames_64; /* # of Tx frames in a particular range */ 84 u64 tx_frames_65_127; 85 u64 tx_frames_128_255; 86 u64 tx_frames_256_511; 87 u64 tx_frames_512_1023; 88 u64 tx_frames_1024_1518; 89 u64 tx_frames_1519_max; 90 91 u64 tx_drop; /* # of dropped Tx frames */ 92 u64 tx_pause; /* # of transmitted pause frames */ 93 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 94 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 95 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 96 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 97 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 98 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 99 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 100 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 101 102 u64 rx_octets; /* total # of octets in good frames */ 103 u64 rx_frames; /* all good frames */ 104 u64 rx_bcast_frames; /* all broadcast frames */ 105 u64 rx_mcast_frames; /* all multicast frames */ 106 u64 rx_ucast_frames; /* all unicast frames */ 107 u64 rx_too_long; /* # of frames exceeding MTU */ 108 u64 rx_jabber; /* # of jabber frames */ 109 u64 rx_fcs_err; /* # of received frames with bad FCS */ 110 u64 rx_len_err; /* # of received frames with length error */ 111 u64 rx_symbol_err; /* symbol errors */ 112 u64 rx_runt; /* # of short frames */ 113 114 u64 rx_frames_64; /* # of Rx frames in a particular range */ 115 u64 rx_frames_65_127; 116 u64 rx_frames_128_255; 117 u64 rx_frames_256_511; 118 u64 rx_frames_512_1023; 119 u64 rx_frames_1024_1518; 120 u64 rx_frames_1519_max; 121 122 u64 rx_pause; /* # of received pause frames */ 123 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 124 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 125 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 126 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 127 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 128 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 129 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 130 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 131 132 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 133 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 134 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 135 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 136 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 137 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 138 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 139 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 140}; 141 142struct lb_port_stats { 143 u64 octets; 144 u64 frames; 145 u64 bcast_frames; 146 u64 mcast_frames; 147 u64 ucast_frames; 148 u64 error_frames; 149 150 u64 frames_64; 151 u64 frames_65_127; 152 u64 frames_128_255; 153 u64 frames_256_511; 154 u64 frames_512_1023; 155 u64 frames_1024_1518; 156 u64 frames_1519_max; 157 158 u64 drop; 159 160 u64 ovflow0; 161 u64 ovflow1; 162 u64 ovflow2; 163 u64 ovflow3; 164 u64 trunc0; 165 u64 trunc1; 166 u64 trunc2; 167 u64 trunc3; 168}; 169 170struct tp_tcp_stats { 171 u32 tcpOutRsts; 172 u64 tcpInSegs; 173 u64 tcpOutSegs; 174 u64 tcpRetransSegs; 175}; 176 177struct tp_usm_stats { 178 u32 frames; 179 u32 drops; 180 u64 octets; 181}; 182 183struct tp_fcoe_stats { 184 u32 framesDDP; 185 u32 framesDrop; 186 u64 octetsDDP; 187}; 188 189struct tp_err_stats { 190 u32 macInErrs[4]; 191 u32 hdrInErrs[4]; 192 u32 tcpInErrs[4]; 193 u32 tnlCongDrops[4]; 194 u32 ofldChanDrops[4]; 195 u32 tnlTxDrops[4]; 196 u32 ofldVlanDrops[4]; 197 u32 tcp6InErrs[4]; 198 u32 ofldNoNeigh; 199 u32 ofldCongDefer; 200}; 201 202struct tp_proxy_stats { 203 u32 proxy[4]; 204}; 205 206struct tp_cpl_stats { 207 u32 req[4]; 208 u32 rsp[4]; 209}; 210 211struct tp_rdma_stats { 212 u32 rqe_dfr_mod; 213 u32 rqe_dfr_pkt; 214}; 215 216struct tp_params { 217 unsigned int ntxchan; /* # of Tx channels */ 218 unsigned int tre; /* log2 of core clocks per TP tick */ 219 unsigned int dack_re; /* DACK timer resolution */ 220 unsigned int la_mask; /* what events are recorded by TP LA */ 221 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 222 uint32_t vlan_pri_map; 223 uint32_t ingress_config; 224 int8_t vlan_shift; 225 int8_t vnic_shift; 226 int8_t port_shift; 227 int8_t protocol_shift; 228}; 229 230struct vpd_params { 231 unsigned int cclk; 232 u8 ec[EC_LEN + 1]; 233 u8 sn[SERNUM_LEN + 1]; 234 u8 id[ID_LEN + 1]; 235 u8 pn[PN_LEN + 1]; 236 u8 na[MACADDR_LEN + 1]; 237}; 238 239struct pci_params { 240 unsigned int vpd_cap_addr; 241 unsigned int mps; 242 unsigned short speed; 243 unsigned short width; 244}; 245 246/* 247 * Firmware device log. 248 */ 249struct devlog_params { 250 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 251 u32 start; /* start of log in firmware memory */ 252 u32 size; /* size of log */ 253}; 254 255struct adapter_params { 256 struct tp_params tp; 257 struct vpd_params vpd; 258 struct pci_params pci; 259 struct devlog_params devlog; 260 261 unsigned int sf_size; /* serial flash size in bytes */ 262 unsigned int sf_nsec; /* # of flash sectors */ 263 264 unsigned int fw_vers; 265 unsigned int tp_vers; 266 267 unsigned short mtus[NMTUS]; 268 unsigned short a_wnd[NCCTRL_WIN]; 269 unsigned short b_wnd[NCCTRL_WIN]; 270 271 u_int ftid_min; 272 u_int ftid_max; 273 u_int etid_min; 274 u_int netids; 275 276 unsigned int cim_la_size; 277 278 uint8_t nports; /* # of ethernet ports */ 279 uint8_t portvec; 280 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 281 unsigned int rev:4; /* chip revision */ 282 unsigned int fpga:1; /* this is an FPGA */ 283 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 284 resources for TOE operation. */ 285 unsigned int bypass:1; /* this is a bypass card */ 286 unsigned int ethoffload:1; 287 288 unsigned int ofldq_wr_cred; 289 unsigned int eo_wr_cred; 290}; 291 292#define CHELSIO_T4 0x4 293#define CHELSIO_T5 0x5 294 295struct trace_params { 296 u32 data[TRACE_LEN / 4]; 297 u32 mask[TRACE_LEN / 4]; 298 unsigned short snap_len; 299 unsigned short min_len; 300 unsigned char skip_ofst; 301 unsigned char skip_len; 302 unsigned char invert; 303 unsigned char port; 304}; 305 306struct link_config { 307 unsigned short supported; /* link capabilities */ 308 unsigned short advertising; /* advertised capabilities */ 309 unsigned short requested_speed; /* speed user has requested */ 310 unsigned short speed; /* actual link speed */ 311 unsigned char requested_fc; /* flow control user has requested */ 312 unsigned char fc; /* actual link flow control */ 313 unsigned char autoneg; /* autonegotiating? */ 314 unsigned char link_ok; /* link up? */ 315}; 316 317#include "adapter.h" 318 319#ifndef PCI_VENDOR_ID_CHELSIO 320# define PCI_VENDOR_ID_CHELSIO 0x1425 321#endif 322 323#define for_each_port(adapter, iter) \ 324 for (iter = 0; iter < (adapter)->params.nports; ++iter) 325 326static inline int is_ftid(const struct adapter *sc, u_int tid) 327{ 328 329 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max); 330} 331 332static inline int is_etid(const struct adapter *sc, u_int tid) 333{ 334 335 return (tid >= sc->params.etid_min); 336} 337 338static inline int is_offload(const struct adapter *adap) 339{ 340 return adap->params.offload; 341} 342 343static inline int is_ethoffload(const struct adapter *adap) 344{ 345 return adap->params.ethoffload; 346} 347 348static inline int chip_id(struct adapter *adap) 349{ 350 return adap->params.chipid; 351} 352 353static inline int chip_rev(struct adapter *adap) 354{ 355 return adap->params.rev; 356} 357 358static inline int is_t4(struct adapter *adap) 359{ 360 return adap->params.chipid == CHELSIO_T4; 361} 362 363static inline int is_t5(struct adapter *adap) 364{ 365 return adap->params.chipid == CHELSIO_T5; 366} 367 368static inline int is_fpga(struct adapter *adap) 369{ 370 return adap->params.fpga; 371} 372 373static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 374{ 375 return adap->params.vpd.cclk / 1000; 376} 377 378static inline unsigned int us_to_core_ticks(const struct adapter *adap, 379 unsigned int us) 380{ 381 return (us * adap->params.vpd.cclk) / 1000; 382} 383 384static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 385 unsigned int ticks) 386{ 387 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 388} 389 390void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 391int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity, 392 int attempts, int delay, u32 *valp); 393 394static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 395 int polarity, int attempts, int delay) 396{ 397 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 398 delay, NULL); 399} 400 401int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 402 void *rpl, bool sleep_ok); 403 404static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 405 int size, void *rpl) 406{ 407 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 408} 409 410static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 411 int size, void *rpl) 412{ 413 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 414} 415 416void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 417 unsigned int data_reg, u32 *vals, unsigned int nregs, 418 unsigned int start_idx); 419void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 420 unsigned int data_reg, const u32 *vals, 421 unsigned int nregs, unsigned int start_idx); 422 423u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 424 425struct fw_filter_wr; 426 427void t4_intr_enable(struct adapter *adapter); 428void t4_intr_disable(struct adapter *adapter); 429void t4_intr_clear(struct adapter *adapter); 430int t4_slow_intr_handler(struct adapter *adapter); 431 432int t4_hash_mac_addr(const u8 *addr); 433int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 434 struct link_config *lc); 435int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 436int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 437int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 438int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 439int t4_seeprom_wp(struct adapter *adapter, int enable); 440int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 441 u32 *data, int byte_oriented); 442int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 443int t4_load_boot(struct adapter *adap, u8 *boot_data, 444 unsigned int boot_addr, unsigned int size); 445int t4_flash_cfg_addr(struct adapter *adapter); 446int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 447int t4_get_fw_version(struct adapter *adapter, u32 *vers); 448int t4_get_tp_version(struct adapter *adapter, u32 *vers); 449int t4_check_fw_version(struct adapter *adapter); 450int t4_init_hw(struct adapter *adapter, u32 fw_params); 451int t4_prep_adapter(struct adapter *adapter); 452int t4_init_tp_params(struct adapter *adap); 453int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 454int t4_port_init(struct port_info *p, int mbox, int pf, int vf); 455int t4_reinit_adapter(struct adapter *adap); 456void t4_fatal_err(struct adapter *adapter); 457int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 458 int filter_index, int enable); 459void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 460 int filter_index, int *enabled); 461int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 462 int start, int n, const u16 *rspq, unsigned int nrspq); 463int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 464 unsigned int flags); 465int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 466 unsigned int flags, unsigned int defq); 467int t4_read_rss(struct adapter *adapter, u16 *entries); 468void t4_read_rss_key(struct adapter *adapter, u32 *key); 469void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 470void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp); 471void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val); 472void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 473 u32 *vfl, u32 *vfh); 474void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 475 u32 vfl, u32 vfh); 476u32 t4_read_rss_pf_map(struct adapter *adapter); 477void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap); 478u32 t4_read_rss_pf_mask(struct adapter *adapter); 479void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask); 480int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 481void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 482void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 483void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 484int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 485int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 486int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 487 unsigned int *valp); 488int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 489 const unsigned int *valp); 490int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 491 unsigned int *valp); 492int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 493void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 494 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 495void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 496int t4_mc_read(struct adapter *adap, int idx, u32 addr, 497 __be32 *data, u64 *parity); 498int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 499int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 500 __be32 *data); 501 502void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 503void t4_get_port_stats_offset(struct adapter *adap, int idx, 504 struct port_stats *stats, 505 struct port_stats *offset); 506void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 507void t4_clr_port_stats(struct adapter *adap, int idx); 508 509void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 510void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 511void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 512void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 513 unsigned int *ipg); 514void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 515 unsigned int mask, unsigned int val); 516void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 517void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 518void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st); 519void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 520void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 521void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 522void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 523 struct tp_tcp_stats *v6); 524void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 525 struct tp_fcoe_stats *st); 526void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 527 const unsigned short *alpha, const unsigned short *beta); 528 529void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 530 531int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 532int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 533int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 534 unsigned int start, unsigned int n); 535void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 536int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map); 537void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 538 539void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 540int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 541 u64 mask0, u64 mask1, unsigned int crc, bool enable); 542 543int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 544 enum dev_master master, enum dev_state *state); 545int t4_fw_bye(struct adapter *adap, unsigned int mbox); 546int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 547int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 548int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 549int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 550 const u8 *fw_data, unsigned int size, int force); 551int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 552int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 553 unsigned int vf, unsigned int nparams, const u32 *params, 554 u32 *val); 555int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 556 unsigned int vf, unsigned int nparams, const u32 *params, 557 const u32 *val); 558int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 559 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 560 unsigned int rxqi, unsigned int rxq, unsigned int tc, 561 unsigned int vi, unsigned int cmask, unsigned int pmask, 562 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 563int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 564 unsigned int port, unsigned int pf, unsigned int vf, 565 unsigned int nmac, u8 *mac, u16 *rss_size, 566 unsigned int portfunc, unsigned int idstype); 567int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 568 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 569 u16 *rss_size); 570int t4_free_vi(struct adapter *adap, unsigned int mbox, 571 unsigned int pf, unsigned int vf, 572 unsigned int viid); 573int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 574 int mtu, int promisc, int all_multi, int bcast, int vlanex, 575 bool sleep_ok); 576int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 577 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 578 u64 *hash, bool sleep_ok); 579int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 580 int idx, const u8 *addr, bool persist, bool add_smt); 581int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 582 bool ucast, u64 vec, bool sleep_ok); 583int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 584 bool rx_en, bool tx_en); 585int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 586 unsigned int nblinks); 587int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 588 unsigned int mmd, unsigned int reg, unsigned int *valp); 589int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 590 unsigned int mmd, unsigned int reg, unsigned int val); 591int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 592 int port, unsigned int devid, 593 unsigned int offset, unsigned int len, 594 u8 *buf); 595int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 596 int port, unsigned int devid, 597 unsigned int offset, unsigned int len, 598 u8 *buf); 599int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 600 unsigned int pf, unsigned int vf, unsigned int iqid, 601 unsigned int fl0id, unsigned int fl1id); 602int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 603 unsigned int vf, unsigned int iqtype, unsigned int iqid, 604 unsigned int fl0id, unsigned int fl1id); 605int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 606 unsigned int vf, unsigned int eqid); 607int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 608 unsigned int vf, unsigned int eqid); 609int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 610 unsigned int vf, unsigned int eqid); 611int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 612 enum ctxt_type ctype, u32 *data); 613int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 614 u32 *data); 615int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 616int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 617int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 618int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 619 int sleep_ok); 620int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 621 int rateunit, int ratemode, int channel, int cl, 622 int minrate, int maxrate, int weight, int pktsize, 623 int sleep_ok); 624#endif /* __CHELSIO_COMMON_H */ 625