1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_dispc_l4_per.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_dispc_l4_per msbfirst ( addr base ) "" {
29    
30    
31    register dispc_revision ro addr(base, 0x0) "IP Revision" type(uint32);
32
33    constants midlemode_status width(2) "" {
34        MIDLEMODE_0 = 0 "Force-standby. MStandby is only asserted when the module is disabled. MStandby is only asserted when the module is disabled.";
35        MIDLEMODE_1 = 1 "No-Standby: MStandby is never asserted.";
36        MIDLEMODE_2 = 2 "Smart-Standby. MStandby is asserted based on the internal activity of the module";
37        MIDLEMODE_3 = 3 "Reserved";
38    };
39
40    constants clockactivity_status width(2) "" {
41        CLOCKACTIVITY_0 = 0 "OCP and Functional clocks can be switched off";
42        CLOCKACTIVITY_1 = 1 "Functional clocks can be switched off and OCP clocks are maintained during wake up period";
43        CLOCKACTIVITY_2 = 2 "OCP clocks can be switched off and Functional clocks are maintained during wake up period";
44        CLOCKACTIVITY_3 = 3 "OCP and Functional clocks are maintained during wake up period";
45    };
46
47    constants warmreset_status width(1) "" {
48        WARMRESET_0 = 0 "Normal mode";
49        WARMRESET_1 = 1 "the warmreset is set";
50    };
51
52    constants sidlemode_status width(2) "" {
53        SIDLEMODE_0 = 0 "Force-idle. An idle request is acknowledged unconditionally";
54        SIDLEMODE_1 = 1 "No-idle. An idle request is never acknowledged";
55        SIDLEMODE_2 = 2 "Smart-idle. Acknowledgment to an idle request is given based on the internal activity of the module.";
56        SIDLEMODE_3 = 3 "Reserved";
57    };
58
59    constants enwakeup_status width(1) "" {
60        ENWAKEUP_0 = 0 "Wakeup is disabled";
61        ENWAKEUP_1 = 1 "Wakeup is enabled";
62    };
63
64    constants softreset_status width(1) "" {
65        SOFTRESET_0 = 0 "Normal mode";
66        SOFTRESET_1 = 1 "The module is reset";
67    };
68
69    constants autoidle_status width(1) "" {
70        AUTOIDLE_0 = 0 "OCP clock is free-running";
71        AUTOIDLE_1 = 1 "Automatic OCP L3 and L4 clocks gating strategy is applied, based on the OCP interface activity. Automatic functional clock gating is also applied to the functional clock based on the module activity (for instance DISPC_<pipe>_ATTRIBUTES.ENABLE)";
72    };
73    
74    register dispc_sysconfig addr(base, 0x10) "This register allows to control various parameters of the OCP interface." {
75        _ 18 mbz;
76        midlemode 2 rw type(midlemode_status) "Master interface power management, standby/wait control";
77        _ 2 mbz;
78        clockactivity 2 rw type(clockactivity_status) "Clocks activity during wake up mode period";
79        _ 2 mbz;
80        warmreset 1 rw type(warmreset_status) "Warm reset. Set this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During reads, it always returns 0. The warm reset keep the configuration registers unchanged.";
81        sidlemode 2 rw type(sidlemode_status) "Slave interface power management, Idle req/ack control";
82        enwakeup 1 rw type(enwakeup_status) "WakeUp feature control";
83        softreset 1 rw type(softreset_status) "Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0.";
84        autoidle 1 rw type(autoidle_status) "Internal OCP clock gating strategy";
85    };
86
87    constants resetdone_status width(1) "" {
88        RESETDONE_0_r = 0 "Internal module reset is on-going";
89        RESETDONE_1_r = 1 "Reset completed";
90    };
91    
92    register dispc_sysstatus addr(base, 0x14) "This register provides status information about the module, excluding the interrupt status information." {
93        _ 31 mbz;
94        resetdone 1 ro type(resetdone_status) "Internal reset monitoring";
95    };
96
97    constants wbbuffer_overflow_irq_status width(1) "" {
98        WBBUFFER_OVERFLOW_IRQ_0 = 0 "READS: Event is false. WRITES: Status bit unchanged.";
99        WBBUFFER_OVERFLOW_IRQ_1 = 1 "READS: Event is true (pending). WRITES: Status bit is reset.";
100    };
101    
102    register dispc_irqstatus addr(base, 0x18) "This register regroups all the status of the module internal events that generate an interrupt. Write 1 to a given bit resets this bit" {
103        _ 5 mbz;
104        wbuncompleteerror_irq 1 rw1c "Write-back DMA buffer is flushed before it is completely drained. In WB capture mode, if the new frame starts before the WB DMA buffers are fully drained (onto external memory), then the contents of the WB DMA buffers are lost (implying last few pixels/lines are corrupted in the captured frame in memory). This interrupt is an indication of that case and will trigger every frame.0x0 READS: Event is false. . 0x0 WRITES: Status bit unchanged. . 0x1 READS: Event is true (Pending). . 0x1 WRITES: Status bit is reset. .";
105        wbbuffer_overflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Write-back DMA Buffer Overflow. The DMA buffer is full.";
106        frame_donetv_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the TV. The TV output has been disabled by user. All the data have been sent.";
107        frame_donewb_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the write-back channel. The write-back channel has output the frame. All the data of the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory. It is available only when the write-back pipeline transfers back to memory the output of one of the pipelines. In case of overlay capture, the interrupt is not generated and the user shall use the FrameDone for the corresponding captured output.";
108        frame_done2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent.";
109        acbiascount_status2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "AC Bias Count Status for the secondary LCD";
110        vid3buffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Video 3 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
111        vid3end_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed.";
112        vsync2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Vertical Synchronization for the secondary LCD";
113        sync_lost2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output.";
114        wakeup_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Wake-up";
115        synclost_tv_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output.";
116        sync_lost1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Synchronization Lost on the primary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the primary LCD output.";
117        vid2end_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed.";
118        vid2buffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Video 2 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
119        vid1end_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed.";
120        vid1buffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Video 1 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
121        ocperror_irq 1 rw1c type(wbbuffer_overflow_irq_status) "OCP Error. L3 Interconnect has sent SResp=ERR.";
122        palettegamma_loading_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Palette Gamma Loading status. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.";
123        gfxend_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed.";
124        gfxbuffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
125        programmed_linenumber_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number.";
126        acbiascount_status1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "AC Bias Count Status for the primary LCD";
127        evsync_odd_irq 1 rw1c type(wbbuffer_overflow_irq_status) "VSYNC for odd field from the TV encoder (VENC or HDMI)";
128        evsync_even_irq 1 rw1c type(wbbuffer_overflow_irq_status) "VSYNC for even field from the TV encoder (VENC or HDMI)";
129        vsync1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Vertical Synchronization for the primary LCD.";
130        frame_done1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent.";
131    };
132
133    constants wbuncompleteerror_en_status width(1) "" {
134        WBUNCOMPLETEERROR_EN_0 = 0 "Interrupt is masked.";
135        WBUNCOMPLETEERROR_EN_1 = 1 "Interrupt is enabled.";
136    };
137
138    constants wbbuffer_overflow_en_status width(1) "" {
139        WBBUFFER_OVERFLOW_EN_0 = 0 "WBBufferOverflow is masked";
140        WBBUFFER_OVERFLOW_EN_1 = 1 "WBBufferOverflow generates an interrupt when it occurs";
141    };
142
143    constants frame_donetv_en_status width(1) "" {
144        FRAME_DONETV_EN_0 = 0 "Frame Done for the TV output is masked";
145        FRAME_DONETV_EN_1 = 1 "Frame Done for the TV output generates an interrupt when it occurs";
146    };
147
148    constants frame_donewb_en_status width(1) "" {
149        FRAME_DONEWB_EN_0 = 0 "Frame Done for the write-back is masked";
150        FRAME_DONEWB_EN_1 = 1 "Frame Done for the write-back generates an interrupt when it occurs";
151    };
152
153    constants frame_done2_en_status width(1) "" {
154        FRAME_DONE2_EN_0 = 0 "Frame Done for the secondary LCD is masked";
155        FRAME_DONE2_EN_1 = 1 "Frame Done for the secondary LCD generates an interrupt when it occurs";
156    };
157
158    constants vid3buffer_underflow_en_status width(1) "" {
159        VID3BUFFER_UNDERFLOW_EN_0 = 0 "Vid3BufferUnderflow is masked";
160        VID3BUFFER_UNDERFLOW_EN_1 = 1 "Vid3BufferUnderflow generates an interrupt when it occurs";
161    };
162
163    constants vid3end_window_en_status width(1) "" {
164        VID3END_WINDOW_EN_0 = 0 "Vid3EndWindow is masked";
165        VID3END_WINDOW_EN_1 = 1 "Vid3EndWindow generates an interrupt when it occurs";
166    };
167
168    constants vsync2_en_status width(1) "" {
169        VSYNC2_EN_0 = 0 "VSYNC for the secondary LCD output is masked";
170        VSYNC2_EN_1 = 1 "VSYNC for the secondary LCD output generates an interrupt when it occurs";
171    };
172
173    constants wakeup_en_status width(1) "" {
174        WAKEUP_EN_0 = 0 "WakeUp is masked";
175        WAKEUP_EN_1 = 1 "WakeUp generates an interrupt when it occurs";
176    };
177
178    constants sync_losttv_en_status width(1) "" {
179        SYNC_LOSTTV_EN_0 = 0 "Synchronization Lost on the TV output is masked";
180        SYNC_LOSTTV_EN_1 = 1 "Synchronization Lost on the TV output generates an interrupt when it occurs";
181    };
182
183    constants vid2end_window_en_status width(1) "" {
184        VID2END_WINDOW_EN_0 = 0 "Vid2EndWindow is masked";
185        VID2END_WINDOW_EN_1 = 1 "Vid2EndWindow generates an interrupt when it occurs";
186    };
187
188    constants vid2buffer_underflow_en_status width(1) "" {
189        VID2BUFFER_UNDERFLOW_EN_0 = 0 "Vid2BufferUnderflow is masked";
190        VID2BUFFER_UNDERFLOW_EN_1 = 1 "Vid2BufferUnderflow generates an interrupt when it occurs";
191    };
192
193    constants endvid1_window_en_status width(1) "" {
194        ENDVID1_WINDOW_EN_0 = 0 "EndVid1Window is masked";
195        ENDVID1_WINDOW_EN_1 = 1 "EndVid1Window generates an interrupt when it occurs";
196    };
197
198    constants vid1buffer_underflow_en_status width(1) "" {
199        VID1BUFFER_UNDERFLOW_EN_0 = 0 "Vid1BufferUnderflow is masked";
200        VID1BUFFER_UNDERFLOW_EN_1 = 1 "Vid1BufferUnderflow generates an interrupt when it occurs";
201    };
202
203    constants ocperror_en_status width(1) "" {
204        OCPERROR_EN_0 = 0 "OCPError is masked";
205        OCPERROR_EN_1 = 1 "OCPError generates an interrupt when it occurs";
206    };
207
208    constants palette_gamma_en_status width(1) "" {
209        PALETTE_GAMMA_EN_0 = 0 "PaletteGamma is masked";
210        PALETTE_GAMMA_EN_1 = 1 "PaletteGamma generates an interrupt when it occurs";
211    };
212
213    constants gfxend_window_en_status width(1) "" {
214        GFXEND_WINDOW_EN_0 = 0 "GfxEndWindow is masked";
215        GFXEND_WINDOW_EN_1 = 1 "GfxEndWindow generates an interrupt when it occurs";
216    };
217
218    constants gfxbuffer_underflow_en_status width(1) "" {
219        GFXBUFFER_UNDERFLOW_EN_0 = 0 "GfxBufferUnderflow is masked";
220        GFXBUFFER_UNDERFLOW_EN_1 = 1 "GfxBufferUnderflow generates an interrupt when it occurs";
221    };
222
223    constants programmed_linenumber_en_status width(1) "" {
224        PROGRAMMED_LINENUMBER_EN_0 = 0 "ProgrammedLineNumber is masked";
225        PROGRAMMED_LINENUMBER_EN_1 = 1 "ProgrammedLineNumber generates an interrupt when it occurs";
226    };
227
228    constants evsync_odd_en_status width(1) "" {
229        EVSYNC_ODD_EN_0 = 0 "EVSYNC_ODD for the TV output is masked";
230        EVSYNC_ODD_EN_1 = 1 "EVSYNC_ODD for the TV output generates an interrupt when it occurs";
231    };
232
233    constants evsync_even_en_status width(1) "" {
234        EVSYNC_EVEN_EN_0 = 0 "EVSYNC_EVEN for the TV output is masked";
235        EVSYNC_EVEN_EN_1 = 1 "EVSYNC_EVEN for the TV output generates an interrupt when it occurs";
236    };
237    
238    register dispc_irqenable addr(base, 0x1C) "This register allows to mask/unmask the module internal sources of interrupt, on an event-by-event basis" {
239        _ 5 mbz;
240        wbuncompleteerror_en 1 rw type(wbuncompleteerror_en_status) "The write back buffer has been flushed before it has been fully drained. Enable.";
241        wbbuffer_overflow_en 1 rw type(wbbuffer_overflow_en_status) "Write-back DMA Buffer Overflow. The DMA buffer is full";
242        frame_donetv_en 1 rw type(frame_donetv_en_status) "Frame Done for the TV. The TV output has been disabled by user. All the data have been sent.";
243        frame_donewb_en 1 rw type(frame_donewb_en_status) "Frame Done for the write-back channel. The write-back channel has output the frame. All the data have been sent for the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory.";
244        frame_done2_en 1 rw type(frame_done2_en_status) "Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent.";
245        acbiascount_status2_en 1 rw type(frame_done2_en_status) "AC Bias Count Status for the secondary LCD";
246        vid3buffer_underflow_en 1 rw type(vid3buffer_underflow_en_status) "Video 3 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)";
247        vid3end_window_en 1 rw type(vid3end_window_en_status) "The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed.";
248        vsync2_en 1 rw type(vsync2_en_status) "Vertical Synchronization for the secondary LCD";
249        sync_lost2_en 1 rw type(frame_done2_en_status) "Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output.";
250        wakeup_en 1 rw type(wakeup_en_status) "Wake Up Mask";
251        sync_losttv_en 1 rw type(sync_losttv_en_status) "Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output.";
252        sync_lost1_en 1 rw type(frame_done2_en_status) "Synchronization Lost for the primary LCD";
253        vid2end_window_en 1 rw type(vid2end_window_en_status) "The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed.";
254        vid2buffer_underflow_en 1 rw type(vid2buffer_underflow_en_status) "Video 2 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)";
255        endvid1_window_en 1 rw type(endvid1_window_en_status) "The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed.";
256        vid1buffer_underflow_en 1 rw type(vid1buffer_underflow_en_status) "Video 1 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)";
257        ocperror_en 1 rw type(ocperror_en_status) "OCP Error. L3 Interconnect has sent SResp=ERR.";
258        palette_gamma_en 1 rw type(palette_gamma_en_status) "Palette Gamma Loading mask. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.";
259        gfxend_window_en 1 rw type(gfxend_window_en_status) "The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed.";
260        gfxbuffer_underflow_en 1 rw type(gfxbuffer_underflow_en_status) "Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
261        programmed_linenumber_en 1 rw type(programmed_linenumber_en_status) "Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number.";
262        acbiascount_status1_en 1 rw type(frame_done2_en_status) "AC Bias Count Status for the primary LCD";
263        evsync_odd_en 1 rw type(evsync_odd_en_status) "VSYNC for odd field from the TV encoder (VENC or HDMI)";
264        evsync_even_en 1 rw type(evsync_even_en_status) "VSYNC for even field from the TV encoder (VENC or HDMI)";
265        vsync1_en 1 rw type(vsync2_en_status) "Vertical Synchronization for the primary LCD.";
266        framedone_en 1 rw type(frame_done2_en_status) "Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent.";
267    };
268
269    constants spatialtemporal_ditheringframes_status width(2) "" {
270        SPATIALTEMPORAL_DITHERINGFRAMES_0 = 0 "Spatial only";
271        SPATIALTEMPORAL_DITHERINGFRAMES_1 = 1 "Spatial and temporal over 2 frames";
272        SPATIALTEMPORAL_DITHERINGFRAMES_2 = 2 "Spatial and temporal over 4 frames";
273        SPATIALTEMPORAL_DITHERINGFRAMES_3 = 3 "Reserved";
274    };
275
276    constants tdmunusedbits_status width(2) "" {
277        TDMUNUSEDBITS_0 = 0 "low level (0)";
278        TDMUNUSEDBITS_1 = 1 "high level (1)";
279        TDMUNUSEDBITS_2 = 2 "unchanged from previous state";
280        TDMUNUSEDBITS_3 = 3 "reserved";
281    };
282
283    constants tdmcycleformat_status width(2) "" {
284        TDMCYCLEFORMAT_0 = 0 "1 cycle for 1 pixel";
285        TDMCYCLEFORMAT_1 = 1 "2 cycles for 1 pixel";
286        TDMCYCLEFORMAT_2 = 2 "3 cycles for 1 pixel";
287        TDMCYCLEFORMAT_3 = 3 "3 cycles for 2 pixels";
288    };
289
290    constants tdmparallelmode_status width(2) "" {
291        TDMPARALLELMODE_0 = 0 "8-bit parallel output interface selected";
292        TDMPARALLELMODE_1 = 1 "9-bit parallel output interface selected";
293        TDMPARALLELMODE_2 = 2 "12-bit parallel output interface selected";
294        TDMPARALLELMODE_3 = 3 "16-bit parallel output interface selected";
295    };
296
297    constants tdmenable_status width(1) "" {
298        TDMENABLE_0 = 0 "TDM disabled";
299        TDMENABLE_1 = 1 "TDM enabled";
300    };
301
302    constants gpout1_status width(1) "" {
303        GPOUT1_0 = 0 "The GPout1 is reset";
304        GPOUT1_1 = 1 "The GPout1 is set";
305    };
306
307    constants gpout0_status width(1) "" {
308        GPOUT0_0 = 0 "The GPout0 is reset";
309        GPOUT0_1 = 1 "The GPout0 is set";
310    };
311
312    constants gpin1_status width(1) "" {
313        GPIN1_0_r = 0 "The GPin1 has been reset";
314        GPIN1_1_r = 1 "The GPin1 has been set";
315    };
316
317    constants gpin0_status width(1) "" {
318        GPIN0_0_r = 0 "The GPin0 has been reset";
319        GPIN0_1_r = 1 "The GPin0 has been set";
320    };
321
322    constants stallmode_status width(1) "" {
323        STALLMODE_0 = 0 "Normal mode selected";
324        STALLMODE_1 = 1 "STALL mode selected. The Display Controller sends the data without considering the VSYNC/HSYNC. The LCD output is disabled at the end of the transfer of the frame. The S/W has to re-enable the LCD output in order to generate a new frame. The stall mode is used in RFBI and DSI command modes.";
325    };
326
327    constants tftdatalines_status width(2) "" {
328        TFTDATALINES_0 = 0 "12-bit output aligned on the LSB of the pixel data interface";
329        TFTDATALINES_1 = 1 "16-bit output aligned on the LSB of the pixel data interface";
330        TFTDATALINES_2 = 2 "18-bit output aligned on the LSB of the pixel data interface";
331        TFTDATALINES_3 = 3 "24-bit output aligned on the LSB of the pixel data interface";
332    };
333
334    constants gotv_status width(1) "" {
335        GOTV_0 = 0 "The hardware has finished updating the internal shadow registers of the pipeline(s) associated with the TV output using the user values. The hardware resets the bit when the update is completed.";
336        GOTV_1 = 1 "The user has finished to program the shadow registers of the pipeline(s) associated with the TV output and the hardware can update the internal registers at the external VSYNC.";
337    };
338
339    constants golcd_status width(1) "" {
340        GOLCD_0 = 0 "The hardware has finished updating the internal shadow registers of the pipeline(s) connected to the LCD output using the user values. The hardware resets the bit when the update is completed.";
341        GOLCD_1 = 1 "The user has finished to program the shadow registers of the pipeline(s) associated with the LCD output and the hardware can update the internal registers at the VFP start period";
342    };
343
344    constants stntft_status width(1) "" {
345        STNTFT_0 = 0 "Passive or STN display operation enabled. STN dither logic is enabled.";
346        STNTFT_1 = 1 "Active or TFT display operation enabled. STN Dither logic and output FIFO bypassed.";
347    };
348
349    constants monocolor_status width(1) "" {
350        MONOCOLOR_0 = 0 "Color operation enabled (STN mode only)";
351        MONOCOLOR_1 = 1 "Monochrome operation enabled (STN mode only)";
352    };
353
354    constants tvenable_status width(1) "" {
355        TVENABLE_0 = 0 "TV output disabled (at the end of the current field if interlace output when the bit is reset)";
356        TVENABLE_1 = 1 "TV output enabled";
357    };
358
359    constants lcdenable_status width(1) "" {
360        LCDENABLE_0 = 0 "LCD output disabled (at the end of the frame when the bit is reset)";
361        LCDENABLE_1 = 1 "LCD output enabled";
362    };
363    
364    register dispc_control1 addr(base, 0x40) "The control register configures the Display Controller module for the primary LCD and TV outputs." {
365        spatialtemporal_ditheringframes 2 rw type(spatialtemporal_ditheringframes_status) "Spatial/Temporal dithering number of frames for the primary LCD output wr: VFP start period of primary LCD";
366        lcdenablepol 1 ro "Write 0s for future compatibility. Reads return 0.";
367        lcdenablesignal 1 ro "Write 0s for future compatibility. Reads return 0.";
368        pckfreeenable 1 ro "Write 0s for future compatibility. Reads return 0.";
369        tdmunusedbits 2 rw type(tdmunusedbits_status) "State of unused bits (TDM mode only) for the primary LCD output. wr: VFP start period of primary LCD";
370        tdmcycleformat 2 rw type(tdmcycleformat_status) "Cycle format (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD";
371        tdmparallelmode 2 rw type(tdmparallelmode_status) "Output Interface width (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD";
372        tdmenable 1 rw type(tdmenable_status) "Enable the multiple cycle format (TDM mode only used for TFT mode with the RFBI enable bit off) for the primary LCD output. wr: VFP start period of primary LCD";
373        ht 3 rw "Hold Time for TV output wr: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)";
374        gpout1 1 rw type(gpout1_status) "General Purpose Output Signal wr:immediate";
375        gpout0 1 rw type(gpout0_status) "General Purpose Output Signal wr:immediate";
376        gpin1 1 ro type(gpin1_status) "General Purpose Input Signal wr: immediately";
377        gpin0 1 ro type(gpin0_status) "General Purpose Input Signal wr: immediately";
378        overlayopti_mization 1 rw type(sidlemode_status) "Overlay Optimization for the primary LCD output wr: VFP start period of the primary LCD";
379        stallmode 1 rw type(stallmode_status) "STALL Mode for the primary LCD output wr: VFP start period of primary LCD";
380        _ 1 mbz;
381        tftdatalines 2 rw type(tftdatalines_status) "Number of lines of the primary LCD interface wr: VFP start period of primary LCD";
382        stditherenable 1 rw type(sidlemode_status) "Spatial Temporal dithering enable for the primary LCD output wr: VFP start period of primary LCD";
383        gotv 1 rw type(gotv_status) "GO Command for the TV output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the TV output. wr: immediate";
384        golcd 1 rw type(golcd_status) "GO Command for the primary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the primary LCD output. wr: immediate";
385        m8b 1 rw type(sidlemode_status) "Mono 8-bit mode of the primary LCD wr: VFP start period of primary LCD output";
386        stntft 1 rw type(stntft_status) "LCD Display type of the primary LCD wr: VFP start period of primary LCD output";
387        monocolor 1 rw type(monocolor_status) "Monochrome/Color selection for the primary LCD wr: VFP start period of primary LCD output";
388        tvenable 1 rw type(tvenable_status) "Enable the TV output wr: immediate effect only occurs at the end of the current frame.";
389        lcdenable 1 rw type(lcdenable_status) "Enable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frame";
390    };
391
392    constants fullrange_status width(1) "" {
393        FULLRANGE_0 = 0 "Limited range selected.";
394        FULLRANGE_1 = 1 "Full range selected.";
395    };
396
397    constants colorconv_enable_status width(1) "" {
398        COLORCONV_ENABLE_0 = 0 "Disable Color Space Conversion RGB to YUV";
399        COLORCONV_ENABLE_1 = 1 "Enable Color Space Conversion RGB to YUV";
400    };
401
402    constants fidfirst_status width(1) "" {
403        FIDFIRST_0 = 0 "First field is even.";
404        FIDFIRST_1 = 1 "Odd field is first.";
405    };
406
407    constants outputmode_enable_status width(1) "" {
408        OUTPUTMODE_ENABLE_0 = 0 "Progressive mode selected.";
409        OUTPUTMODE_ENABLE_1 = 1 "Interlace mode selected.";
410    };
411
412    constants tvalphablender_enable_status width(1) "" {
413        TVALPHABLENDER_ENABLE_0 = 0 "Alpha blender is disabled.";
414        TVALPHABLENDER_ENABLE_1 = 1 "The alpha blender is enabled.";
415    };
416
417    constants lcdalphablender_enable_status width(1) "" {
418        LCDALPHABLENDER_ENABLE_0 = 0 "Alpha blender is disabled. The color key alpha blending is used.";
419        LCDALPHABLENDER_ENABLE_1 = 1 "The alpha blender is enabled.";
420    };
421
422    constants bufferfilling_status width(1) "" {
423        BUFFERFILLING_0 = 0 "Each DMA buffer is refilled when it reaches LOW threshold.";
424        BUFFERFILLING_1 = 1 "All DMA buffers are refilled up to high threshold when at least one of them reaches the LOW threshold. (only active DMA buffers shall be considered and when reaching the end of the frame the DMA buffer goes to empty condition so no need to fill it again).";
425    };
426
427    constants bufferhand_check_status width(1) "" {
428        BUFFERHAND_CHECK_0 = 0 "Only the STALL signal (generated by RFBI, DSI1 or DSI2 depending on which IP uses the LCD output) is used regardless of the DMA buffer fullness information in order to provide data to the RFBI,DSI1 or DS2 module.";
429        BUFFERHAND_CHECK_1 = 1 "The STALL signal (generated by RFBI, DSI1 or DSI2 depending on which IP uses the LCD output) is used in combination with the DMA buffer fullness information in order to provide data to the RFBI, DSI1 or DSI2 module only when it does not generated buffer underflow.";
430    };
431
432    constants cpr_status width(1) "" {
433        CPR_0 = 0 "Color Phase Rotation Disabled";
434        CPR_1 = 1 "Color Phase Rotation Enabled";
435    };
436
437    constants buffermerge_status width(1) "" {
438        BUFFERMERGE_0 = 0 "DMA buffer merge disabled Each DMA buffer is dedicated to one pipeline.";
439        BUFFERMERGE_1 = 1 "DMA buffer merge enabled All the DMA buffers are merged into a single one to be used by the single active pipeline.";
440    };
441
442    constants tcktv_selection_status width(1) "" {
443        TCKTV_SELECTION_0 = 0 "Destination transparency color key selected";
444        TCKTV_SELECTION_1 = 1 "Source transparency color key selected";
445    };
446
447    constants gamatable_enable_status width(1) "" {
448        GAMATABLE_ENABLE_0 = 0 "Gamma table LDC2 and TV are bypassed";
449        GAMATABLE_ENABLE_1 = 1 "Gamma table LCD2 and TV are enabled";
450    };
451
452    constants acbiasgated_status width(1) "" {
453        ACBIASGATED_0 = 0 "AcBias Gated Disabled";
454        ACBIASGATED_1 = 1 "AcBias Gated Enabled";
455    };
456
457    constants vsyncgated_status width(1) "" {
458        VSYNCGATED_0 = 0 "VSYNC Gated Disabled";
459        VSYNCGATED_1 = 1 "VSYNC Gated Enabled";
460    };
461
462    constants hsyncgated_status width(1) "" {
463        HSYNCGATED_0 = 0 "HSYNC Gated Disabled";
464        HSYNCGATED_1 = 1 "HSYNC Gated Enabled";
465    };
466
467    constants pixelclock_gated_status width(1) "" {
468        PIXELCLOCK_GATED_0 = 0 "Pixel Clock Gated Disabled";
469        PIXELCLOCK_GATED_1 = 1 "Pixel Clock Gated Enabled";
470    };
471
472    constants pixeldatagated_status width(1) "" {
473        PIXELDATAGATED_0 = 0 "Pixel Data Gated Disabled";
474        PIXELDATAGATED_1 = 1 "Pixel Data Gated Enabled";
475    };
476
477    constants palettegamma_table_status width(1) "" {
478        PALETTEGAMMA_TABLE_0 = 0 "LUT used as palette (only if graphics format is BITMAP1, 2, 4, and 8)";
479        PALETTEGAMMA_TABLE_1 = 1 "LUT used as gamma table (only if graphics format is NOT BITMAP1, 2, 4, and 8 or no graphics window present)";
480    };
481
482    constants loadmode_status width(2) "" {
483        LOADMODE_0 = 0 "Palette/Gamma Table and data are loaded every frame";
484        LOADMODE_1 = 1 "Palette/Gamma Table to be loaded. The user sets the bit when the palette/gamma table has to be loaded. Hardware resets the bit to 0x2 when table has been loaded. (.ENABLE has to be set to 1).";
485        LOADMODE_2 = 2 "Frame data only loaded every frame";
486        LOADMODE_3 = 3 "Palette/Gamma Table and frame data loaded on first frame then switch to 0x2 (Hardware).";
487    };
488
489    constants pixelgated_status width(1) "" {
490        PIXELGATED_0 = 0 "Pixel clock always toggles (only in TFT mode)";
491        PIXELGATED_1 = 1 "Pixel clock only toggles when there is valid data to display. (only in TFT mode)";
492    };
493    
494    register dispc_config1 addr(base, 0x44) "The control register configures the Display Controller module for the primary LCD output and TV output. Shadow register, updated on VFP start period of primary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
495        _ 6 mbz;
496        fullrange 1 rw type(fullrange_status) "Color Space Conversion full range setting. wr: VFP start of primary LCD";
497        colorconv_enable 1 rw type(colorconv_enable_status) "Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. wr: VFP start of primary LCD";
498        fidfirst 1 rw type(fidfirst_status) "Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. wr: VFP start of primary LCD";
499        outputmode_enable 1 rw type(outputmode_enable_status) "Selects between progressive and interlace mode for the primary LCD output. wr: VFP start of primary LCD";
500        _ 2 mbz;
501        tvalphablender_enable 1 rw type(tvalphablender_enable_status) "Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated pipeline connected to the TV output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: EVSYNC start of primary LCD";
502        lcdalphablender_enable 1 rw type(lcdalphablender_enable_status) "Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated with the primary LCD output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: VFP start of primary LCD";
503        bufferfilling 1 rw type(bufferfilling_status) "Controls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold. wr: immediate";
504        bufferhand_check 1 rw type(bufferhand_check_status) "Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (primary LCD output) wr: VFP start of primary LCD";
505        cpr 1 rw type(cpr_status) "Color Phase Rotation Control (primary LCD output). It shall be reset when ColorConvEnable bit field is set to 1 wr: VFP start period of primary LCD output";
506        buffermerge 1 rw type(buffermerge_status) "Buffer merge control wr: EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory or VFP When enabled, the DISPC_GLOBAL_BUFFER register is ignored. This bit must be set to zero when the write back channel is used. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero. wr: immediate";
507        tcktv_selection 1 rw type(tcktv_selection_status) "Transparency Color Key Selection (TV output) wr: EVSYNC";
508        tcktvenable 1 rw type(sync_losttv_en_status) "Transparency Color Key Enabled (TV output) wr: EVSYNC";
509        tcklcd_selection 1 rw type(tcktv_selection_status) "Transparency Color Key Selection (primary LCD output) wr: VFP start period of primary LCD output";
510        tcklcdenable 1 rw type(frame_done2_en_status) "Transparency Color Key Enabled (primary LCD output) wr: VFP start period of primary LCD output";
511        gamatable_enable 1 rw type(gamatable_enable_status) "For backward compatibility, an enable bit has been added on the 2 additional gamma tables (secondary display and TV). Gamma table of LCD1 is always enabled.";
512        acbiasgated 1 rw type(acbiasgated_status) "ACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
513        vsyncgated 1 rw type(vsyncgated_status) "VSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
514        hsyncgated 1 rw type(hsyncgated_status) "HSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
515        pixelclock_gated 1 rw type(pixelclock_gated_status) "Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
516        pixeldatagated 1 rw type(pixeldatagated_status) "Pixel Data Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
517        palettegamma_table 1 rw type(palettegamma_table_status) "Palette/Gamma Table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the graphics pipeline: primary LCD, secondary LCD, TV output or write-back to the memory. In case of the table is used as gamma table, it is used for the primary LCD output only.";
518        loadmode 2 rw type(loadmode_status) "Loading Mode for the Palette/Gamma Table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory";
519        pixelgated 1 rw type(pixelgated_status) "Pixel Gated Enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD output";
520    };
521    
522    register dispc_default_color0 addr(base, 0x4C) "The control register allows to configure the default solid background color for the primary LCD. Shadow register, updated on VFP start period of the primary LCD" {
523        _ 8 mbz;
524        defaultcolor 24 rw "24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.";
525    };
526    
527    register dispc_default_color1 addr(base, 0x50) "The control register allows to configure the default solid background color for the TV output. Shadow register, updated on EVSYNC" {
528        _ 8 mbz;
529        defaultcolor 24 rw "24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.";
530    };
531    
532    register dispc_trans_color0 addr(base, 0x54) "The register sets the transparency color value for the video/graphics overlays for the primary LCD output. Shadow register, updated on VFP start period of the primary LCD" {
533        _ 8 mbz;
534        transcolorkey 24 rw "Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24";
535    };
536    
537    register dispc_trans_color1 addr(base, 0x58) "The register sets the transparency color value for the video/graphics overlays for the TV output. Shadow register, updated on EVSYNC" {
538        _ 8 mbz;
539        transcolorkey 24 rw "Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24";
540    };
541    
542    register dispc_line_status addr(base, 0x5C) "The control register indicates the current primary LCD panel display line number." {
543        _ 21 mbz;
544        linenumber 11 ro "Current LCD panel line number Current display line number. The first active line has the value 0. During blanking lines the line number is not incremented.";
545    };
546    
547    register dispc_line_number addr(base, 0x60) "The control register indicates the primary LCD panel display line number for the interrupt and the DMA request. Shadow register, updated on VFP start period of primary LCD." {
548        _ 21 mbz;
549        linenumber 11 rw "LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs.";
550    };
551    
552    register dispc_timing_h1 addr(base, 0x64) "The register configures the timing logic for the HSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
553        hbp 12 rw "Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field.";
554        hfp 12 rw "Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field.";
555        hsw 8 rw "Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1). When in BT mode, this field corresponds to the horizontal blanking";
556    };
557    
558    register dispc_timing_v1 addr(base, 0x68) "The register configures the timing logic for the VSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
559        vbp 12 rw "Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame.";
560        vfp 12 rw "Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame.";
561        vsw 8 rw "Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode. In passive mode, encoded value (from 1 to 256) to specify the number of extra line clock periods (program to value minus 1) to insert after the vertical front porch (VFP) period has elapsed.";
562    };
563
564    constants align_status width(1) "" {
565        ALIGN_0 = 0 "VSYNC and HSYNC are not aligned";
566        ALIGN_1 = 1 "VSYNC and HSYNC assertions are aligned.";
567    };
568
569    constants onoff_status width(1) "" {
570        ONOFF_0 = 0 "HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data";
571        ONOFF_1 = 1 "HSYNC and VSYNC are driven according to bit 16";
572    };
573    
574    register dispc_pol_freq1 addr(base, 0x6C) "The register configures the signal configuration. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD." {
575        _ 13 mbz;
576        align 1 rw type(align_status) "Defines the alignment between HSYNC and VSYNC assertion.";
577        onoff 1 rw type(onoff_status) "HSYNC/VSYNC Pixel clock Control On/Off";
578        rf 1 rw type(onoff_status) "Program HSYNC/VSYNC Rise or Fall";
579        ieo 1 rw type(sidlemode_status) "Invert output enable";
580        ipc 1 rw type(frame_done2_en_status) "Invert pixel clock";
581        ihs 1 rw type(sidlemode_status) "Invert HSYNC";
582        ivs 1 rw type(sidlemode_status) "Invert VSYNC";
583        acbi 4 rw "AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions";
584        acb 8 rw "AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display.";
585    };
586    
587    register dispc_divisor1 addr(base, 0x70) "The register configures the divisors. It is used for the primary LCD output Shadow register, updated on VFP start period of primary LCD" {
588        _ 8 mbz;
589        lcd 8 rw "Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK. The value 0 is invalid.";
590        _ 8 mbz;
591        pcd 8 rw "Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided byDISPC_DIVISOR1.LCD value. The values 0 is invalid.";
592    };
593    
594    register dispc_global_alpha addr(base, 0x74) "The register defines the global alpha value for the graphics and three video pipelines. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory for each bit field depending on the association of the each pipeline with the primary LCD, secondary LCD or TV output." {
595        vid3globalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
596        vid2globalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
597        vid1globalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
598        gfxglobalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
599    };
600
601    constants delta_lpp_status width(2) "" {
602        DELTA_LPP_0 = 0 "Same size";
603        DELTA_LPP_1 = 1 "Odd size = Even size +1";
604        DELTA_LPP_2 = 2 "Odd size = Even Size -1";
605    };
606    
607    register dispc_size_tv addr(base, 0x78) "The register configures the size of the TV output field (interlace), frame (progressive) (horizontal and vertical). Shadow register, updated on EVSYNC. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." {
608        _ 5 mbz;
609        lpp 11 rw "Lines per panel (LPP). Encoded value (from 1 to 2048) to specify the number of LPP.";
610        delta_lpp 2 rw type(delta_lpp_status) "Indicates the delta size value of the odd field compared to the even field";
611        _ 3 mbz;
612        ppl 11 rw "Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display.";
613    };
614
615    constants delta_lpp_status1 width(2) "" {
616        DELTA_LPP_0_1 = 0 "same size";
617        DELTA_LPP_1_1 = 1 "Odd size = Even size +1";
618        DELTA_LPP_2_1 = 2 "Odd size = Even Size -1";
619    };
620    
621    register dispc_size_lcd1 addr(base, 0x7C) "The register configures the panel size (horizontal and vertical). Shadow register, updated on VFP start period of primary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." {
622        _ 5 mbz;
623        lpp 11 rw "Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1).";
624        delta_lpp 2 rw type(delta_lpp_status1) "Indicates the delta size value of the odd field compared to the even field";
625        _ 3 mbz;
626        ppl 11 rw "Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid.";
627    };
628    
629    register dispc_gfx_ba_j_0 rw addr(base, 0x80) "The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output and 0 and 1 when on the TV output). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
630    
631    register dispc_gfx_ba_j_1 rw addr(base, 0x84) "The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output and 0 and 1 when on the TV output). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
632    
633    register dispc_gfx_position addr(base, 0x88) "The register configures the position of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
634        _ 5 mbz;
635        posy 11 rw "Y position of the graphics window. Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0.";
636        _ 5 mbz;
637        posx 11 rw "X position of the graphics window. Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0.";
638    };
639    
640    register dispc_gfx_size addr(base, 0x8C) "The register configures the size of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
641        _ 5 mbz;
642        sizey 11 rw "Number of lines of the graphics window. Encoded value (from 1 to 2048) to specify the number of lines of the graphics window (program to value minus 1).";
643        _ 5 mbz;
644        sizex 11 rw "Number of pixels of the graphics window. Encoded value (from 1 to 2048) to specify the number of pixels per line of the graphics window (program to value minus 1).";
645    };
646
647    constants channelout2_status width(2) "" {
648        CHANNELOUT2_0 = 0 "primary LCD output selected.";
649        CHANNELOUT2_1 = 1 "Secondary LCD output selected.";
650        CHANNELOUT2_3 = 3 "Write-back output to the memory selected.";
651    };
652
653    constants bursttype_status width(1) "" {
654        BURSTTYPE_0 = 0 "INC burst type is used.";
655        BURSTTYPE_1 = 1 "2D block burst type is used.";
656    };
657
658    constants premultiplyalpha_status width(1) "" {
659        PREMULTIPLYALPHA_0 = 0 "Non premultiplyalpha data color component";
660        PREMULTIPLYALPHA_1 = 1 "Premultiplyalpha data color component";
661    };
662
663    constants zorderenable_status width(1) "" {
664        ZORDERENABLE_0 = 0 "Z-order disabled. The Z-order of the layer is 0.";
665        ZORDERENABLE_1 = 1 "Z-order enabled. The Z-order is defined by the bit field ZORDER (bits 26 and 27).";
666    };
667
668    constants antiflicker_status width(1) "" {
669        ANTIFLICKER_0 = 0 "Antiflicker disabled.";
670        ANTIFLICKER_1 = 1 "Antiflicker enabled.";
671    };
672
673    constants selfrefresh_status width(1) "" {
674        SELFREFRESH_0 = 0 "The graphics pipeline accesses the interconnect to fetch data from the system memory.";
675        SELFREFRESH_1 = 1 "The graphics pipeline does not need anymore to fetch data from memory. Only the graphics DMA buffer is used. It takes effect after the frame has been loaded in the DMA buffer.";
676    };
677
678    constants rotation_status width(2) "" {
679        ROTATION_0 = 0 "No rotation";
680        ROTATION_1 = 1 "Rotation by 90 degrees";
681        ROTATION_3 = 3 "Rotation by 270 degrees";
682        ROTATION_2 = 2 "Rotation by 180 degrees";
683    };
684
685    constants nibblemode_status width(1) "" {
686        NIBBLEMODE_0 = 0 "Nibble mode is disabled";
687        NIBBLEMODE_1 = 1 "Nibble mode is enabled";
688    };
689
690    constants channelout_status width(1) "" {
691        CHANNELOUT_0 = 0 "LCD output or WB to the memory selected. bit fields 31 and 30 defines the output associated (primary, secondary or write-back).";
692        CHANNELOUT_1 = 1 "TV output selected";
693    };
694
695    constants burstsize_status width(2) "" {
696        BURSTSIZE_0 = 0 "2x128bit bursts";
697        BURSTSIZE_1 = 1 "4x128bit bursts";
698        BURSTSIZE_3 = 3 "Reserved";
699        BURSTSIZE_2 = 2 "8x128bit bursts";
700    };
701
702    constants replicationenable_status width(1) "" {
703        REPLICATIONENABLE_0 = 0 "Disable Graphics replication logic. The conversion to ARGB32-8888 is done by adding 0s for the LSBs";
704        REPLICATIONENABLE_1 = 1 "Enable Graphics replication logic. The conversion to ARGB32-8888 is done by duplicating the MSBs for the LSBs";
705    };
706
707    constants format_status width(4) "" {
708        FORMAT_6 = 6 "RGB16-565";
709        FORMAT_1 = 1 "BITMAP2 (CLUT is required to be used)";
710        FORMAT_10 = 10 "RGBx12-4444";
711        FORMAT_7 = 7 "ARGB16-1555";
712        FORMAT_13 = 13 "RGBA32-8888";
713        FORMAT_0 = 0 "BITMAP1 (CLUT is required to be used)";
714        FORMAT_2 = 2 "BITMAP4 (CLUT is required to be used)";
715        FORMAT_8 = 8 "xRGB24-8888 (32-bit container)";
716        FORMAT_9 = 9 "RGB24-888 (24-bit container)";
717        FORMAT_11 = 11 "RGBA12-4444";
718        FORMAT_4 = 4 "xRGB12-4444";
719        FORMAT_5 = 5 "ARGB16-4444";
720        FORMAT_15 = 15 "xRGB15-1555";
721        FORMAT_12 = 12 "ARGB32-8888";
722        FORMAT_3 = 3 "BITMAP8 (CLUT is required to be used)";
723        FORMAT_14 = 14 "RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)";
724    };
725    
726    register dispc_gfx_attributes addr(base, 0xA0) "The register configures the graphics attributes. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
727        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero) wr: immediate";
728        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. (It does not apply to the palette loading OCP requests using INCR burst only)";
729        premultiplyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
730        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
731        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
732        antiflicker 1 rw type(antiflicker_status) "Antiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4, 1/2, 1/4)";
733        _ 6 mbz;
734        selfrefreshauto 1 rw type(sidlemode_status) "Automatic self-refresh mode";
735        _ 1 mbz;
736        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the graphics window from its own DMA buffer. This bit should be set only after having set the GO bit of the channel and read back a zero in its field.";
737        arbitration 1 rw type(sidlemode_status) "Determines the priority of the graphics pipeline. When the graphics pipeline is one of the high priority pipelines. The arbitration wheel gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
738        rotation 2 rw type(rotation_status) "Graphics Rotation Flag";
739        bufpreload 1 rw type(sidlemode_status) "Graphics Preload Value";
740        _ 1 mbz;
741        nibblemode 1 rw type(nibblemode_status) "Graphics Nibble Mode (only for 1-, 2- and 4-bpp)";
742        channelout 1 rw type(channelout_status) "Graphics Channel Out configuration: LCD, WB or TV. wr: immediate";
743        burstsize 2 rw type(burstsize_status) "Graphics DMA Burst Size";
744        replicationenable 1 rw type(replicationenable_status) "Graphics Replication Enabled: RGB . ARGB, and RGBA formats are converted into ARGB32-8888 using replication of the MSBs or '0s";
745        format 4 rw type(format_status) "Graphics format. It defines the pixel format when fetching the graphics picture into memory.";
746        enable 1 rw type(sidlemode_status) "Graphics Enable";
747    };
748    
749    register dispc_gfx_buf_threshold addr(base, 0xA4) "The register configures the graphics buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
750        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
751        buflowthreshold 16 rw "DMA buffer Low Threshold Number of 128-bits defining the threshold value. The value put is this register should always be greater than zero.";
752    };
753    
754    register dispc_gfx_buf_size_status addr(base, 0xA8) "The register defines the Graphics buffer size" {
755        _ 16 mbz;
756        bufsize 16 ro "DMA buffer Size in number of 128-bits";
757    };
758    
759    register dispc_gfx_row_inc rw addr(base, 0xAC) "The register configures the number of bytes to increment at the end of the row. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
760    
761    register dispc_gfx_pixel_inc addr(base, 0xB0) "The register configures the number of bytes to increment between two pixels. For more information, see, Predecimation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
762        _ 24 mbz;
763        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels.";
764    };
765    
766    register dispc_gfx_table_ba rw addr(base, 0xB8) "The register configures the base address of the palette buffer or the gamma table buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
767    
768    register dispc_vid1_ba_j_0 rw addr(base, 0xBC) "The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
769    
770    register dispc_vid1_ba_j_1 rw addr(base, 0xC0) "The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
771    
772    register dispc_vid1_position addr(base, 0xC4) "The register configures the position of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
773        _ 5 mbz;
774        posy 11 rw "Y position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0.";
775        _ 5 mbz;
776        posx 11 rw "X position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1. The first pixel on the left of the display screen has the X-position 0.";
777    };
778    
779    register dispc_vid1_size addr(base, 0xC8) "The register configures the size of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
780        _ 5 mbz;
781        sizey 11 rw "Number of lines of the video 1 Encoded value (from 1 to 2048) to specify the number of lines of the video window 1. Program to value minus 1.";
782        _ 5 mbz;
783        sizex 11 rw "Number of pixels of the video window 1 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 1. Program to value minus 1.";
784    };
785
786    constants doublestride_status width(1) "" {
787        DOUBLESTRIDE_0 = 0 "The CbCr stride value is equal to the Y stride.";
788        DOUBLESTRIDE_1 = 1 "The CbCr stride value is double to the Y stride.";
789    };
790
791    constants selfrefreshauto_status width(1) "" {
792        SELFREFRESHAUTO_0_1 = 0 "The transition from SELFREFRESH 'disabled' to 'enabled' is controlled by SW.";
793        SELFREFRESHAUTO_1_1 = 1 "The transition from SELFREFRESH 'disabled' to 'enabled' is controlled only by hardware.";
794    };
795
796    constants replicationenable_status1 width(1) "" {
797        REPLICATIONENABLE_0_1 = 0 "Disable Video replication logic";
798        REPLICATIONENABLE_1_1 = 1 "Enable Video replication logic";
799    };
800
801    constants colorconvenable_status width(1) "" {
802        COLORCONVENABLE_0 = 0 "Disable Color Space Conversion YUV to RGB";
803        COLORCONVENABLE_1 = 1 "Enable Color Space Conversion YUV to RGB";
804    };
805
806    constants resizeenable_status width(2) "" {
807        RESIZEENABLE_0 = 0 "Disable both horizontal and vertical resize processing";
808        RESIZEENABLE_1 = 1 "Enable the horizontal resize processing";
809        RESIZEENABLE_3 = 3 "Enable both horizontal and vertical resize processing";
810        RESIZEENABLE_2 = 2 "Enable the vertical resize processing";
811    };
812
813    constants format_status1 width(4) "" {
814        FORMAT_6_1 = 6 "RGB16-565";
815        FORMAT_1_1 = 1 "RGB12x-4444";
816        FORMAT_10_1 = 10 "YUV2 4:2:2 co-sited";
817        FORMAT_7_1 = 7 "ARGB16-1555";
818        FORMAT_13_1 = 13 "RGBA32-8888";
819        FORMAT_0_1 = 0 "NV12 4:2:0 2 buffers (Y + UV)";
820        FORMAT_2_1 = 2 "RGBA12-4444";
821        FORMAT_8_1 = 8 "xRGB24-8888 (32-bit container)";
822        FORMAT_9_1 = 9 "RGB24-888 (24-bit container)";
823        FORMAT_11_1 = 11 "UYVY 4:2:2 co-sited";
824        FORMAT_5_1 = 5 "ARGB16-4444";
825        FORMAT_15_1 = 15 "xRGB15-1555";
826        FORMAT_12_1 = 12 "ARGB32-8888";
827        FORMAT_4_1 = 4 "xRGB12-4444";
828        FORMAT_14_1 = 14 "RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)";
829    };
830    
831    register dispc_vid1_attributes addr(base, 0xCC) "The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
832        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate";
833        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
834        premultiphyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
835        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
836        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
837        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the video window from its own DMA buffer only.";
838        arbitration 1 rw type(sidlemode_status) "Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
839        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
840        verticaltaps 1 rw type(sidlemode_status) "Video Vertical Resize Tap Number. The vertical polyphase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap compared to 5-tap.";
841        dmaoptimization 1 ro "Write 0s for future compatibility. Reads return 0.";
842        bufpreload 1 rw type(sidlemode_status) "Video Preload Value";
843        _ 1 mbz;
844        selfrefreshauto 1 rw type(selfrefreshauto_status) "Automatic self-refresh mode";
845        channelout 1 rw type(channelout_status) "Video Channel Out configuration: LCD, WB or TV. wr: immediate";
846        burstsize 2 rw type(burstsize_status) "Video DMA Burst Size";
847        rotation 2 rw type(rotation_status) "Video Rotation Flag";
848        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
849        replicationenable 1 rw type(replicationenable_status1) "Replication Enable";
850        colorconvenable 1 rw type(colorconvenable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
851        vresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
852        hresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
853        resizeenable 2 rw type(resizeenable_status) "Video Resize Enable";
854        format 4 rw type(format_status1) "Video Format. It defines the pixel format when fetching the video 1 picture into memory.";
855        enable 1 rw type(tdmparallelmode_status) "Video Enable";
856    };
857    
858    register dispc_vid1_buf_threshold addr(base, 0xD0) "The register configures the video buffer associated with the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
859        bufhighthreshold 16 rw "Video DMA buffer High Threshold Number of 128-bits defining the threshold value.";
860        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
861    };
862    
863    register dispc_vid1_buf_size_status addr(base, 0xD4) "The register defines the Video buffer size for the video pipeline 1." {
864        _ 16 mbz;
865        bufsize 16 ro "Video 1 DMA buffer Size in number of 128-bits";
866    };
867    
868    register dispc_vid1_row_inc rw addr(base, 0xD8) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
869    
870    register dispc_vid1_pixel_inc addr(base, 0xDC) "The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
871        _ 24 mbz;
872        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. For YUV4:2:0, Max supported value is 128.";
873    };
874    
875    register dispc_vid1_fir addr(base, 0xE0) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
876        _ 3 mbz;
877        firvinc 13 rw "Vertical increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
878        _ 3 mbz;
879        firhinc 13 rw "Horizontal increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
880    };
881    
882    register dispc_vid1_picture_size addr(base, 0xE4) "The register configures the size of the video picture associated with the video layer 1 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
883        _ 5 mbz;
884        orgsizey 11 rw "Number of lines of the video picture. Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 2.";
885        _ 5 mbz;
886        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 2.";
887    };
888    
889    register dispc_vid1_accu_j_0 addr(base, 0xE8) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
890        _ 5 mbz;
891        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
892        _ 5 mbz;
893        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
894    };
895    
896    register dispc_vid1_accu_j_1 addr(base, 0xEC) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
897        _ 5 mbz;
898        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
899        _ 5 mbz;
900        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
901    };
902    
903    register dispc_vid1_fir_coef_h_i_0 addr(base, 0xF0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
904        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
905        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
906        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
907        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
908    };
909    
910    register dispc_vid1_fir_coef_h_i_1 addr(base, 0xF8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
911        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
912        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
913        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
914        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
915    };
916    
917    register dispc_vid1_fir_coef_h_i_2 addr(base, 0x100) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
918        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
919        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
920        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
921        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
922    };
923    
924    register dispc_vid1_fir_coef_h_i_3 addr(base, 0x108) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
925        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
926        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
927        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
928        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
929    };
930    
931    register dispc_vid1_fir_coef_h_i_4 addr(base, 0x110) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
932        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
933        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
934        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
935        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
936    };
937    
938    register dispc_vid1_fir_coef_h_i_5 addr(base, 0x118) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
939        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
940        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
941        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
942        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
943    };
944    
945    register dispc_vid1_fir_coef_h_i_6 addr(base, 0x120) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
946        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
947        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
948        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
949        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
950    };
951    
952    register dispc_vid1_fir_coef_h_i_7 addr(base, 0x128) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
953        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
954        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
955        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
956        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
957    };
958    
959    register dispc_vid1_fir_coef_hv_i_0 addr(base, 0xF4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
960        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
961        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
962        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
963        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
964    };
965    
966    register dispc_vid1_fir_coef_hv_i_1 addr(base, 0xFC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
967        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
968        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
969        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
970        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
971    };
972    
973    register dispc_vid1_fir_coef_hv_i_2 addr(base, 0x104) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
974        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
975        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
976        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
977        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
978    };
979    
980    register dispc_vid1_fir_coef_hv_i_3 addr(base, 0x10C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
981        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
982        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
983        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
984        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
985    };
986    
987    register dispc_vid1_fir_coef_hv_i_4 addr(base, 0x114) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
988        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
989        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
990        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
991        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
992    };
993    
994    register dispc_vid1_fir_coef_hv_i_5 addr(base, 0x11C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
995        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
996        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
997        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
998        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
999    };
1000    
1001    register dispc_vid1_fir_coef_hv_i_6 addr(base, 0x124) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1002        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1003        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1004        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1005        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1006    };
1007    
1008    register dispc_vid1_fir_coef_hv_i_7 addr(base, 0x12C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1009        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1010        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1011        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1012        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1013    };
1014    
1015    register dispc_vid1_conv_coef0 addr(base, 0x130) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1016        _ 5 mbz;
1017        rcr 11 rw "RCr Coefficient Encoded signed value (from -1024 to 1023).";
1018        _ 5 mbz;
1019        ry 11 rw "RY Coefficient Encoded signed value (from -1024 to 1023).";
1020    };
1021    
1022    register dispc_vid1_conv_coef1 addr(base, 0x134) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1023        _ 5 mbz;
1024        gy 11 rw "GY Coefficient Encoded signed value (from -1024 to 1023).";
1025        _ 5 mbz;
1026        rcb 11 rw "RCb Coefficient Encoded signed value (from -1024 to 1023).";
1027    };
1028    
1029    register dispc_vid1_conv_coef2 addr(base, 0x138) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1030        _ 5 mbz;
1031        gcb 11 rw "GCb Coefficient Encoded signed value (from -1024 to 1023).";
1032        _ 5 mbz;
1033        gcr 11 rw "GCr Coefficient Encoded signed value (from -1024 to 1023).";
1034    };
1035    
1036    register dispc_vid1_conv_coef3 addr(base, 0x13C) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1037        _ 5 mbz;
1038        bcr 11 rw "BCr coefficient Encoded signed value (from -1024 to 1023).";
1039        _ 5 mbz;
1040        by 11 rw "BY coefficient Encoded signed value (from -1024 to 1023).";
1041    };
1042    
1043    register dispc_vid1_conv_coef4 addr(base, 0x140) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1044        _ 21 mbz;
1045        bcb 11 rw "BCb Coefficient Encoded signed value (from -1024 to 1023).";
1046    };
1047    
1048    register dispc_vid2_ba_j_0 rw addr(base, 0x14C) "The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
1049    
1050    register dispc_vid2_ba_j_1 rw addr(base, 0x150) "The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
1051    
1052    register dispc_vid2_position addr(base, 0x154) "The register configures the position of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1053        _ 5 mbz;
1054        posy 11 rw "Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0.";
1055        _ 5 mbz;
1056        posx 11 rw "X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0.";
1057    };
1058    
1059    register dispc_vid2_size addr(base, 0x158) "The register configures the size of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1060        _ 5 mbz;
1061        sizey 11 rw "Number of lines of the video 2 Encoded value (from 1 to 2048) to specify the number of lines of the video window 2. Program to value minus 1.";
1062        _ 5 mbz;
1063        sizex 11 rw "Number of pixels of the video window 2 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 2. Program to value minus 1.";
1064    };
1065    
1066    register dispc_vid2_attributes addr(base, 0x15C) "The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1067        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero)";
1068        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
1069        premultiplyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
1070        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
1071        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
1072        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the video window from its own DMA buffer only.";
1073        arbitration 1 rw type(tdmparallelmode_status) "Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
1074        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
1075        verticaltaps 1 rw type(tdmparallelmode_status) "Video Vertical Resize Tap Number";
1076        dmaoptimization 1 ro "Write 0s for future compatibility. Reads return 0.";
1077        bufpreload 1 rw type(tdmparallelmode_status) "Video Preload Value";
1078        _ 1 mbz;
1079        selfrefreshauto 1 rw type(selfrefreshauto_status) "Automatic self-refresh mode";
1080        channelout 1 rw type(channelout_status) "Video Channel Out configuration: LCD, WB or TV. wr: immediate";
1081        burstsize 2 rw type(burstsize_status) "Video DMA Burst Size";
1082        rotation 2 rw type(rotation_status) "Video Rotation Flag";
1083        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
1084        replicationenable 1 rw type(replicationenable_status1) "Replication Enable";
1085        colorconvenable 1 rw type(colorconvenable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
1086        vresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
1087        hresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
1088        resizeenable 2 rw type(resizeenable_status) "Video Resize Enable";
1089        format 4 rw type(format_status1) "Video Format. It defines the pixel format when fetching the video 2 picture into memory.";
1090        enable 1 rw type(tdmparallelmode_status) "VidEnable";
1091    };
1092    
1093    register dispc_vid2_buf_threshold addr(base, 0x160) "The register configures the DMA buffer associated with the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1094        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
1095        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
1096    };
1097    
1098    register dispc_vid2_buf_size_status addr(base, 0x164) "The register defines the DMA buffer size for the video pipeline 2." {
1099        _ 16 mbz;
1100        bufsize 16 ro "DMA buffer size in number of 128 bits";
1101    };
1102    
1103    register dispc_vid2_row_inc rw addr(base, 0x168) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
1104    
1105    register dispc_vid2_pixel_inc addr(base, 0x16C) "The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1106        _ 24 mbz;
1107        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. For YUV4:2:0, Max supported value is 128.";
1108    };
1109    
1110    register dispc_vid2_fir addr(base, 0x170) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1111        _ 3 mbz;
1112        firvinc 13 rw "Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
1113        _ 3 mbz;
1114        firhinc 13 rw "Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
1115    };
1116    
1117    register dispc_vid2_picture_size addr(base, 0x174) "The register configures the size of the video picture associated with the video layer 2 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1118        _ 5 mbz;
1119        orgsizey 11 rw "Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
1120        _ 5 mbz;
1121        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
1122    };
1123    
1124    register dispc_vid2_accu_j_0 addr(base, 0x178) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1125        _ 5 mbz;
1126        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
1127        _ 5 mbz;
1128        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
1129    };
1130    
1131    register dispc_vid2_accu_j_1 addr(base, 0x17C) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1132        _ 5 mbz;
1133        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
1134        _ 5 mbz;
1135        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
1136    };
1137    
1138    register dispc_vid2_fir_coef_h_i_0 addr(base, 0x180) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1139        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1140        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1141        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1142        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1143    };
1144    
1145    register dispc_vid2_fir_coef_h_i_1 addr(base, 0x188) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1146        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1147        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1148        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1149        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1150    };
1151    
1152    register dispc_vid2_fir_coef_h_i_2 addr(base, 0x190) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1153        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1154        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1155        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1156        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1157    };
1158    
1159    register dispc_vid2_fir_coef_h_i_3 addr(base, 0x198) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1160        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1161        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1162        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1163        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1164    };
1165    
1166    register dispc_vid2_fir_coef_h_i_4 addr(base, 0x1A0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1167        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1168        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1169        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1170        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1171    };
1172    
1173    register dispc_vid2_fir_coef_h_i_5 addr(base, 0x1A8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1174        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1175        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1176        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1177        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1178    };
1179    
1180    register dispc_vid2_fir_coef_h_i_6 addr(base, 0x1B0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1181        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1182        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1183        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1184        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1185    };
1186    
1187    register dispc_vid2_fir_coef_h_i_7 addr(base, 0x1B8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1188        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1189        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1190        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1191        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1192    };
1193    
1194    register dispc_vid2_fir_coef_hv_i_0 addr(base, 0x184) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1195        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1196        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1197        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1198        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1199    };
1200    
1201    register dispc_vid2_fir_coef_hv_i_1 addr(base, 0x18C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1202        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1203        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1204        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1205        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1206    };
1207    
1208    register dispc_vid2_fir_coef_hv_i_2 addr(base, 0x194) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1209        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1210        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1211        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1212        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1213    };
1214    
1215    register dispc_vid2_fir_coef_hv_i_3 addr(base, 0x19C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1216        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1217        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1218        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1219        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1220    };
1221    
1222    register dispc_vid2_fir_coef_hv_i_4 addr(base, 0x1A4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1223        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1224        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1225        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1226        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1227    };
1228    
1229    register dispc_vid2_fir_coef_hv_i_5 addr(base, 0x1AC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1230        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1231        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1232        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1233        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1234    };
1235    
1236    register dispc_vid2_fir_coef_hv_i_6 addr(base, 0x1B4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1237        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1238        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1239        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1240        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1241    };
1242    
1243    register dispc_vid2_fir_coef_hv_i_7 addr(base, 0x1BC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1244        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1245        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1246        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1247        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1248    };
1249    
1250    register dispc_vid2_conv_coef0 addr(base, 0x1C0) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1251        _ 5 mbz;
1252        rcr 11 rw "RCr Coefficient Encoded signed value (from -1024 to 1023).";
1253        _ 5 mbz;
1254        ry 11 rw "RY Coefficient Encoded signed value (from -1024 to 1023).";
1255    };
1256    
1257    register dispc_vid2_conv_coef1 addr(base, 0x1C4) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1258        _ 5 mbz;
1259        gy 11 rw "GY Coefficient Encoded signed value (from -1024 to 1023).";
1260        _ 5 mbz;
1261        rcb 11 rw "RCb Coefficient Encoded signed value (from -1024 to 1023).";
1262    };
1263    
1264    register dispc_vid2_conv_coef2 addr(base, 0x1C8) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1265        _ 5 mbz;
1266        gcb 11 rw "GCb Coefficient Encoded signed value (from -1024 to 1023).";
1267        _ 5 mbz;
1268        gcr 11 rw "GCr Coefficient Encoded signed value (from -1024 to 1023).";
1269    };
1270    
1271    register dispc_vid2_conv_coef3 addr(base, 0x1CC) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1272        _ 5 mbz;
1273        bcr 11 rw "BCr coefficient Encoded signed value (from -1024 to 1023).";
1274        _ 5 mbz;
1275        by 11 rw "BY coefficient Encoded signed value (from -1024 to 1023).";
1276    };
1277    
1278    register dispc_vid2_conv_coef4 addr(base, 0x1D0) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1279        _ 21 mbz;
1280        bcb 11 rw "BCb Coefficient Encoded signed value (from -1024 to 1023).";
1281    };
1282    
1283    register dispc_data1_cycle1 addr(base, 0x1D4) "The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of primary LCD" {
1284        _ 4 mbz;
1285        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
1286        _ 3 mbz;
1287        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1288        _ 4 mbz;
1289        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
1290        _ 3 mbz;
1291        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1292    };
1293    
1294    register dispc_data1_cycle2 addr(base, 0x1D8) "The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of primary LCD" {
1295        _ 4 mbz;
1296        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
1297        _ 3 mbz;
1298        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1299        _ 4 mbz;
1300        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
1301        _ 3 mbz;
1302        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1303    };
1304    
1305    register dispc_data1_cycle3 addr(base, 0x1DC) "The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of primary LCD" {
1306        _ 4 mbz;
1307        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
1308        _ 3 mbz;
1309        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1310        _ 4 mbz;
1311        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
1312        _ 3 mbz;
1313        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1314    };
1315    
1316    register dispc_vid1_fir_coef_v_i_0 addr(base, 0x1E0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1317        _ 16 mbz;
1318        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1319        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1320    };
1321    
1322    register dispc_vid1_fir_coef_v_i_1 addr(base, 0x1E4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1323        _ 16 mbz;
1324        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1325        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1326    };
1327    
1328    register dispc_vid1_fir_coef_v_i_2 addr(base, 0x1E8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1329        _ 16 mbz;
1330        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1331        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1332    };
1333    
1334    register dispc_vid1_fir_coef_v_i_3 addr(base, 0x1EC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1335        _ 16 mbz;
1336        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1337        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1338    };
1339    
1340    register dispc_vid1_fir_coef_v_i_4 addr(base, 0x1F0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1341        _ 16 mbz;
1342        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1343        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1344    };
1345    
1346    register dispc_vid1_fir_coef_v_i_5 addr(base, 0x1F4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1347        _ 16 mbz;
1348        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1349        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1350    };
1351    
1352    register dispc_vid1_fir_coef_v_i_6 addr(base, 0x1F8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1353        _ 16 mbz;
1354        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1355        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1356    };
1357    
1358    register dispc_vid1_fir_coef_v_i_7 addr(base, 0x1FC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1359        _ 16 mbz;
1360        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1361        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1362    };
1363    
1364    register dispc_vid2_fir_coef_v_i_0 addr(base, 0x200) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1365        _ 16 mbz;
1366        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1367        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1368    };
1369    
1370    register dispc_vid2_fir_coef_v_i_1 addr(base, 0x204) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1371        _ 16 mbz;
1372        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1373        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1374    };
1375    
1376    register dispc_vid2_fir_coef_v_i_2 addr(base, 0x208) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1377        _ 16 mbz;
1378        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1379        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1380    };
1381    
1382    register dispc_vid2_fir_coef_v_i_3 addr(base, 0x20C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1383        _ 16 mbz;
1384        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1385        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1386    };
1387    
1388    register dispc_vid2_fir_coef_v_i_4 addr(base, 0x210) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1389        _ 16 mbz;
1390        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1391        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1392    };
1393    
1394    register dispc_vid2_fir_coef_v_i_5 addr(base, 0x214) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1395        _ 16 mbz;
1396        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1397        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1398    };
1399    
1400    register dispc_vid2_fir_coef_v_i_6 addr(base, 0x218) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1401        _ 16 mbz;
1402        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1403        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1404    };
1405    
1406    register dispc_vid2_fir_coef_v_i_7 addr(base, 0x21C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1407        _ 16 mbz;
1408        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1409        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1410    };
1411    
1412    register dispc_cpr1_coef_r addr(base, 0x220) "The register configures the color phase rotation matrix coefficients for the Red component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
1413        rr 10 rw "RR Coefficient Encoded signed value (from -512 to 511).";
1414        _ 1 mbz;
1415        rg 10 rw "RG Coefficient Encoded signed value (from -512 to 511).";
1416        _ 1 mbz;
1417        rb 10 rw "RB Coefficient Encoded signed value (from -512 to 511).";
1418    };
1419    
1420    register dispc_cpr1_coef_g addr(base, 0x224) "The register configures the color phase rotation matrix coefficients for the Green component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
1421        gr 10 rw "GR Coefficient Encoded signed value (from -512 to 511).";
1422        _ 1 mbz;
1423        gg 10 rw "GG Coefficient Encoded signed value (from -512 to 511).";
1424        _ 1 mbz;
1425        gb 10 rw "GB Coefficient Encoded signed value (from -512 to 511).";
1426    };
1427    
1428    register dispc_cpr1_coef_b addr(base, 0x228) "The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
1429        br 10 rw "BR Coefficient Encoded signed value (from -512 to 511).";
1430        _ 1 mbz;
1431        bg 10 rw "BG Coefficient Encoded signed value (from -512 to 511).";
1432        _ 1 mbz;
1433        bb 10 rw "BB Coefficient Encoded signed value (from -512 to 511).";
1434    };
1435    
1436    register dispc_gfx_preload addr(base, 0x22C) "The register configures the graphics DMA buffer Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1437        _ 20 mbz;
1438        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
1439    };
1440    
1441    register dispc_vid1_preload addr(base, 0x230) "The register configures the DMA buffer of the video 1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1442        _ 20 mbz;
1443        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
1444    };
1445    
1446    register dispc_vid2_preload addr(base, 0x234) "The register configures the DMA buffer of the video 2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1447        _ 20 mbz;
1448        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
1449    };
1450
1451    constants stallmode_status1 width(1) "" {
1452        STALLMODE_0_1 = 0 "Normal mode selected";
1453        STALLMODE_1_1 = 1 "STALL mode selected. The Display Controller sends the data without considering the VSYNC/HSYNC. The LCD output is disabled at the end of the transfer of the frame. The S/W has to re-enable the LCD output in order to generate a new frame.";
1454    };
1455
1456    constants stntft_status1 width(1) "" {
1457        STNTFT_0_1 = 0 "Passive Matrix display operation enabled. Passive Matrix dither logic is enabled.";
1458        STNTFT_1_1 = 1 "Active or TFT display operation enabled. STN Dither logic and output FIFO bypassed.";
1459    };
1460    
1461    register dispc_control2 addr(base, 0x238) "The control register configures the Display Controller module for the secondary LCD output. Shadow registers are updated during the VFP start period of the secondary LCD, EVSYNC, or when.GOWB is set to 1 by software and the current WB frame is complete (that is, has no more data in the write-back pipeline)." {
1462        spatialtemporal_ditheringframes 2 rw type(spatialtemporal_ditheringframes_status) "Spatial/Temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD output";
1463        _ 3 mbz;
1464        tdmunused_bits 2 rw type(tdmunusedbits_status) "State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output";
1465        tdmcycle_format 2 rw type(tdmcycleformat_status) "Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output";
1466        tdmparallel_mode 2 rw type(tdmparallelmode_status) "Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output";
1467        tdmenable 1 rw type(tdmenable_status) "Enable the multiple cycle format (TDM mode only used for Active Matrix mode with the RFBI enable bit off) for the secondary LCD output wr: VFP start period of secondary LCD output";
1468        _ 6 mbz;
1469        tvoverlay_optimization 1 rw type(tdmparallelmode_status) "Overlay Optimization for the TV output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory";
1470        overlay_optimization 1 rw type(tdmparallelmode_status) "Overlay Optimization for the secondary LCD output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory";
1471        stallmode 1 rw type(stallmode_status1) "STALL Mode for the secondary LCD output wr: VFP start period of secondary LCD output";
1472        _ 1 mbz;
1473        tftdatalines 2 rw type(tftdatalines_status) "Number of lines of the secondary LCD interface wr: VFP start period of secondary LCD output";
1474        stdither_enable 1 rw type(tdmparallelmode_status) "Spatial Temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD output";
1475        gowb 1 rw type(tdmparallelmode_status) "GO Command for the write-back output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the write-back output to the memory. wr:immediate";
1476        golcd 1 rw type(golcd_status) "GO Command for the secondary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the secondary LCD output. wr:immediate";
1477        m8b 1 rw type(tdmparallelmode_status) "Mono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD output";
1478        stntft 1 rw type(stntft_status1) "LCD Display type of the secondary LCD wr: VFP start period of secondary LCD output";
1479        monocolor 1 rw type(tdmparallelmode_status) "Monochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD output";
1480        _ 1 mbz;
1481        lcdenable 1 rw type(lcdenable_status) "Enable the secondary LCD output wr:immediate";
1482    };
1483    
1484    register dispc_vid3_accu_j_0 addr(base, 0x300) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1485        _ 5 mbz;
1486        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
1487        _ 5 mbz;
1488        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
1489    };
1490    
1491    register dispc_vid3_accu_j_1 addr(base, 0x304) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1492        _ 5 mbz;
1493        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
1494        _ 5 mbz;
1495        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
1496    };
1497    
1498    register dispc_vid3_ba_j_0 rw addr(base, 0x308) "The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
1499    
1500    register dispc_vid3_ba_j_1 rw addr(base, 0x30C) "The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
1501    
1502    register dispc_vid3_fir_coef_h_i_0 addr(base, 0x310) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1503        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1504        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1505        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1506        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1507    };
1508    
1509    register dispc_vid3_fir_coef_h_i_1 addr(base, 0x318) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1510        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1511        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1512        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1513        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1514    };
1515    
1516    register dispc_vid3_fir_coef_h_i_2 addr(base, 0x320) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1517        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1518        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1519        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1520        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1521    };
1522    
1523    register dispc_vid3_fir_coef_h_i_3 addr(base, 0x328) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1524        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1525        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1526        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1527        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1528    };
1529    
1530    register dispc_vid3_fir_coef_h_i_4 addr(base, 0x330) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1531        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1532        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1533        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1534        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1535    };
1536    
1537    register dispc_vid3_fir_coef_h_i_5 addr(base, 0x338) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1538        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1539        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1540        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1541        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1542    };
1543    
1544    register dispc_vid3_fir_coef_h_i_6 addr(base, 0x340) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1545        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1546        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1547        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1548        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1549    };
1550    
1551    register dispc_vid3_fir_coef_h_i_7 addr(base, 0x348) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1552        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1553        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1554        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1555        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1556    };
1557    
1558    register dispc_vid3_fir_coef_hv_i_0 addr(base, 0x314) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1559        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1560        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1561        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1562        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1563    };
1564    
1565    register dispc_vid3_fir_coef_hv_i_1 addr(base, 0x31C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1566        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1567        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1568        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1569        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1570    };
1571    
1572    register dispc_vid3_fir_coef_hv_i_2 addr(base, 0x324) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1573        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1574        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1575        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1576        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1577    };
1578    
1579    register dispc_vid3_fir_coef_hv_i_3 addr(base, 0x32C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1580        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1581        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1582        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1583        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1584    };
1585    
1586    register dispc_vid3_fir_coef_hv_i_4 addr(base, 0x334) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1587        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1588        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1589        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1590        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1591    };
1592    
1593    register dispc_vid3_fir_coef_hv_i_5 addr(base, 0x33C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1594        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1595        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1596        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1597        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1598    };
1599    
1600    register dispc_vid3_fir_coef_hv_i_6 addr(base, 0x344) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1601        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1602        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1603        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1604        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1605    };
1606    
1607    register dispc_vid3_fir_coef_hv_i_7 addr(base, 0x34C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1608        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1609        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1610        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1611        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1612    };
1613    
1614    register dispc_vid3_fir_coef_v_i_0 addr(base, 0x350) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1615        _ 16 mbz;
1616        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1617        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1618    };
1619    
1620    register dispc_vid3_fir_coef_v_i_1 addr(base, 0x354) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1621        _ 16 mbz;
1622        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1623        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1624    };
1625    
1626    register dispc_vid3_fir_coef_v_i_2 addr(base, 0x358) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1627        _ 16 mbz;
1628        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1629        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1630    };
1631    
1632    register dispc_vid3_fir_coef_v_i_3 addr(base, 0x35C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1633        _ 16 mbz;
1634        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1635        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1636    };
1637    
1638    register dispc_vid3_fir_coef_v_i_4 addr(base, 0x360) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1639        _ 16 mbz;
1640        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1641        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1642    };
1643    
1644    register dispc_vid3_fir_coef_v_i_5 addr(base, 0x364) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1645        _ 16 mbz;
1646        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1647        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1648    };
1649    
1650    register dispc_vid3_fir_coef_v_i_6 addr(base, 0x368) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1651        _ 16 mbz;
1652        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1653        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1654    };
1655    
1656    register dispc_vid3_fir_coef_v_i_7 addr(base, 0x36C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1657        _ 16 mbz;
1658        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
1659        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
1660    };
1661
1662    constants format_status2 width(4) "" {
1663        FORMAT_6_3 = 6 "RGB16-565";
1664        FORMAT_1_3 = 1 "RGB12x-4444";
1665        FORMAT_10_3 = 10 "YUV2 4:2:2 co-sited";
1666        FORMAT_7_3 = 7 "ARGB16-1555";
1667        FORMAT_13_3 = 13 "RGBA32-8888";
1668        FORMAT_0_3 = 0 "NV12 4:2:0 2 buffers (Y + UV)";
1669        FORMAT_2_3 = 2 "RGBA12-4444";
1670        FORMAT_8_3 = 8 "RGB24-8888 (32-bit container)";
1671        FORMAT_9_3 = 9 "RGB24-888 (24-bit container)";
1672        FORMAT_11_3 = 11 "UYVY 4:2:2 co-sited";
1673        FORMAT_5_3 = 5 "ARGB16-4444";
1674        FORMAT_15_3 = 15 "xRGB15-1555";
1675        FORMAT_12_3 = 12 "ARGB32-8888";
1676        FORMAT_4_3 = 4 "xRGB12-4444";
1677        FORMAT_14_3 = 14 "RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)";
1678    };
1679    
1680    register dispc_vid3_attributes addr(base, 0x370) "The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1681        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate";
1682        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
1683        premultiplyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
1684        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
1685        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
1686        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the video window from its own DMA buffer only.";
1687        arbitration 1 rw type(tdmparallelmode_status) "Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
1688        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
1689        verticaltaps 1 rw type(tdmparallelmode_status) "Video Vertical Resize Tap Number";
1690        dmaoptimization 1 ro "Write 0s for future compatibility. Reads return 0.";
1691        bufpreload 1 rw type(tdmparallelmode_status) "Video Preload Value";
1692        _ 1 mbz;
1693        selfrefreshauto 1 rw type(selfrefreshauto_status) "Automatic self-refresh mode";
1694        channelout 1 rw type(channelout_status) "Video Channel Out configuration: LCD, WB or TV. wr: immediate";
1695        burstsize 2 rw type(burstsize_status) "Video DMA Burst Size";
1696        rotation 2 rw type(rotation_status) "Video Rotation Flag";
1697        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
1698        replicationenable 1 rw type(replicationenable_status1) "Replication Enable";
1699        colorconvenable 1 rw type(colorconvenable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
1700        vresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
1701        hresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
1702        resizeenable 2 rw type(resizeenable_status) "Video Resize Enable";
1703        format 4 rw type(format_status2) "Video Format. It defines the pixel format when fetching the video 3 picture into memory.";
1704        enable 1 rw type(tdmparallelmode_status) "Video Enable";
1705    };
1706    
1707    register dispc_vid3_conv_coef0 addr(base, 0x374) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1708        _ 5 mbz;
1709        rcr 11 rw "RCr Coefficient Encoded signed value (from -1024 to 1023).";
1710        _ 5 mbz;
1711        ry 11 rw "RY Coefficient Encoded signed value (from -1024 to 1023).";
1712    };
1713    
1714    register dispc_vid3_conv_coef1 addr(base, 0x378) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1715        _ 5 mbz;
1716        gy 11 rw "GY Coefficient Encoded signed value (from -1024 to 1023).";
1717        _ 5 mbz;
1718        rcb 11 rw "RCb Coefficient Encoded signed value (from -1024 to 1023).";
1719    };
1720    
1721    register dispc_vid3_conv_coef2 addr(base, 0x37C) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1722        _ 5 mbz;
1723        gcb 11 rw "GCb Coefficient Encoded signed value (from -1024 to 1023).";
1724        _ 5 mbz;
1725        gcr 11 rw "GCr Coefficient Encoded signed value (from -1024 to 1023).";
1726    };
1727    
1728    register dispc_vid3_conv_coef3 addr(base, 0x380) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1729        _ 5 mbz;
1730        bcr 11 rw "BCr coefficient Encoded signed value (from -1024 to 1023).";
1731        _ 5 mbz;
1732        by 11 rw "BY coefficient Encoded signed value (from -1024 to 1023).";
1733    };
1734    
1735    register dispc_vid3_conv_coef4 addr(base, 0x384) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1736        _ 21 mbz;
1737        bcb 11 rw "BCb Coefficient Encoded signed value (from -1024 to 1023).";
1738    };
1739    
1740    register dispc_vid3_buf_size_status addr(base, 0x388) "The register defines the DMA buffer size for the video pipeline 3." {
1741        _ 16 mbz;
1742        bufsize 16 ro "DMA buffer Size in number of 128-bits.";
1743    };
1744    
1745    register dispc_vid3_buf_threshold addr(base, 0x38C) "The register configures the DMA buffer associated with the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1746        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
1747        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
1748    };
1749    
1750    register dispc_vid3_fir addr(base, 0x390) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1751        _ 3 mbz;
1752        firvinc 13 rw "Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
1753        _ 3 mbz;
1754        firhinc 13 rw "Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
1755    };
1756    
1757    register dispc_vid3_picture_size addr(base, 0x394) "The register configures the size of the video picture associated with the video layer 3 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1758        _ 5 mbz;
1759        orgsizey 11 rw "Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
1760        _ 5 mbz;
1761        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
1762    };
1763    
1764    register dispc_vid3_pixel_inc addr(base, 0x398) "The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3. For more information, see, Predecimation. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1765        _ 24 mbz;
1766        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. For YUV4:2:0, Max supported value is 128.";
1767    };
1768    
1769    register dispc_vid3_position addr(base, 0x39C) "The register configures the position of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1770        _ 5 mbz;
1771        posy 11 rw "Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0.";
1772        _ 5 mbz;
1773        posx 11 rw "X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0.";
1774    };
1775    
1776    register dispc_vid3_preload addr(base, 0x3A0) "The register configures the DMA buffer of the video 3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1777        _ 20 mbz;
1778        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
1779    };
1780    
1781    register dispc_vid3_row_inc rw addr(base, 0x3A4) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
1782    
1783    register dispc_vid3_size addr(base, 0x3A8) "The register configures the size of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
1784        _ 5 mbz;
1785        sizey 11 rw "Number of lines of the video 3 Encoded value (from 1 to 2048) to specify the number of lines of the video window 3. Program to value minus 1.";
1786        _ 5 mbz;
1787        sizex 11 rw "Number of pixels of the video window 3 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 3. Program to value minus 1.";
1788    };
1789    
1790    register dispc_default_color2 addr(base, 0x3AC) "The control register allows to configure the default solid background color for the secondary LCD Shadow register, updated on VFP start period of secondary LCD" {
1791        _ 8 mbz;
1792        defaultcolor 24 rw "24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.";
1793    };
1794    
1795    register dispc_trans_color2 addr(base, 0x3B0) "The register sets the transparency color value for the video/graphics overlays for the secondary LCD output. Shadow register, updated on VFP start period of the secondary LCD" {
1796        _ 8 mbz;
1797        transcolorkey 24 rw "Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24";
1798    };
1799    
1800    register dispc_cpr2_coef_b addr(base, 0x3B4) "The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
1801        br 10 rw "BR Coefficient Encoded signed value (from -512 to 511).";
1802        _ 1 mbz;
1803        bg 10 rw "BG Coefficient Encoded signed value (from -512 to 511).";
1804        _ 1 mbz;
1805        bb 10 rw "BB Coefficient Encoded signed value (from -512 to 511).";
1806    };
1807    
1808    register dispc_cpr2_coef_g addr(base, 0x3B8) "The register configures the color phase rotation matrix coefficients for the Green component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
1809        gr 10 rw "GR Coefficient Encoded signed value (from -512 to 511).";
1810        _ 1 mbz;
1811        gg 10 rw "GG Coefficient Encoded signed value (from -512 to 511).";
1812        _ 1 mbz;
1813        gb 10 rw "GB Coefficient Encoded signed value (from -512 to 511).";
1814    };
1815    
1816    register dispc_cpr2_coef_r addr(base, 0x3BC) "The register configures the color phase rotation matrix coefficients for the Red component. Shadow register, updated on VFP start period of secondary LCD" {
1817        rr 10 rw "RR Coefficient Encoded signed value (from -512 to 511).";
1818        _ 1 mbz;
1819        rg 10 rw "RG Coefficient Encoded signed value (from -512 to 511).";
1820        _ 1 mbz;
1821        rb 10 rw "RB Coefficient Encoded signed value (from -512 to 511).";
1822    };
1823    
1824    register dispc_data2_cycle1 addr(base, 0x3C0) "The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of secondary LCD" {
1825        _ 4 mbz;
1826        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
1827        _ 3 mbz;
1828        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1829        _ 4 mbz;
1830        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
1831        _ 3 mbz;
1832        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1833    };
1834    
1835    register dispc_data2_cycle2 addr(base, 0x3C4) "The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of secondary LCD" {
1836        _ 4 mbz;
1837        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
1838        _ 3 mbz;
1839        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1840        _ 4 mbz;
1841        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
1842        _ 3 mbz;
1843        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1844    };
1845    
1846    register dispc_data2_cycle3 addr(base, 0x3C8) "The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of secondary LCD" {
1847        _ 4 mbz;
1848        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
1849        _ 3 mbz;
1850        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1851        _ 4 mbz;
1852        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
1853        _ 3 mbz;
1854        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
1855    };
1856
1857    constants delta_lpp_status2 width(2) "" {
1858        DELTA_LPP_0_2 = 0 "same size";
1859        DELTA_LPP_1_2 = 1 "odd size = even size +1";
1860        DELTA_LPP_2_2 = 2 "Odd size = even size -1";
1861    };
1862    
1863    register dispc_size_lcd2 addr(base, 0x3CC) "The register configures the panel size (horizontal and vertical). It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." {
1864        _ 5 mbz;
1865        lpp 11 rw "Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1).";
1866        delta_lpp 2 rw type(delta_lpp_status2) "Indicates the delta size value of the odd field compared to the even field";
1867        _ 3 mbz;
1868        ppl 11 rw "Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid.";
1869    };
1870    
1871    register dispc_timing_h2 addr(base, 0x400) "The register configures the timing logic for the HSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
1872        hbp 12 rw "Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1).";
1873        hfp 12 rw "Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1).";
1874        hsw 8 rw "Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1).";
1875    };
1876    
1877    register dispc_timing_v2 addr(base, 0x404) "The register configures the timing logic for the VSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
1878        vbp 12 rw "Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display.";
1879        vfp 12 rw "Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame.";
1880        vsw 8 rw "Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode. In passive mode, encoded value (from 1 to 256) to specify the number of extra line clock periods (program to value minus 1) to insert after the vertical front porch (VFP) period has elapsed.";
1881    };
1882    
1883    register dispc_pol_freq2 addr(base, 0x408) "The register configures the signal configuration. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
1884        _ 13 mbz;
1885        align 1 rw type(align_status) "Defines the alignment between HSYNC and VSYNC assertion.";
1886        onoff 1 rw type(onoff_status) "HSYNC/VSYNC Pixel clock Control On/Off";
1887        rf 1 rw type(onoff_status) "Program HSYNC/VSYNC Rise or Fall";
1888        ieo 1 rw type(tdmparallelmode_status) "Invert output enable";
1889        ipc 1 rw type(frame_done2_en_status) "Invert pixel clock";
1890        ihs 1 rw type(tdmparallelmode_status) "Invert HSYNC";
1891        ivs 1 rw type(tdmparallelmode_status) "Invert VSYNC";
1892        acbi 4 rw "AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions";
1893        acb 8 rw "AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display.";
1894    };
1895    
1896    register dispc_divisor2 addr(base, 0x40C) "The register configures the divisors. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
1897        _ 8 mbz;
1898        lcd 8 rw "Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK. The value 0 is invalid.";
1899        _ 8 mbz;
1900        pcd 8 rw "Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided byDISPC_DIVISOR2.LCD value. The values 0 is invalid.";
1901    };
1902    
1903    register dispc_wb_accu_j_0 addr(base, 0x500) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1904        _ 5 mbz;
1905        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
1906        _ 5 mbz;
1907        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
1908    };
1909    
1910    register dispc_wb_accu_j_1 addr(base, 0x504) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1911        _ 5 mbz;
1912        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
1913        _ 5 mbz;
1914        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
1915    };
1916    
1917    register dispc_wb_ba_j_0 rw addr(base, 0x508) "The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" type(uint32);
1918    
1919    register dispc_wb_ba_j_1 rw addr(base, 0x50C) "The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" type(uint32);
1920    
1921    register dispc_wb_fir_coef_h_i_0 addr(base, 0x510) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1922        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1923        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1924        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1925        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1926    };
1927    
1928    register dispc_wb_fir_coef_h_i_1 addr(base, 0x518) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1929        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1930        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1931        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1932        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1933    };
1934    
1935    register dispc_wb_fir_coef_h_i_2 addr(base, 0x520) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1936        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1937        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1938        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1939        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1940    };
1941    
1942    register dispc_wb_fir_coef_h_i_3 addr(base, 0x528) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1943        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1944        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1945        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1946        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1947    };
1948    
1949    register dispc_wb_fir_coef_h_i_4 addr(base, 0x530) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1950        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1951        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1952        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1953        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1954    };
1955    
1956    register dispc_wb_fir_coef_h_i_5 addr(base, 0x538) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1957        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1958        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1959        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1960        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1961    };
1962    
1963    register dispc_wb_fir_coef_h_i_6 addr(base, 0x540) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1964        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1965        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1966        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1967        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1968    };
1969    
1970    register dispc_wb_fir_coef_h_i_7 addr(base, 0x548) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1971        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
1972        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
1973        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
1974        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
1975    };
1976    
1977    register dispc_wb_fir_coef_hv_i_0 addr(base, 0x514) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1978        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1979        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1980        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1981        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1982    };
1983    
1984    register dispc_wb_fir_coef_hv_i_1 addr(base, 0x51C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1985        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1986        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1987        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1988        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1989    };
1990    
1991    register dispc_wb_fir_coef_hv_i_2 addr(base, 0x524) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1992        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
1993        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
1994        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
1995        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
1996    };
1997    
1998    register dispc_wb_fir_coef_hv_i_3 addr(base, 0x52C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
1999        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2000        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2001        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2002        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2003    };
2004    
2005    register dispc_wb_fir_coef_hv_i_4 addr(base, 0x534) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2006        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2007        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2008        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2009        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2010    };
2011    
2012    register dispc_wb_fir_coef_hv_i_5 addr(base, 0x53C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2013        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2014        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2015        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2016        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2017    };
2018    
2019    register dispc_wb_fir_coef_hv_i_6 addr(base, 0x544) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2020        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2021        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2022        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2023        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2024    };
2025    
2026    register dispc_wb_fir_coef_hv_i_7 addr(base, 0x54C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2027        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2028        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2029        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2030        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2031    };
2032    
2033    register dispc_wb_fir_coef_v_i_0 addr(base, 0x550) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2034        _ 16 mbz;
2035        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2036        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2037    };
2038    
2039    register dispc_wb_fir_coef_v_i_1 addr(base, 0x554) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2040        _ 16 mbz;
2041        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2042        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2043    };
2044    
2045    register dispc_wb_fir_coef_v_i_2 addr(base, 0x558) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2046        _ 16 mbz;
2047        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2048        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2049    };
2050    
2051    register dispc_wb_fir_coef_v_i_3 addr(base, 0x55C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2052        _ 16 mbz;
2053        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2054        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2055    };
2056    
2057    register dispc_wb_fir_coef_v_i_4 addr(base, 0x560) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2058        _ 16 mbz;
2059        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2060        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2061    };
2062    
2063    register dispc_wb_fir_coef_v_i_5 addr(base, 0x564) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2064        _ 16 mbz;
2065        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2066        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2067    };
2068    
2069    register dispc_wb_fir_coef_v_i_6 addr(base, 0x568) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2070        _ 16 mbz;
2071        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2072        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2073    };
2074    
2075    register dispc_wb_fir_coef_v_i_7 addr(base, 0x56C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2076        _ 16 mbz;
2077        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2078        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2079    };
2080
2081    constants idlesize_status width(1) "" {
2082        IDLESIZE_0 = 0 "The number of idles between requests is defined by IDLENUMBER as number of cycles.";
2083        IDLESIZE_1 = 1 "The number of idles between requests is defined by IDLENUMBER multiplied by burst size as number of cycles.";
2084    };
2085
2086    constants capturemode_status width(3) "" {
2087        CAPTUREMODE_6 = 6 "Only one out of six frames is captured. The first one is captured then the second one is skipped and so on.";
2088        CAPTUREMODE_1 = 1 "Only one frame is captured.";
2089        CAPTUREMODE_7 = 7 "Only one out of seven frames is captured. The first one is captured then the second one is skipped and so on.";
2090        CAPTUREMODE_0 = 0 "All frames are captures until the write-back channel is disabled or there is no more data generated by the overlay or the pipeline attached to the write-back channel.";
2091        CAPTUREMODE_2 = 2 "Only one out of two frames is captured. The first one is captured then the second one is skipped and so on.";
2092        CAPTUREMODE_4 = 4 "Only one out of four frames is captured. The first one is captured then the second one is skipped and so on.";
2093        CAPTUREMODE_5 = 5 "Only one out of five frames is captured. The first one is captured then the second one is skipped and so on.";
2094        CAPTUREMODE_3 = 3 "Only one out of three frames is captured. The first one is captured then the second one is skipped and so on.";
2095    };
2096
2097    constants channelin_status width(3) "" {
2098        CHANNELIN_6 = 6 "Video3 pipeline output";
2099        CHANNELIN_1 = 1 "Secondary LCD output";
2100        CHANNELIN_0 = 0 "Primary LCD overlay output";
2101        CHANNELIN_2 = 2 "TV overlay output";
2102        CHANNELIN_4 = 4 "Video1 pipeline output";
2103        CHANNELIN_5 = 5 "Video2 pipeline output";
2104        CHANNELIN_3 = 3 "Graphics pipeline output";
2105    };
2106
2107    constants truncationenable_status width(1) "" {
2108        TRUNCATIONENABLE_0 = 0 "Disable truncation logic";
2109        TRUNCATIONENABLE_1 = 1 "Enable truncation logic from ARGB32 to the pixel format defined in the field FORMAT.";
2110    };
2111
2112    constants resizeenable_status1 width(2) "" {
2113        RESIZEENABLE_0_3 = 0 "Disable the resize processing";
2114        RESIZEENABLE_1_3 = 1 "Enable the horizontal resize processing";
2115        RESIZEENABLE_3_3 = 3 "Enable both horizontal and vertical resize processing";
2116        RESIZEENABLE_2_3 = 2 "Enable the vertical resize processing";
2117    };
2118
2119    constants enable_status width(1) "" {
2120        ENABLE_0_4 = 0 "Write-back disabled";
2121        ENABLE_1_4 = 1 "Write-back enabled";
2122    };
2123    
2124    register dispc_wb_attributes addr(base, 0x570) "The register configures the attributes of the viwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2125        idlenumber 4 rw "Determines the number of idles between requests on the L3 interconnect. It is only used when the write-back pipeline does data transfer from memory to memory. When the output of an overlay is stored in memory through the write-back pipeline in capture mode, the bit field IDLENUMBER is ignored since a timing generator is used to time the transfer. The number of IDLE cycles is IDLENUMBER (from 0 to 15) if IDLESIZE=0. The number of IDLE cycles is IDLENUMBERx8 (from 0 to 120) if IDLESIZE=1 and BURSTSIZE=2. The number of IDLE cycles is IDLENUMBERx4 (from 0 to 60) if IDLESIZE=1 and BURSTSIZE=1. The number of IDLE cycles is IDLENUMBERx2 (from 0 to 30) if IDLESIZE=1 and BURSTSIZE=0.";
2126        idlesize 1 rw type(idlesize_status) "Determines if the IDLENUMBER corresponds to a number of bursts or singles.";
2127        capturemode 3 rw type(capturemode_status) "Defines the frame rate capture.";
2128        arbitration 1 rw type(tdmparallelmode_status) "Determines the priority of the write-back pipeline. The write-back pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
2129        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
2130        verticaltaps 1 rw type(tdmparallelmode_status) "Video Vertical Resize Tap Number";
2131        _ 1 mbz;
2132        writebackmode 1 rw "When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel. 0x0: Capture mode (default mode) 0x1: Memory-to-memory mode";
2133        channelin 3 rw type(channelin_status) "Video Channel In configuration wr: immediate";
2134        burstsize 2 rw type(burstsize_status) "Write-back DMA Burst Size";
2135        _ 2 mbz;
2136        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
2137        truncationenable 1 rw type(truncationenable_status) "It applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32. If the format is one of the YUV supported formats, the bit field is ignored.";
2138        colorconvenable 1 rw type(colorconv_enable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
2139        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
2140        alphaenable 1 rw "Premultiplied alpha enable Read 0x1: Enabled Read 0x0: Disabled. This bit also disable the logic present in the associated channel out that compute the alpha component sent to the WB pipe. When the WB is configured to copy back one of the output channels (output of overlay), the following configurations are available: 0x1: The WB pipe copies back to memory the premultiplied alpha calculated through the overlay. 0x0: The alpha value is not written back.";
2141        resizeenable 2 rw type(resizeenable_status1) "Resize Enable";
2142        format 4 rw type(format_status1) "Write-back Format. It defines the pixel format when storing the write-back picture into memory.";
2143        enable 1 rw type(enable_status) "Write-back Enable. wr: immediate";
2144    };
2145    
2146    register dispc_wb_conv_coef0 addr(base, 0x574) "The register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24) Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2147        _ 5 mbz;
2148        yg 11 rw "YG Coefficient Encoded signed value (from -1024 to 1023).";
2149        _ 5 mbz;
2150        yr 11 rw "YR Coefficient Encoded signed value (from -1024 to 1023).";
2151    };
2152    
2153    register dispc_wb_conv_coef1 addr(base, 0x578) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2154        _ 5 mbz;
2155        crr 11 rw "CrR Coefficient Encoded signed value (from -1024 to 1023).";
2156        _ 5 mbz;
2157        yb 11 rw "YB Coefficient Encoded signed value (from -1024 to 1023).";
2158    };
2159    
2160    register dispc_wb_conv_coef2 addr(base, 0x57C) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2161        _ 5 mbz;
2162        crb 11 rw "CrB Coefficient Encoded signed value (from -1024 to 1023).";
2163        _ 5 mbz;
2164        crg 11 rw "CrG Coefficient Encoded signed value (from -1024 to 1023).";
2165    };
2166    
2167    register dispc_wb_conv_coef3 addr(base, 0x580) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2168        _ 5 mbz;
2169        cbg 11 rw "CbG coefficient Encoded signed value (from -1024 to 1023).";
2170        _ 5 mbz;
2171        cbr 11 rw "CbR coefficient Encoded signed value (from -1024 to 1023).";
2172    };
2173    
2174    register dispc_wb_conv_coef4 addr(base, 0x584) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2175        _ 21 mbz;
2176        cbb 11 rw "CbB Coefficient Encoded signed value (from -1024 to 1023).";
2177    };
2178    
2179    register dispc_wb_buf_size_status addr(base, 0x588) "The register defines the DMA buffer size for the write back pipeline." {
2180        _ 16 mbz;
2181        bufsize 16 ro "DMA buffer Size in number of 128-bits.";
2182    };
2183    
2184    register dispc_wb_buf_threshold addr(base, 0x58C) "The register configures the DMA buffer associated with the write-back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2185        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
2186        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
2187    };
2188    
2189    register dispc_wb_fir addr(base, 0x590) "The register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2190        _ 3 mbz;
2191        firvinc 13 rw "Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2192        _ 3 mbz;
2193        firhinc 13 rw "Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2194    };
2195    
2196    register dispc_wb_picture_size addr(base, 0x594) "The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2197        _ 5 mbz;
2198        orgsizey 11 rw "Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1).";
2199        _ 5 mbz;
2200        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit.";
2201    };
2202    
2203    register dispc_wb_pixel_inc addr(base, 0x598) "The register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2204        _ 24 mbz;
2205        pixelinc 8 rw "Values other than 1 are invalid";
2206    };
2207    
2208    register dispc_wb_row_inc rw addr(base, 0x5A4) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" type(uint32);
2209    
2210    register dispc_wb_size addr(base, 0x5A8) "The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline. When the overlay is output on the primary LCD or secondary LCD or TV outputs, the size of the frame is defined in the, , and respectively. Shadow register, updated when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2211        _ 5 mbz;
2212        sizey 11 rw "Number of lines of the Write-back picture Encoded value (from 1 to 2048) to specify the number of lines of the write-back picture. Program to value minus 1.";
2213        _ 5 mbz;
2214        sizex 11 rw "Number of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture. Program to value minus 1.";
2215    };
2216    
2217    register dispc_vid1_ba_uv_j_0 rw addr(base, 0x600) "The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2218    
2219    register dispc_vid1_ba_uv_j_1 rw addr(base, 0x604) "The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2220    
2221    register dispc_vid2_ba_uv_j_0 rw addr(base, 0x608) "The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2222    
2223    register dispc_vid2_ba_uv_j_1 rw addr(base, 0x60C) "The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2224    
2225    register dispc_vid3_ba_uv_j_0 rw addr(base, 0x610) "The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2226    
2227    register dispc_vid3_ba_uv_j_1 rw addr(base, 0x614) "The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2228    
2229    register dispc_wb_ba_uv_j_0 rw addr(base, 0x618) "The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2230    
2231    register dispc_wb_ba_uv_j_1 rw addr(base, 0x61C) "The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
2232
2233    constants bufferhand_check_status1 width(1) "" {
2234        BUFFERHAND_CHECK_0_1 = 0 "Only the STALL signal (generated by RFBI or DSI2 depending on which IP uses the LCD output) is used regardless of the DMA buffer fullness information in order to provide data to the RFBI or DS2 module.";
2235        BUFFERHAND_CHECK_1_1 = 1 "The STALL signal (generated by RFBI or DSI2 depending on which IP uses the LCD output) is used in combination with the DMA buffer fullness information in order to provide data to the RFBI or DSI2 module only when it does not generated buffer underflow.";
2236    };
2237    
2238    register dispc_config2 addr(base, 0x620) "The control register configures the Display Controller module for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD or EVSYNC" {
2239        _ 6 mbz;
2240        fullrange 1 rw type(fullrange_status) "Color Space Conversion full range setting.";
2241        colorconv_enable 1 rw type(colorconv_enable_status) "Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1.";
2242        fidfirst 1 rw type(fidfirst_status) "Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used.";
2243        outputmode_enable 1 rw type(outputmode_enable_status) "Selects between progressive and interlace mode for the secondary LCD output.";
2244        _ 5 mbz;
2245        bufferhand_check 1 rw type(bufferhand_check_status1) "Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (secondary LCD output)";
2246        cpr 1 rw type(cpr_status) "Color Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD output";
2247        _ 3 mbz;
2248        tcklcd_selection 1 rw type(tcktv_selection_status) "Transparency Color Key Selection (secondary LCD output) wr: VFP start period of secondary LCD output";
2249        tcklcdenable 1 rw type(frame_done2_en_status) "Transparency Color Key Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
2250        _ 1 mbz;
2251        acbiasgated 1 rw type(acbiasgated_status) "ACBias Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
2252        vsyncgated 1 rw type(vsyncgated_status) "VSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
2253        hsyncgated 1 rw type(hsyncgated_status) "HSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
2254        pixelclock_gated 1 rw type(pixelclock_gated_status) "Pixel Clock Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
2255        pixeldata_gated 1 rw type(pixeldatagated_status) "Pixel Data Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
2256        _ 3 mbz;
2257        pixelgated 1 rw type(tdmparallelmode_status) "Pixel Gated Enable (only for Active Matrix) (secondary LCD output) wr: VFP start period of secondary LCD output";
2258    };
2259
2260    constants yuvchromare_sampling_status width(1) "" {
2261        YUVCHROMARE_SAMPLING_0 = 0 "When input is 4:2:2, the missing chrominance samples are calculated by averaging the adjacent samples if. ROTATION=0 only. Other rotation configurations are not supported.";
2262        YUVCHROMARE_SAMPLING_1 = 1 "For 4:2:2 (or 4:2:0), the missing chrominance samples are calculated by filtering the adjacent samples (5-tap polyphase filter). See, Configuration 2: Video Pipeline. All rotation configurations are supported.";
2263    };
2264
2265    constants vc1enable_status width(1) "" {
2266        VC1ENABLE_0 = 0 "VC-1 range mapping disabled";
2267        VC1ENABLE_1 = 1 "VC-1 range mapping enabled";
2268    };
2269    
2270    register dispc_vid1_attributes2 addr(base, 0x624) "The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2271        _ 23 mbz;
2272        yuvchromare_sampling 1 rw type(yuvchromare_sampling_status) "The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.";
2273        _ 1 mbz;
2274        vc1_range_cbcr 3 rw "Defines the VC-1 range value for the CbCr component from 0 to 7.";
2275        vc1_range_y 3 rw "Defines the VC-1 range value for the Y component from 0 to 7.";
2276        vc1enable 1 rw type(vc1enable_status) "Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.";
2277    };
2278    
2279    register dispc_vid2_attributes2 addr(base, 0x628) "The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2280        _ 23 mbz;
2281        yuvchromare_sampling 1 rw type(yuvchromare_sampling_status) "The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.";
2282        _ 1 mbz;
2283        vc1_range_cbcr 3 rw "Defines the VC-1 range value for the CbCr component from 0 to 7.";
2284        vc1_range_y 3 rw "Defines the VC-1 range value for the Y component from 0 to 7.";
2285        vc1enable 1 rw type(vc1enable_status) "Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.";
2286    };
2287    
2288    register dispc_vid3_attributes2 addr(base, 0x62C) "The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2289        _ 23 mbz;
2290        yuvchromare_sampling 1 rw type(yuvchromare_sampling_status) "The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.";
2291        _ 1 mbz;
2292        vc1_range_cbcr 3 rw "Defines the VC-1 range value for the CbCr component from 0 to 7.";
2293        vc1_range_y 3 rw "Defines the VC-1 range value for the Y component from 0 to 7.";
2294        vc1enable 1 rw type(vc1enable_status) "Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.";
2295    };
2296    
2297    register dispc_gamma_table0 addr(base, 0x630) "The register configures the look up table used as color look up table for BITMAP formats (1-, 2-, 4, and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output." {
2298        index 8 wo "Defines the location in the table where the bit field VALUE is stored.";
2299        value_r 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
2300        value_g 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
2301        value_b 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
2302    };
2303    
2304    register dispc_gamma_table1 addr(base, 0x634) "The register configures the gamma table on the secondary LCD output." {
2305        index 8 wo "Defines the location in the table where the bit field VALUE is stored.";
2306        value_r 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
2307        value_g 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
2308        value_b 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
2309    };
2310    
2311    register dispc_gamma_table2 addr(base, 0x638) "The register configures the gamma table on the TV output." {
2312        index 1 wo "Setting this bit to 1 resets the internal index counter to zero. Each subsequent access to the register (with the INDEX bit kept at 0) increments the address for the next storage location into the table memory.";
2313        _ 1 mbz;
2314        value_r 10 wo "10-bit color component value to store in the table.";
2315        value_g 10 wo "10-bit color component value to store in the table.";
2316        value_b 10 wo "10-bit color component value to store in the table.";
2317    };
2318    
2319    register dispc_vid1_fir2 addr(base, 0x63C) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2320        _ 3 mbz;
2321        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2322        _ 3 mbz;
2323        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2324    };
2325    
2326    register dispc_vid1_accu2_j_0 addr(base, 0x640) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2327        _ 5 mbz;
2328        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2329        _ 5 mbz;
2330        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2331    };
2332    
2333    register dispc_vid1_accu2_j_1 addr(base, 0x644) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2334        _ 5 mbz;
2335        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2336        _ 5 mbz;
2337        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2338    };
2339    
2340    register dispc_vid1_fir_coef_h2_i_0 addr(base, 0x648) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2341        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2342        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2343        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2344        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2345    };
2346    
2347    register dispc_vid1_fir_coef_h2_i_1 addr(base, 0x650) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2348        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2349        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2350        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2351        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2352    };
2353    
2354    register dispc_vid1_fir_coef_h2_i_2 addr(base, 0x658) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2355        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2356        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2357        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2358        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2359    };
2360    
2361    register dispc_vid1_fir_coef_h2_i_3 addr(base, 0x660) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2362        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2363        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2364        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2365        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2366    };
2367    
2368    register dispc_vid1_fir_coef_h2_i_4 addr(base, 0x668) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2369        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2370        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2371        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2372        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2373    };
2374    
2375    register dispc_vid1_fir_coef_h2_i_5 addr(base, 0x670) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2376        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2377        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2378        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2379        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2380    };
2381    
2382    register dispc_vid1_fir_coef_h2_i_6 addr(base, 0x678) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2383        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2384        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2385        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2386        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2387    };
2388    
2389    register dispc_vid1_fir_coef_h2_i_7 addr(base, 0x680) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2390        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2391        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2392        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2393        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2394    };
2395    
2396    register dispc_vid1_fir_coef_hv2_i_0 addr(base, 0x64C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2397        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2398        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2399        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2400        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2401    };
2402    
2403    register dispc_vid1_fir_coef_hv2_i_1 addr(base, 0x654) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2404        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2405        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2406        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2407        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2408    };
2409    
2410    register dispc_vid1_fir_coef_hv2_i_2 addr(base, 0x65C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2411        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2412        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2413        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2414        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2415    };
2416    
2417    register dispc_vid1_fir_coef_hv2_i_3 addr(base, 0x664) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2418        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2419        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2420        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2421        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2422    };
2423    
2424    register dispc_vid1_fir_coef_hv2_i_4 addr(base, 0x66C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2425        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2426        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2427        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2428        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2429    };
2430    
2431    register dispc_vid1_fir_coef_hv2_i_5 addr(base, 0x674) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2432        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2433        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2434        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2435        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2436    };
2437    
2438    register dispc_vid1_fir_coef_hv2_i_6 addr(base, 0x67C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2439        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2440        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2441        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2442        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2443    };
2444    
2445    register dispc_vid1_fir_coef_hv2_i_7 addr(base, 0x684) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2446        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2447        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2448        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2449        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2450    };
2451    
2452    register dispc_vid1_fir_coef_v2_i_0 addr(base, 0x688) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2453        _ 16 mbz;
2454        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2455        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2456    };
2457    
2458    register dispc_vid1_fir_coef_v2_i_1 addr(base, 0x68C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2459        _ 16 mbz;
2460        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2461        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2462    };
2463    
2464    register dispc_vid1_fir_coef_v2_i_2 addr(base, 0x690) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2465        _ 16 mbz;
2466        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2467        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2468    };
2469    
2470    register dispc_vid1_fir_coef_v2_i_3 addr(base, 0x694) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2471        _ 16 mbz;
2472        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2473        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2474    };
2475    
2476    register dispc_vid1_fir_coef_v2_i_4 addr(base, 0x698) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2477        _ 16 mbz;
2478        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2479        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2480    };
2481    
2482    register dispc_vid1_fir_coef_v2_i_5 addr(base, 0x69C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2483        _ 16 mbz;
2484        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2485        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2486    };
2487    
2488    register dispc_vid1_fir_coef_v2_i_6 addr(base, 0x6A0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2489        _ 16 mbz;
2490        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2491        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2492    };
2493    
2494    register dispc_vid1_fir_coef_v2_i_7 addr(base, 0x6A4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2495        _ 16 mbz;
2496        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2497        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2498    };
2499    
2500    register dispc_vid2_fir2 addr(base, 0x6A8) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2501        _ 3 mbz;
2502        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2503        _ 3 mbz;
2504        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2505    };
2506    
2507    register dispc_vid2_accu2_j_0 addr(base, 0x6AC) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2508        _ 5 mbz;
2509        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2510        _ 5 mbz;
2511        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2512    };
2513    
2514    register dispc_vid2_accu2_j_1 addr(base, 0x6B0) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2515        _ 5 mbz;
2516        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2517        _ 5 mbz;
2518        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2519    };
2520    
2521    register dispc_vid2_fir_coef_h2_i_0 addr(base, 0x6B4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2522        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2523        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2524        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2525        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2526    };
2527    
2528    register dispc_vid2_fir_coef_h2_i_1 addr(base, 0x6BC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2529        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2530        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2531        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2532        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2533    };
2534    
2535    register dispc_vid2_fir_coef_h2_i_2 addr(base, 0x6C4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2536        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2537        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2538        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2539        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2540    };
2541    
2542    register dispc_vid2_fir_coef_h2_i_3 addr(base, 0x6CC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2543        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2544        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2545        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2546        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2547    };
2548    
2549    register dispc_vid2_fir_coef_h2_i_4 addr(base, 0x6D4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2550        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2551        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2552        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2553        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2554    };
2555    
2556    register dispc_vid2_fir_coef_h2_i_5 addr(base, 0x6DC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2557        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2558        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2559        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2560        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2561    };
2562    
2563    register dispc_vid2_fir_coef_h2_i_6 addr(base, 0x6E4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2564        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2565        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2566        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2567        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2568    };
2569    
2570    register dispc_vid2_fir_coef_h2_i_7 addr(base, 0x6EC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2571        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2572        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2573        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2574        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2575    };
2576    
2577    register dispc_vid2_fir_coef_hv2_i_0 addr(base, 0x6B8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2578        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2579        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2580        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2581        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2582    };
2583    
2584    register dispc_vid2_fir_coef_hv2_i_1 addr(base, 0x6C0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2585        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2586        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2587        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2588        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2589    };
2590    
2591    register dispc_vid2_fir_coef_hv2_i_2 addr(base, 0x6C8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2592        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2593        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2594        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2595        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2596    };
2597    
2598    register dispc_vid2_fir_coef_hv2_i_3 addr(base, 0x6D0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2599        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2600        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2601        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2602        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2603    };
2604    
2605    register dispc_vid2_fir_coef_hv2_i_4 addr(base, 0x6D8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2606        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2607        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2608        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2609        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2610    };
2611    
2612    register dispc_vid2_fir_coef_hv2_i_5 addr(base, 0x6E0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2613        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2614        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2615        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2616        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2617    };
2618    
2619    register dispc_vid2_fir_coef_hv2_i_6 addr(base, 0x6E8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2620        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2621        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2622        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2623        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2624    };
2625    
2626    register dispc_vid2_fir_coef_hv2_i_7 addr(base, 0x6F0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2627        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2628        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2629        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2630        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2631    };
2632    
2633    register dispc_vid2_fir_coef_v2_i_0 addr(base, 0x6F4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2634        _ 16 mbz;
2635        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2636        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2637    };
2638    
2639    register dispc_vid2_fir_coef_v2_i_1 addr(base, 0x6F8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2640        _ 16 mbz;
2641        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2642        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2643    };
2644    
2645    register dispc_vid2_fir_coef_v2_i_2 addr(base, 0x6FC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2646        _ 16 mbz;
2647        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2648        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2649    };
2650    
2651    register dispc_vid2_fir_coef_v2_i_3 addr(base, 0x700) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2652        _ 16 mbz;
2653        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2654        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2655    };
2656    
2657    register dispc_vid2_fir_coef_v2_i_4 addr(base, 0x704) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2658        _ 16 mbz;
2659        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2660        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2661    };
2662    
2663    register dispc_vid2_fir_coef_v2_i_5 addr(base, 0x708) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2664        _ 16 mbz;
2665        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2666        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2667    };
2668    
2669    register dispc_vid2_fir_coef_v2_i_6 addr(base, 0x70C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2670        _ 16 mbz;
2671        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2672        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2673    };
2674    
2675    register dispc_vid2_fir_coef_v2_i_7 addr(base, 0x710) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2676        _ 16 mbz;
2677        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2678        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2679    };
2680    
2681    register dispc_vid3_fir2 addr(base, 0x724) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2682        _ 3 mbz;
2683        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2684        _ 3 mbz;
2685        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2686    };
2687    
2688    register dispc_vid3_accu2_j_0 addr(base, 0x728) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2689        _ 5 mbz;
2690        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2691        _ 5 mbz;
2692        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2693    };
2694    
2695    register dispc_vid3_accu2_j_1 addr(base, 0x72C) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2696        _ 5 mbz;
2697        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2698        _ 5 mbz;
2699        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2700    };
2701    
2702    register dispc_vid3_fir_coef_h2_i_0 addr(base, 0x730) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2703        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2704        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2705        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2706        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2707    };
2708    
2709    register dispc_vid3_fir_coef_h2_i_1 addr(base, 0x738) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2710        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2711        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2712        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2713        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2714    };
2715    
2716    register dispc_vid3_fir_coef_h2_i_2 addr(base, 0x740) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2717        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2718        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2719        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2720        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2721    };
2722    
2723    register dispc_vid3_fir_coef_h2_i_3 addr(base, 0x748) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2724        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2725        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2726        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2727        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2728    };
2729    
2730    register dispc_vid3_fir_coef_h2_i_4 addr(base, 0x750) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2731        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2732        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2733        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2734        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2735    };
2736    
2737    register dispc_vid3_fir_coef_h2_i_5 addr(base, 0x758) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2738        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2739        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2740        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2741        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2742    };
2743    
2744    register dispc_vid3_fir_coef_h2_i_6 addr(base, 0x760) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2745        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2746        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2747        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2748        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2749    };
2750    
2751    register dispc_vid3_fir_coef_h2_i_7 addr(base, 0x768) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2752        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2753        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2754        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2755        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2756    };
2757    
2758    register dispc_vid3_fir_coef_hv2_i_0 addr(base, 0x734) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2759        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2760        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2761        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2762        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2763    };
2764    
2765    register dispc_vid3_fir_coef_hv2_i_1 addr(base, 0x73C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2766        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2767        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2768        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2769        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2770    };
2771    
2772    register dispc_vid3_fir_coef_hv2_i_2 addr(base, 0x744) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2773        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2774        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2775        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2776        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2777    };
2778    
2779    register dispc_vid3_fir_coef_hv2_i_3 addr(base, 0x74C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2780        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2781        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2782        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2783        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2784    };
2785    
2786    register dispc_vid3_fir_coef_hv2_i_4 addr(base, 0x754) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2787        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2788        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2789        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2790        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2791    };
2792    
2793    register dispc_vid3_fir_coef_hv2_i_5 addr(base, 0x75C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2794        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2795        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2796        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2797        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2798    };
2799    
2800    register dispc_vid3_fir_coef_hv2_i_6 addr(base, 0x764) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2801        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2802        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2803        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2804        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2805    };
2806    
2807    register dispc_vid3_fir_coef_hv2_i_7 addr(base, 0x76C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2808        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2809        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2810        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2811        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2812    };
2813    
2814    register dispc_vid3_fir_coef_v2_i_0 addr(base, 0x770) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2815        _ 16 mbz;
2816        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2817        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2818    };
2819    
2820    register dispc_vid3_fir_coef_v2_i_1 addr(base, 0x774) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2821        _ 16 mbz;
2822        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2823        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2824    };
2825    
2826    register dispc_vid3_fir_coef_v2_i_2 addr(base, 0x778) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2827        _ 16 mbz;
2828        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2829        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2830    };
2831    
2832    register dispc_vid3_fir_coef_v2_i_3 addr(base, 0x77C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2833        _ 16 mbz;
2834        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2835        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2836    };
2837    
2838    register dispc_vid3_fir_coef_v2_i_4 addr(base, 0x780) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2839        _ 16 mbz;
2840        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2841        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2842    };
2843    
2844    register dispc_vid3_fir_coef_v2_i_5 addr(base, 0x784) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2845        _ 16 mbz;
2846        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2847        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2848    };
2849    
2850    register dispc_vid3_fir_coef_v2_i_6 addr(base, 0x788) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2851        _ 16 mbz;
2852        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2853        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2854    };
2855    
2856    register dispc_vid3_fir_coef_v2_i_7 addr(base, 0x78C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
2857        _ 16 mbz;
2858        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2859        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2860    };
2861    
2862    register dispc_wb_fir2 addr(base, 0x790) "The register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2863        _ 3 mbz;
2864        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2865        _ 3 mbz;
2866        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
2867    };
2868    
2869    register dispc_wb_accu2_j_0 addr(base, 0x794) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2870        _ 5 mbz;
2871        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2872        _ 5 mbz;
2873        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2874    };
2875    
2876    register dispc_wb_accu2_j_1 addr(base, 0x798) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2877        _ 5 mbz;
2878        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
2879        _ 5 mbz;
2880        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
2881    };
2882    
2883    register dispc_wb_fir_coef_h2_i_0 addr(base, 0x7A0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2884        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2885        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2886        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2887        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2888    };
2889    
2890    register dispc_wb_fir_coef_h2_i_1 addr(base, 0x7A8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2891        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2892        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2893        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2894        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2895    };
2896    
2897    register dispc_wb_fir_coef_h2_i_2 addr(base, 0x7B0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2898        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2899        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2900        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2901        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2902    };
2903    
2904    register dispc_wb_fir_coef_h2_i_3 addr(base, 0x7B8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2905        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2906        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2907        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2908        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2909    };
2910    
2911    register dispc_wb_fir_coef_h2_i_4 addr(base, 0x7C0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2912        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2913        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2914        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2915        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2916    };
2917    
2918    register dispc_wb_fir_coef_h2_i_5 addr(base, 0x7C8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2919        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2920        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2921        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2922        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2923    };
2924    
2925    register dispc_wb_fir_coef_h2_i_6 addr(base, 0x7D0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2926        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2927        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2928        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2929        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2930    };
2931    
2932    register dispc_wb_fir_coef_h2_i_7 addr(base, 0x7D8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2933        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
2934        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
2935        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
2936        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
2937    };
2938    
2939    register dispc_wb_fir_coef_hv2_i_0 addr(base, 0x7A4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2940        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2941        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2942        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2943        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2944    };
2945    
2946    register dispc_wb_fir_coef_hv2_i_1 addr(base, 0x7AC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2947        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2948        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2949        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2950        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2951    };
2952    
2953    register dispc_wb_fir_coef_hv2_i_2 addr(base, 0x7B4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2954        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2955        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2956        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2957        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2958    };
2959    
2960    register dispc_wb_fir_coef_hv2_i_3 addr(base, 0x7BC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2961        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2962        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2963        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2964        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2965    };
2966    
2967    register dispc_wb_fir_coef_hv2_i_4 addr(base, 0x7C4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2968        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2969        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2970        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2971        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2972    };
2973    
2974    register dispc_wb_fir_coef_hv2_i_5 addr(base, 0x7CC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2975        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2976        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2977        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2978        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2979    };
2980    
2981    register dispc_wb_fir_coef_hv2_i_6 addr(base, 0x7D4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2982        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2983        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2984        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2985        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2986    };
2987    
2988    register dispc_wb_fir_coef_hv2_i_7 addr(base, 0x7DC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2989        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
2990        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
2991        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
2992        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
2993    };
2994    
2995    register dispc_wb_fir_coef_v2_i_0 addr(base, 0x7E0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
2996        _ 16 mbz;
2997        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
2998        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
2999    };
3000    
3001    register dispc_wb_fir_coef_v2_i_1 addr(base, 0x7E4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3002        _ 16 mbz;
3003        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
3004        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
3005    };
3006    
3007    register dispc_wb_fir_coef_v2_i_2 addr(base, 0x7E8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3008        _ 16 mbz;
3009        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
3010        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
3011    };
3012    
3013    register dispc_wb_fir_coef_v2_i_3 addr(base, 0x7EC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3014        _ 16 mbz;
3015        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
3016        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
3017    };
3018    
3019    register dispc_wb_fir_coef_v2_i_4 addr(base, 0x7F0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3020        _ 16 mbz;
3021        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
3022        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
3023    };
3024    
3025    register dispc_wb_fir_coef_v2_i_5 addr(base, 0x7F4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3026        _ 16 mbz;
3027        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
3028        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
3029    };
3030    
3031    register dispc_wb_fir_coef_v2_i_6 addr(base, 0x7F8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3032        _ 16 mbz;
3033        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
3034        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
3035    };
3036    
3037    register dispc_wb_fir_coef_v2_i_7 addr(base, 0x7FC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3038        _ 16 mbz;
3039        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
3040        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
3041    };
3042
3043    constants wb_bottom_buffer_status width(3) "" {
3044        WB_BOTTOM_BUFFER_0 = 0 "DMA buffer allocated to the graphics pipeline.";
3045        WB_BOTTOM_BUFFER_1 = 1 "DMA buffer allocated to the video1 pipeline.";
3046        WB_BOTTOM_BUFFER_2 = 2 "DMA buffer allocated to the vdieo2 pipeline.";
3047        WB_BOTTOM_BUFFER_3 = 3 "DMA buffer allocated to the vdieo3 pipeline.";
3048        WB_BOTTOM_BUFFER_4 = 4 "DMA buffer allocated to the write-back pipeline.";
3049    };
3050    
3051    register dispc_global_buffer addr(base, 0x800) "The register configures the DMA buffers allocations to the pipeline (graphics, video1, video2, video3 and write-back). Both TOP and BOTTOM must be allocated to the same pipeline." {
3052        _ 2 mbz;
3053        wb_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Write-back DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline.";
3054        wb_top_buffer 3 rw type(wb_bottom_buffer_status) "Write-back DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline.";
3055        vid3_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Video3 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline.";
3056        vid3_top_buffer 3 rw type(wb_bottom_buffer_status) "Video3 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline.";
3057        vid2_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Video2 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline.";
3058        vid2_top_buffer 3 rw type(wb_bottom_buffer_status) "Video2 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline.";
3059        vid1_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Video1 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video1 pipeline.";
3060        vid1_top_buffer 3 rw type(wb_bottom_buffer_status) "Video1 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video 1 pipeline.";
3061        gfx_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Graphics DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline.";
3062        gfx_top_buffer 3 rw type(wb_bottom_buffer_status) "Graphics DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline.";
3063    };
3064
3065    constants enable_status1 width(1) "" {
3066        ENABLE_0_5 = 0 ".LCD bit field is used";
3067        ENABLE_1_5 = 1 ".LCD bit field is used";
3068    };
3069    
3070    register dispc_divisor addr(base, 0x804) "The register configures the divisor value for generating the core functional clock. There is a backward compatibility mode enabled by default in order to use.LCD value instead of .LCD bit field for generating the core functional clock." {
3071        _ 8 mbz;
3072        lcd 8 rw "Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock. The value 0 is invalid.";
3073        _ 15 mbz;
3074        enable 1 rw type(enable_status1) "When the bit field is set to 1, the bit field LCD is used to generated the core functional clock from the input clock. When the bit field is set to 0, the valueDISPC_DIVISOR1.LCD is used instead.";
3075    };
3076    
3077    register dispc_wb_attributes2 addr(base, 0x810) "The register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
3078        _ 24 mbz;
3079        wbdelaycount 8 rw "Delays the WB pipe flush after the end of the frame.delay = n x (1/F_clk) n = 0:255";
3080    };
3081};