/*
 * Copyright (c) 2013 ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
 * Attn: Systems Group.
 */

/*
 * omap44xx_dispc_l4_per.dev
 *
 * DESCRIPTION: 
 *
 * NOTE: This file has been automatically generated based on the
 * XML files extracted from the TI RDT v1.0.0.4p Tool.
 * Download from here: http://www.ti.com/product/omap4460
 * This means that the file might not be optimal in terms of naming
 * conventions for constants and registers (duplicated
 * namespaces in register and device name etc.).
 * Also, because of the underlying structure from the original XML
 * it's possible that some constants appear multiple times (if they
 * have slightly different descriptions for example).
 *
 * You want to clean that up before using the files for the first time!
 */
 
device omap44xx_dispc_l4_per msbfirst ( addr base ) "" {
    
    
    register dispc_revision ro addr(base, 0x0) "IP Revision" type(uint32);

    constants midlemode_status width(2) "" {
        MIDLEMODE_0 = 0 "Force-standby. MStandby is only asserted when the module is disabled. MStandby is only asserted when the module is disabled.";
        MIDLEMODE_1 = 1 "No-Standby: MStandby is never asserted.";
        MIDLEMODE_2 = 2 "Smart-Standby. MStandby is asserted based on the internal activity of the module";
        MIDLEMODE_3 = 3 "Reserved";
    };

    constants clockactivity_status width(2) "" {
        CLOCKACTIVITY_0 = 0 "OCP and Functional clocks can be switched off";
        CLOCKACTIVITY_1 = 1 "Functional clocks can be switched off and OCP clocks are maintained during wake up period";
        CLOCKACTIVITY_2 = 2 "OCP clocks can be switched off and Functional clocks are maintained during wake up period";
        CLOCKACTIVITY_3 = 3 "OCP and Functional clocks are maintained during wake up period";
    };

    constants warmreset_status width(1) "" {
        WARMRESET_0 = 0 "Normal mode";
        WARMRESET_1 = 1 "the warmreset is set";
    };

    constants sidlemode_status width(2) "" {
        SIDLEMODE_0 = 0 "Force-idle. An idle request is acknowledged unconditionally";
        SIDLEMODE_1 = 1 "No-idle. An idle request is never acknowledged";
        SIDLEMODE_2 = 2 "Smart-idle. Acknowledgment to an idle request is given based on the internal activity of the module.";
        SIDLEMODE_3 = 3 "Reserved";
    };

    constants enwakeup_status width(1) "" {
        ENWAKEUP_0 = 0 "Wakeup is disabled";
        ENWAKEUP_1 = 1 "Wakeup is enabled";
    };

    constants softreset_status width(1) "" {
        SOFTRESET_0 = 0 "Normal mode";
        SOFTRESET_1 = 1 "The module is reset";
    };

    constants autoidle_status width(1) "" {
        AUTOIDLE_0 = 0 "OCP clock is free-running";
        AUTOIDLE_1 = 1 "Automatic OCP L3 and L4 clocks gating strategy is applied, based on the OCP interface activity. Automatic functional clock gating is also applied to the functional clock based on the module activity (for instance DISPC_<pipe>_ATTRIBUTES.ENABLE)";
    };
    
    register dispc_sysconfig addr(base, 0x10) "This register allows to control various parameters of the OCP interface." {
        _ 18 mbz;
        midlemode 2 rw type(midlemode_status) "Master interface power management, standby/wait control";
        _ 2 mbz;
        clockactivity 2 rw type(clockactivity_status) "Clocks activity during wake up mode period";
        _ 2 mbz;
        warmreset 1 rw type(warmreset_status) "Warm reset. Set this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During reads, it always returns 0. The warm reset keep the configuration registers unchanged.";
        sidlemode 2 rw type(sidlemode_status) "Slave interface power management, Idle req/ack control";
        enwakeup 1 rw type(enwakeup_status) "WakeUp feature control";
        softreset 1 rw type(softreset_status) "Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0.";
        autoidle 1 rw type(autoidle_status) "Internal OCP clock gating strategy";
    };

    constants resetdone_status width(1) "" {
        RESETDONE_0_r = 0 "Internal module reset is on-going";
        RESETDONE_1_r = 1 "Reset completed";
    };
    
    register dispc_sysstatus addr(base, 0x14) "This register provides status information about the module, excluding the interrupt status information." {
        _ 31 mbz;
        resetdone 1 ro type(resetdone_status) "Internal reset monitoring";
    };

    constants wbbuffer_overflow_irq_status width(1) "" {
        WBBUFFER_OVERFLOW_IRQ_0 = 0 "READS: Event is false. WRITES: Status bit unchanged.";
        WBBUFFER_OVERFLOW_IRQ_1 = 1 "READS: Event is true (pending). WRITES: Status bit is reset.";
    };
    
    register dispc_irqstatus addr(base, 0x18) "This register regroups all the status of the module internal events that generate an interrupt. Write 1 to a given bit resets this bit" {
        _ 5 mbz;
        wbuncompleteerror_irq 1 rw1c "Write-back DMA buffer is flushed before it is completely drained. In WB capture mode, if the new frame starts before the WB DMA buffers are fully drained (onto external memory), then the contents of the WB DMA buffers are lost (implying last few pixels/lines are corrupted in the captured frame in memory). This interrupt is an indication of that case and will trigger every frame.0x0 READS: Event is false. . 0x0 WRITES: Status bit unchanged. . 0x1 READS: Event is true (Pending). . 0x1 WRITES: Status bit is reset. .";
        wbbuffer_overflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Write-back DMA Buffer Overflow. The DMA buffer is full.";
        frame_donetv_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the TV. The TV output has been disabled by user. All the data have been sent.";
        frame_donewb_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the write-back channel. The write-back channel has output the frame. All the data of the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory. It is available only when the write-back pipeline transfers back to memory the output of one of the pipelines. In case of overlay capture, the interrupt is not generated and the user shall use the FrameDone for the corresponding captured output.";
        frame_done2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent.";
        acbiascount_status2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "AC Bias Count Status for the secondary LCD";
        vid3buffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Video 3 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
        vid3end_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed.";
        vsync2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Vertical Synchronization for the secondary LCD";
        sync_lost2_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output.";
        wakeup_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Wake-up";
        synclost_tv_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output.";
        sync_lost1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Synchronization Lost on the primary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the primary LCD output.";
        vid2end_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed.";
        vid2buffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Video 2 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
        vid1end_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed.";
        vid1buffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Video 1 DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
        ocperror_irq 1 rw1c type(wbbuffer_overflow_irq_status) "OCP Error. L3 Interconnect has sent SResp=ERR.";
        palettegamma_loading_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Palette Gamma Loading status. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.";
        gfxend_window_irq 1 rw1c type(wbbuffer_overflow_irq_status) "The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed.";
        gfxbuffer_underflow_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
        programmed_linenumber_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number.";
        acbiascount_status1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "AC Bias Count Status for the primary LCD";
        evsync_odd_irq 1 rw1c type(wbbuffer_overflow_irq_status) "VSYNC for odd field from the TV encoder (VENC or HDMI)";
        evsync_even_irq 1 rw1c type(wbbuffer_overflow_irq_status) "VSYNC for even field from the TV encoder (VENC or HDMI)";
        vsync1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Vertical Synchronization for the primary LCD.";
        frame_done1_irq 1 rw1c type(wbbuffer_overflow_irq_status) "Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent.";
    };

    constants wbuncompleteerror_en_status width(1) "" {
        WBUNCOMPLETEERROR_EN_0 = 0 "Interrupt is masked.";
        WBUNCOMPLETEERROR_EN_1 = 1 "Interrupt is enabled.";
    };

    constants wbbuffer_overflow_en_status width(1) "" {
        WBBUFFER_OVERFLOW_EN_0 = 0 "WBBufferOverflow is masked";
        WBBUFFER_OVERFLOW_EN_1 = 1 "WBBufferOverflow generates an interrupt when it occurs";
    };

    constants frame_donetv_en_status width(1) "" {
        FRAME_DONETV_EN_0 = 0 "Frame Done for the TV output is masked";
        FRAME_DONETV_EN_1 = 1 "Frame Done for the TV output generates an interrupt when it occurs";
    };

    constants frame_donewb_en_status width(1) "" {
        FRAME_DONEWB_EN_0 = 0 "Frame Done for the write-back is masked";
        FRAME_DONEWB_EN_1 = 1 "Frame Done for the write-back generates an interrupt when it occurs";
    };

    constants frame_done2_en_status width(1) "" {
        FRAME_DONE2_EN_0 = 0 "Frame Done for the secondary LCD is masked";
        FRAME_DONE2_EN_1 = 1 "Frame Done for the secondary LCD generates an interrupt when it occurs";
    };

    constants vid3buffer_underflow_en_status width(1) "" {
        VID3BUFFER_UNDERFLOW_EN_0 = 0 "Vid3BufferUnderflow is masked";
        VID3BUFFER_UNDERFLOW_EN_1 = 1 "Vid3BufferUnderflow generates an interrupt when it occurs";
    };

    constants vid3end_window_en_status width(1) "" {
        VID3END_WINDOW_EN_0 = 0 "Vid3EndWindow is masked";
        VID3END_WINDOW_EN_1 = 1 "Vid3EndWindow generates an interrupt when it occurs";
    };

    constants vsync2_en_status width(1) "" {
        VSYNC2_EN_0 = 0 "VSYNC for the secondary LCD output is masked";
        VSYNC2_EN_1 = 1 "VSYNC for the secondary LCD output generates an interrupt when it occurs";
    };

    constants wakeup_en_status width(1) "" {
        WAKEUP_EN_0 = 0 "WakeUp is masked";
        WAKEUP_EN_1 = 1 "WakeUp generates an interrupt when it occurs";
    };

    constants sync_losttv_en_status width(1) "" {
        SYNC_LOSTTV_EN_0 = 0 "Synchronization Lost on the TV output is masked";
        SYNC_LOSTTV_EN_1 = 1 "Synchronization Lost on the TV output generates an interrupt when it occurs";
    };

    constants vid2end_window_en_status width(1) "" {
        VID2END_WINDOW_EN_0 = 0 "Vid2EndWindow is masked";
        VID2END_WINDOW_EN_1 = 1 "Vid2EndWindow generates an interrupt when it occurs";
    };

    constants vid2buffer_underflow_en_status width(1) "" {
        VID2BUFFER_UNDERFLOW_EN_0 = 0 "Vid2BufferUnderflow is masked";
        VID2BUFFER_UNDERFLOW_EN_1 = 1 "Vid2BufferUnderflow generates an interrupt when it occurs";
    };

    constants endvid1_window_en_status width(1) "" {
        ENDVID1_WINDOW_EN_0 = 0 "EndVid1Window is masked";
        ENDVID1_WINDOW_EN_1 = 1 "EndVid1Window generates an interrupt when it occurs";
    };

    constants vid1buffer_underflow_en_status width(1) "" {
        VID1BUFFER_UNDERFLOW_EN_0 = 0 "Vid1BufferUnderflow is masked";
        VID1BUFFER_UNDERFLOW_EN_1 = 1 "Vid1BufferUnderflow generates an interrupt when it occurs";
    };

    constants ocperror_en_status width(1) "" {
        OCPERROR_EN_0 = 0 "OCPError is masked";
        OCPERROR_EN_1 = 1 "OCPError generates an interrupt when it occurs";
    };

    constants palette_gamma_en_status width(1) "" {
        PALETTE_GAMMA_EN_0 = 0 "PaletteGamma is masked";
        PALETTE_GAMMA_EN_1 = 1 "PaletteGamma generates an interrupt when it occurs";
    };

    constants gfxend_window_en_status width(1) "" {
        GFXEND_WINDOW_EN_0 = 0 "GfxEndWindow is masked";
        GFXEND_WINDOW_EN_1 = 1 "GfxEndWindow generates an interrupt when it occurs";
    };

    constants gfxbuffer_underflow_en_status width(1) "" {
        GFXBUFFER_UNDERFLOW_EN_0 = 0 "GfxBufferUnderflow is masked";
        GFXBUFFER_UNDERFLOW_EN_1 = 1 "GfxBufferUnderflow generates an interrupt when it occurs";
    };

    constants programmed_linenumber_en_status width(1) "" {
        PROGRAMMED_LINENUMBER_EN_0 = 0 "ProgrammedLineNumber is masked";
        PROGRAMMED_LINENUMBER_EN_1 = 1 "ProgrammedLineNumber generates an interrupt when it occurs";
    };

    constants evsync_odd_en_status width(1) "" {
        EVSYNC_ODD_EN_0 = 0 "EVSYNC_ODD for the TV output is masked";
        EVSYNC_ODD_EN_1 = 1 "EVSYNC_ODD for the TV output generates an interrupt when it occurs";
    };

    constants evsync_even_en_status width(1) "" {
        EVSYNC_EVEN_EN_0 = 0 "EVSYNC_EVEN for the TV output is masked";
        EVSYNC_EVEN_EN_1 = 1 "EVSYNC_EVEN for the TV output generates an interrupt when it occurs";
    };
    
    register dispc_irqenable addr(base, 0x1C) "This register allows to mask/unmask the module internal sources of interrupt, on an event-by-event basis" {
        _ 5 mbz;
        wbuncompleteerror_en 1 rw type(wbuncompleteerror_en_status) "The write back buffer has been flushed before it has been fully drained. Enable.";
        wbbuffer_overflow_en 1 rw type(wbbuffer_overflow_en_status) "Write-back DMA Buffer Overflow. The DMA buffer is full";
        frame_donetv_en 1 rw type(frame_donetv_en_status) "Frame Done for the TV. The TV output has been disabled by user. All the data have been sent.";
        frame_donewb_en 1 rw type(frame_donewb_en_status) "Frame Done for the write-back channel. The write-back channel has output the frame. All the data have been sent for the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory.";
        frame_done2_en 1 rw type(frame_done2_en_status) "Frame Done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent.";
        acbiascount_status2_en 1 rw type(frame_done2_en_status) "AC Bias Count Status for the secondary LCD";
        vid3buffer_underflow_en 1 rw type(vid3buffer_underflow_en_status) "Video 3 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)";
        vid3end_window_en 1 rw type(vid3end_window_en_status) "The end of the video 3 Window has been reached. It is detected by the overlay manager when the full video 3 has been displayed.";
        vsync2_en 1 rw type(vsync2_en_status) "Vertical Synchronization for the secondary LCD";
        sync_lost2_en 1 rw type(frame_done2_en_status) "Synchronization Lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output.";
        wakeup_en 1 rw type(wakeup_en_status) "Wake Up Mask";
        sync_losttv_en 1 rw type(sync_losttv_en_status) "Synchronization Lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output.";
        sync_lost1_en 1 rw type(frame_done2_en_status) "Synchronization Lost for the primary LCD";
        vid2end_window_en 1 rw type(vid2end_window_en_status) "The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed.";
        vid2buffer_underflow_en 1 rw type(vid2buffer_underflow_en_status) "Video 2 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)";
        endvid1_window_en 1 rw type(endvid1_window_en_status) "The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed.";
        vid1buffer_underflow_en 1 rw type(vid1buffer_underflow_en_status) "Video 1 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)";
        ocperror_en 1 rw type(ocperror_en_status) "OCP Error. L3 Interconnect has sent SResp=ERR.";
        palette_gamma_en 1 rw type(palette_gamma_en_status) "Palette Gamma Loading mask. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.";
        gfxend_window_en 1 rw type(gfxend_window_en_status) "The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed.";
        gfxbuffer_underflow_en 1 rw type(gfxbuffer_underflow_en_status) "Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)";
        programmed_linenumber_en 1 rw type(programmed_linenumber_en_status) "Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number.";
        acbiascount_status1_en 1 rw type(frame_done2_en_status) "AC Bias Count Status for the primary LCD";
        evsync_odd_en 1 rw type(evsync_odd_en_status) "VSYNC for odd field from the TV encoder (VENC or HDMI)";
        evsync_even_en 1 rw type(evsync_even_en_status) "VSYNC for even field from the TV encoder (VENC or HDMI)";
        vsync1_en 1 rw type(vsync2_en_status) "Vertical Synchronization for the primary LCD.";
        framedone_en 1 rw type(frame_done2_en_status) "Frame Done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent.";
    };

    constants spatialtemporal_ditheringframes_status width(2) "" {
        SPATIALTEMPORAL_DITHERINGFRAMES_0 = 0 "Spatial only";
        SPATIALTEMPORAL_DITHERINGFRAMES_1 = 1 "Spatial and temporal over 2 frames";
        SPATIALTEMPORAL_DITHERINGFRAMES_2 = 2 "Spatial and temporal over 4 frames";
        SPATIALTEMPORAL_DITHERINGFRAMES_3 = 3 "Reserved";
    };

    constants tdmunusedbits_status width(2) "" {
        TDMUNUSEDBITS_0 = 0 "low level (0)";
        TDMUNUSEDBITS_1 = 1 "high level (1)";
        TDMUNUSEDBITS_2 = 2 "unchanged from previous state";
        TDMUNUSEDBITS_3 = 3 "reserved";
    };

    constants tdmcycleformat_status width(2) "" {
        TDMCYCLEFORMAT_0 = 0 "1 cycle for 1 pixel";
        TDMCYCLEFORMAT_1 = 1 "2 cycles for 1 pixel";
        TDMCYCLEFORMAT_2 = 2 "3 cycles for 1 pixel";
        TDMCYCLEFORMAT_3 = 3 "3 cycles for 2 pixels";
    };

    constants tdmparallelmode_status width(2) "" {
        TDMPARALLELMODE_0 = 0 "8-bit parallel output interface selected";
        TDMPARALLELMODE_1 = 1 "9-bit parallel output interface selected";
        TDMPARALLELMODE_2 = 2 "12-bit parallel output interface selected";
        TDMPARALLELMODE_3 = 3 "16-bit parallel output interface selected";
    };

    constants tdmenable_status width(1) "" {
        TDMENABLE_0 = 0 "TDM disabled";
        TDMENABLE_1 = 1 "TDM enabled";
    };

    constants gpout1_status width(1) "" {
        GPOUT1_0 = 0 "The GPout1 is reset";
        GPOUT1_1 = 1 "The GPout1 is set";
    };

    constants gpout0_status width(1) "" {
        GPOUT0_0 = 0 "The GPout0 is reset";
        GPOUT0_1 = 1 "The GPout0 is set";
    };

    constants gpin1_status width(1) "" {
        GPIN1_0_r = 0 "The GPin1 has been reset";
        GPIN1_1_r = 1 "The GPin1 has been set";
    };

    constants gpin0_status width(1) "" {
        GPIN0_0_r = 0 "The GPin0 has been reset";
        GPIN0_1_r = 1 "The GPin0 has been set";
    };

    constants stallmode_status width(1) "" {
        STALLMODE_0 = 0 "Normal mode selected";
        STALLMODE_1 = 1 "STALL mode selected. The Display Controller sends the data without considering the VSYNC/HSYNC. The LCD output is disabled at the end of the transfer of the frame. The S/W has to re-enable the LCD output in order to generate a new frame. The stall mode is used in RFBI and DSI command modes.";
    };

    constants tftdatalines_status width(2) "" {
        TFTDATALINES_0 = 0 "12-bit output aligned on the LSB of the pixel data interface";
        TFTDATALINES_1 = 1 "16-bit output aligned on the LSB of the pixel data interface";
        TFTDATALINES_2 = 2 "18-bit output aligned on the LSB of the pixel data interface";
        TFTDATALINES_3 = 3 "24-bit output aligned on the LSB of the pixel data interface";
    };

    constants gotv_status width(1) "" {
        GOTV_0 = 0 "The hardware has finished updating the internal shadow registers of the pipeline(s) associated with the TV output using the user values. The hardware resets the bit when the update is completed.";
        GOTV_1 = 1 "The user has finished to program the shadow registers of the pipeline(s) associated with the TV output and the hardware can update the internal registers at the external VSYNC.";
    };

    constants golcd_status width(1) "" {
        GOLCD_0 = 0 "The hardware has finished updating the internal shadow registers of the pipeline(s) connected to the LCD output using the user values. The hardware resets the bit when the update is completed.";
        GOLCD_1 = 1 "The user has finished to program the shadow registers of the pipeline(s) associated with the LCD output and the hardware can update the internal registers at the VFP start period";
    };

    constants stntft_status width(1) "" {
        STNTFT_0 = 0 "Passive or STN display operation enabled. STN dither logic is enabled.";
        STNTFT_1 = 1 "Active or TFT display operation enabled. STN Dither logic and output FIFO bypassed.";
    };

    constants monocolor_status width(1) "" {
        MONOCOLOR_0 = 0 "Color operation enabled (STN mode only)";
        MONOCOLOR_1 = 1 "Monochrome operation enabled (STN mode only)";
    };

    constants tvenable_status width(1) "" {
        TVENABLE_0 = 0 "TV output disabled (at the end of the current field if interlace output when the bit is reset)";
        TVENABLE_1 = 1 "TV output enabled";
    };

    constants lcdenable_status width(1) "" {
        LCDENABLE_0 = 0 "LCD output disabled (at the end of the frame when the bit is reset)";
        LCDENABLE_1 = 1 "LCD output enabled";
    };
    
    register dispc_control1 addr(base, 0x40) "The control register configures the Display Controller module for the primary LCD and TV outputs." {
        spatialtemporal_ditheringframes 2 rw type(spatialtemporal_ditheringframes_status) "Spatial/Temporal dithering number of frames for the primary LCD output wr: VFP start period of primary LCD";
        lcdenablepol 1 ro "Write 0s for future compatibility. Reads return 0.";
        lcdenablesignal 1 ro "Write 0s for future compatibility. Reads return 0.";
        pckfreeenable 1 ro "Write 0s for future compatibility. Reads return 0.";
        tdmunusedbits 2 rw type(tdmunusedbits_status) "State of unused bits (TDM mode only) for the primary LCD output. wr: VFP start period of primary LCD";
        tdmcycleformat 2 rw type(tdmcycleformat_status) "Cycle format (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD";
        tdmparallelmode 2 rw type(tdmparallelmode_status) "Output Interface width (TDM mode only) for the primary LCD output wr: VFP start period of primary LCD";
        tdmenable 1 rw type(tdmenable_status) "Enable the multiple cycle format (TDM mode only used for TFT mode with the RFBI enable bit off) for the primary LCD output. wr: VFP start period of primary LCD";
        ht 3 rw "Hold Time for TV output wr: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)";
        gpout1 1 rw type(gpout1_status) "General Purpose Output Signal wr:immediate";
        gpout0 1 rw type(gpout0_status) "General Purpose Output Signal wr:immediate";
        gpin1 1 ro type(gpin1_status) "General Purpose Input Signal wr: immediately";
        gpin0 1 ro type(gpin0_status) "General Purpose Input Signal wr: immediately";
        overlayopti_mization 1 rw type(sidlemode_status) "Overlay Optimization for the primary LCD output wr: VFP start period of the primary LCD";
        stallmode 1 rw type(stallmode_status) "STALL Mode for the primary LCD output wr: VFP start period of primary LCD";
        _ 1 mbz;
        tftdatalines 2 rw type(tftdatalines_status) "Number of lines of the primary LCD interface wr: VFP start period of primary LCD";
        stditherenable 1 rw type(sidlemode_status) "Spatial Temporal dithering enable for the primary LCD output wr: VFP start period of primary LCD";
        gotv 1 rw type(gotv_status) "GO Command for the TV output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the TV output. wr: immediate";
        golcd 1 rw type(golcd_status) "GO Command for the primary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the primary LCD output. wr: immediate";
        m8b 1 rw type(sidlemode_status) "Mono 8-bit mode of the primary LCD wr: VFP start period of primary LCD output";
        stntft 1 rw type(stntft_status) "LCD Display type of the primary LCD wr: VFP start period of primary LCD output";
        monocolor 1 rw type(monocolor_status) "Monochrome/Color selection for the primary LCD wr: VFP start period of primary LCD output";
        tvenable 1 rw type(tvenable_status) "Enable the TV output wr: immediate effect only occurs at the end of the current frame.";
        lcdenable 1 rw type(lcdenable_status) "Enable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frame";
    };

    constants fullrange_status width(1) "" {
        FULLRANGE_0 = 0 "Limited range selected.";
        FULLRANGE_1 = 1 "Full range selected.";
    };

    constants colorconv_enable_status width(1) "" {
        COLORCONV_ENABLE_0 = 0 "Disable Color Space Conversion RGB to YUV";
        COLORCONV_ENABLE_1 = 1 "Enable Color Space Conversion RGB to YUV";
    };

    constants fidfirst_status width(1) "" {
        FIDFIRST_0 = 0 "First field is even.";
        FIDFIRST_1 = 1 "Odd field is first.";
    };

    constants outputmode_enable_status width(1) "" {
        OUTPUTMODE_ENABLE_0 = 0 "Progressive mode selected.";
        OUTPUTMODE_ENABLE_1 = 1 "Interlace mode selected.";
    };

    constants tvalphablender_enable_status width(1) "" {
        TVALPHABLENDER_ENABLE_0 = 0 "Alpha blender is disabled.";
        TVALPHABLENDER_ENABLE_1 = 1 "The alpha blender is enabled.";
    };

    constants lcdalphablender_enable_status width(1) "" {
        LCDALPHABLENDER_ENABLE_0 = 0 "Alpha blender is disabled. The color key alpha blending is used.";
        LCDALPHABLENDER_ENABLE_1 = 1 "The alpha blender is enabled.";
    };

    constants bufferfilling_status width(1) "" {
        BUFFERFILLING_0 = 0 "Each DMA buffer is refilled when it reaches LOW threshold.";
        BUFFERFILLING_1 = 1 "All DMA buffers are refilled up to high threshold when at least one of them reaches the LOW threshold. (only active DMA buffers shall be considered and when reaching the end of the frame the DMA buffer goes to empty condition so no need to fill it again).";
    };

    constants bufferhand_check_status width(1) "" {
        BUFFERHAND_CHECK_0 = 0 "Only the STALL signal (generated by RFBI, DSI1 or DSI2 depending on which IP uses the LCD output) is used regardless of the DMA buffer fullness information in order to provide data to the RFBI,DSI1 or DS2 module.";
        BUFFERHAND_CHECK_1 = 1 "The STALL signal (generated by RFBI, DSI1 or DSI2 depending on which IP uses the LCD output) is used in combination with the DMA buffer fullness information in order to provide data to the RFBI, DSI1 or DSI2 module only when it does not generated buffer underflow.";
    };

    constants cpr_status width(1) "" {
        CPR_0 = 0 "Color Phase Rotation Disabled";
        CPR_1 = 1 "Color Phase Rotation Enabled";
    };

    constants buffermerge_status width(1) "" {
        BUFFERMERGE_0 = 0 "DMA buffer merge disabled Each DMA buffer is dedicated to one pipeline.";
        BUFFERMERGE_1 = 1 "DMA buffer merge enabled All the DMA buffers are merged into a single one to be used by the single active pipeline.";
    };

    constants tcktv_selection_status width(1) "" {
        TCKTV_SELECTION_0 = 0 "Destination transparency color key selected";
        TCKTV_SELECTION_1 = 1 "Source transparency color key selected";
    };

    constants gamatable_enable_status width(1) "" {
        GAMATABLE_ENABLE_0 = 0 "Gamma table LDC2 and TV are bypassed";
        GAMATABLE_ENABLE_1 = 1 "Gamma table LCD2 and TV are enabled";
    };

    constants acbiasgated_status width(1) "" {
        ACBIASGATED_0 = 0 "AcBias Gated Disabled";
        ACBIASGATED_1 = 1 "AcBias Gated Enabled";
    };

    constants vsyncgated_status width(1) "" {
        VSYNCGATED_0 = 0 "VSYNC Gated Disabled";
        VSYNCGATED_1 = 1 "VSYNC Gated Enabled";
    };

    constants hsyncgated_status width(1) "" {
        HSYNCGATED_0 = 0 "HSYNC Gated Disabled";
        HSYNCGATED_1 = 1 "HSYNC Gated Enabled";
    };

    constants pixelclock_gated_status width(1) "" {
        PIXELCLOCK_GATED_0 = 0 "Pixel Clock Gated Disabled";
        PIXELCLOCK_GATED_1 = 1 "Pixel Clock Gated Enabled";
    };

    constants pixeldatagated_status width(1) "" {
        PIXELDATAGATED_0 = 0 "Pixel Data Gated Disabled";
        PIXELDATAGATED_1 = 1 "Pixel Data Gated Enabled";
    };

    constants palettegamma_table_status width(1) "" {
        PALETTEGAMMA_TABLE_0 = 0 "LUT used as palette (only if graphics format is BITMAP1, 2, 4, and 8)";
        PALETTEGAMMA_TABLE_1 = 1 "LUT used as gamma table (only if graphics format is NOT BITMAP1, 2, 4, and 8 or no graphics window present)";
    };

    constants loadmode_status width(2) "" {
        LOADMODE_0 = 0 "Palette/Gamma Table and data are loaded every frame";
        LOADMODE_1 = 1 "Palette/Gamma Table to be loaded. The user sets the bit when the palette/gamma table has to be loaded. Hardware resets the bit to 0x2 when table has been loaded. (.ENABLE has to be set to 1).";
        LOADMODE_2 = 2 "Frame data only loaded every frame";
        LOADMODE_3 = 3 "Palette/Gamma Table and frame data loaded on first frame then switch to 0x2 (Hardware).";
    };

    constants pixelgated_status width(1) "" {
        PIXELGATED_0 = 0 "Pixel clock always toggles (only in TFT mode)";
        PIXELGATED_1 = 1 "Pixel clock only toggles when there is valid data to display. (only in TFT mode)";
    };
    
    register dispc_config1 addr(base, 0x44) "The control register configures the Display Controller module for the primary LCD output and TV output. Shadow register, updated on VFP start period of primary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 6 mbz;
        fullrange 1 rw type(fullrange_status) "Color Space Conversion full range setting. wr: VFP start of primary LCD";
        colorconv_enable 1 rw type(colorconv_enable_status) "Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. wr: VFP start of primary LCD";
        fidfirst 1 rw type(fidfirst_status) "Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. wr: VFP start of primary LCD";
        outputmode_enable 1 rw type(outputmode_enable_status) "Selects between progressive and interlace mode for the primary LCD output. wr: VFP start of primary LCD";
        _ 2 mbz;
        tvalphablender_enable 1 rw type(tvalphablender_enable_status) "Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated pipeline connected to the TV output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: EVSYNC start of primary LCD";
        lcdalphablender_enable 1 rw type(lcdalphablender_enable_status) "Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated with the primary LCD output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: VFP start of primary LCD";
        bufferfilling 1 rw type(bufferfilling_status) "Controls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold. wr: immediate";
        bufferhand_check 1 rw type(bufferhand_check_status) "Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (primary LCD output) wr: VFP start of primary LCD";
        cpr 1 rw type(cpr_status) "Color Phase Rotation Control (primary LCD output). It shall be reset when ColorConvEnable bit field is set to 1 wr: VFP start period of primary LCD output";
        buffermerge 1 rw type(buffermerge_status) "Buffer merge control wr: EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory or VFP When enabled, the DISPC_GLOBAL_BUFFER register is ignored. This bit must be set to zero when the write back channel is used. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero. wr: immediate";
        tcktv_selection 1 rw type(tcktv_selection_status) "Transparency Color Key Selection (TV output) wr: EVSYNC";
        tcktvenable 1 rw type(sync_losttv_en_status) "Transparency Color Key Enabled (TV output) wr: EVSYNC";
        tcklcd_selection 1 rw type(tcktv_selection_status) "Transparency Color Key Selection (primary LCD output) wr: VFP start period of primary LCD output";
        tcklcdenable 1 rw type(frame_done2_en_status) "Transparency Color Key Enabled (primary LCD output) wr: VFP start period of primary LCD output";
        gamatable_enable 1 rw type(gamatable_enable_status) "For backward compatibility, an enable bit has been added on the 2 additional gamma tables (secondary display and TV). Gamma table of LCD1 is always enabled.";
        acbiasgated 1 rw type(acbiasgated_status) "ACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
        vsyncgated 1 rw type(vsyncgated_status) "VSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
        hsyncgated 1 rw type(hsyncgated_status) "HSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
        pixelclock_gated 1 rw type(pixelclock_gated_status) "Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
        pixeldatagated 1 rw type(pixeldatagated_status) "Pixel Data Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output";
        palettegamma_table 1 rw type(palettegamma_table_status) "Palette/Gamma Table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the graphics pipeline: primary LCD, secondary LCD, TV output or write-back to the memory. In case of the table is used as gamma table, it is used for the primary LCD output only.";
        loadmode 2 rw type(loadmode_status) "Loading Mode for the Palette/Gamma Table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory";
        pixelgated 1 rw type(pixelgated_status) "Pixel Gated Enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD output";
    };
    
    register dispc_default_color0 addr(base, 0x4C) "The control register allows to configure the default solid background color for the primary LCD. Shadow register, updated on VFP start period of the primary LCD" {
        _ 8 mbz;
        defaultcolor 24 rw "24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.";
    };
    
    register dispc_default_color1 addr(base, 0x50) "The control register allows to configure the default solid background color for the TV output. Shadow register, updated on EVSYNC" {
        _ 8 mbz;
        defaultcolor 24 rw "24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.";
    };
    
    register dispc_trans_color0 addr(base, 0x54) "The register sets the transparency color value for the video/graphics overlays for the primary LCD output. Shadow register, updated on VFP start period of the primary LCD" {
        _ 8 mbz;
        transcolorkey 24 rw "Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24";
    };
    
    register dispc_trans_color1 addr(base, 0x58) "The register sets the transparency color value for the video/graphics overlays for the TV output. Shadow register, updated on EVSYNC" {
        _ 8 mbz;
        transcolorkey 24 rw "Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24";
    };
    
    register dispc_line_status addr(base, 0x5C) "The control register indicates the current primary LCD panel display line number." {
        _ 21 mbz;
        linenumber 11 ro "Current LCD panel line number Current display line number. The first active line has the value 0. During blanking lines the line number is not incremented.";
    };
    
    register dispc_line_number addr(base, 0x60) "The control register indicates the primary LCD panel display line number for the interrupt and the DMA request. Shadow register, updated on VFP start period of primary LCD." {
        _ 21 mbz;
        linenumber 11 rw "LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs.";
    };
    
    register dispc_timing_h1 addr(base, 0x64) "The register configures the timing logic for the HSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
        hbp 12 rw "Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field.";
        hfp 12 rw "Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field.";
        hsw 8 rw "Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1). When in BT mode, this field corresponds to the horizontal blanking";
    };
    
    register dispc_timing_v1 addr(base, 0x68) "The register configures the timing logic for the VSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
        vbp 12 rw "Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame.";
        vfp 12 rw "Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame.";
        vsw 8 rw "Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode. In passive mode, encoded value (from 1 to 256) to specify the number of extra line clock periods (program to value minus 1) to insert after the vertical front porch (VFP) period has elapsed.";
    };

    constants align_status width(1) "" {
        ALIGN_0 = 0 "VSYNC and HSYNC are not aligned";
        ALIGN_1 = 1 "VSYNC and HSYNC assertions are aligned.";
    };

    constants onoff_status width(1) "" {
        ONOFF_0 = 0 "HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data";
        ONOFF_1 = 1 "HSYNC and VSYNC are driven according to bit 16";
    };
    
    register dispc_pol_freq1 addr(base, 0x6C) "The register configures the signal configuration. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD." {
        _ 13 mbz;
        align 1 rw type(align_status) "Defines the alignment between HSYNC and VSYNC assertion.";
        onoff 1 rw type(onoff_status) "HSYNC/VSYNC Pixel clock Control On/Off";
        rf 1 rw type(onoff_status) "Program HSYNC/VSYNC Rise or Fall";
        ieo 1 rw type(sidlemode_status) "Invert output enable";
        ipc 1 rw type(frame_done2_en_status) "Invert pixel clock";
        ihs 1 rw type(sidlemode_status) "Invert HSYNC";
        ivs 1 rw type(sidlemode_status) "Invert VSYNC";
        acbi 4 rw "AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions";
        acb 8 rw "AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display.";
    };
    
    register dispc_divisor1 addr(base, 0x70) "The register configures the divisors. It is used for the primary LCD output Shadow register, updated on VFP start period of primary LCD" {
        _ 8 mbz;
        lcd 8 rw "Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK. The value 0 is invalid.";
        _ 8 mbz;
        pcd 8 rw "Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided byDISPC_DIVISOR1.LCD value. The values 0 is invalid.";
    };
    
    register dispc_global_alpha addr(base, 0x74) "The register defines the global alpha value for the graphics and three video pipelines. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory for each bit field depending on the association of the each pipeline with the primary LCD, secondary LCD or TV output." {
        vid3globalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
        vid2globalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
        vid1globalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
        gfxglobalalpha 8 rw "Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.";
    };

    constants delta_lpp_status width(2) "" {
        DELTA_LPP_0 = 0 "Same size";
        DELTA_LPP_1 = 1 "Odd size = Even size +1";
        DELTA_LPP_2 = 2 "Odd size = Even Size -1";
    };
    
    register dispc_size_tv addr(base, 0x78) "The register configures the size of the TV output field (interlace), frame (progressive) (horizontal and vertical). Shadow register, updated on EVSYNC. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." {
        _ 5 mbz;
        lpp 11 rw "Lines per panel (LPP). Encoded value (from 1 to 2048) to specify the number of LPP.";
        delta_lpp 2 rw type(delta_lpp_status) "Indicates the delta size value of the odd field compared to the even field";
        _ 3 mbz;
        ppl 11 rw "Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display.";
    };

    constants delta_lpp_status1 width(2) "" {
        DELTA_LPP_0_1 = 0 "same size";
        DELTA_LPP_1_1 = 1 "Odd size = Even size +1";
        DELTA_LPP_2_1 = 2 "Odd size = Even Size -1";
    };
    
    register dispc_size_lcd1 addr(base, 0x7C) "The register configures the panel size (horizontal and vertical). Shadow register, updated on VFP start period of primary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." {
        _ 5 mbz;
        lpp 11 rw "Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1).";
        delta_lpp 2 rw type(delta_lpp_status1) "Indicates the delta size value of the odd field compared to the even field";
        _ 3 mbz;
        ppl 11 rw "Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid.";
    };
    
    register dispc_gfx_ba_j_0 rw addr(base, 0x80) "The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output and 0 and 1 when on the TV output). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_gfx_ba_j_1 rw addr(base, 0x84) "The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output and 0 and 1 when on the TV output). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_gfx_position addr(base, 0x88) "The register configures the position of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        posy 11 rw "Y position of the graphics window. Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0.";
        _ 5 mbz;
        posx 11 rw "X position of the graphics window. Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0.";
    };
    
    register dispc_gfx_size addr(base, 0x8C) "The register configures the size of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        sizey 11 rw "Number of lines of the graphics window. Encoded value (from 1 to 2048) to specify the number of lines of the graphics window (program to value minus 1).";
        _ 5 mbz;
        sizex 11 rw "Number of pixels of the graphics window. Encoded value (from 1 to 2048) to specify the number of pixels per line of the graphics window (program to value minus 1).";
    };

    constants channelout2_status width(2) "" {
        CHANNELOUT2_0 = 0 "primary LCD output selected.";
        CHANNELOUT2_1 = 1 "Secondary LCD output selected.";
        CHANNELOUT2_3 = 3 "Write-back output to the memory selected.";
    };

    constants bursttype_status width(1) "" {
        BURSTTYPE_0 = 0 "INC burst type is used.";
        BURSTTYPE_1 = 1 "2D block burst type is used.";
    };

    constants premultiplyalpha_status width(1) "" {
        PREMULTIPLYALPHA_0 = 0 "Non premultiplyalpha data color component";
        PREMULTIPLYALPHA_1 = 1 "Premultiplyalpha data color component";
    };

    constants zorderenable_status width(1) "" {
        ZORDERENABLE_0 = 0 "Z-order disabled. The Z-order of the layer is 0.";
        ZORDERENABLE_1 = 1 "Z-order enabled. The Z-order is defined by the bit field ZORDER (bits 26 and 27).";
    };

    constants antiflicker_status width(1) "" {
        ANTIFLICKER_0 = 0 "Antiflicker disabled.";
        ANTIFLICKER_1 = 1 "Antiflicker enabled.";
    };

    constants selfrefresh_status width(1) "" {
        SELFREFRESH_0 = 0 "The graphics pipeline accesses the interconnect to fetch data from the system memory.";
        SELFREFRESH_1 = 1 "The graphics pipeline does not need anymore to fetch data from memory. Only the graphics DMA buffer is used. It takes effect after the frame has been loaded in the DMA buffer.";
    };

    constants rotation_status width(2) "" {
        ROTATION_0 = 0 "No rotation";
        ROTATION_1 = 1 "Rotation by 90 degrees";
        ROTATION_3 = 3 "Rotation by 270 degrees";
        ROTATION_2 = 2 "Rotation by 180 degrees";
    };

    constants nibblemode_status width(1) "" {
        NIBBLEMODE_0 = 0 "Nibble mode is disabled";
        NIBBLEMODE_1 = 1 "Nibble mode is enabled";
    };

    constants channelout_status width(1) "" {
        CHANNELOUT_0 = 0 "LCD output or WB to the memory selected. bit fields 31 and 30 defines the output associated (primary, secondary or write-back).";
        CHANNELOUT_1 = 1 "TV output selected";
    };

    constants burstsize_status width(2) "" {
        BURSTSIZE_0 = 0 "2x128bit bursts";
        BURSTSIZE_1 = 1 "4x128bit bursts";
        BURSTSIZE_3 = 3 "Reserved";
        BURSTSIZE_2 = 2 "8x128bit bursts";
    };

    constants replicationenable_status width(1) "" {
        REPLICATIONENABLE_0 = 0 "Disable Graphics replication logic. The conversion to ARGB32-8888 is done by adding 0s for the LSBs";
        REPLICATIONENABLE_1 = 1 "Enable Graphics replication logic. The conversion to ARGB32-8888 is done by duplicating the MSBs for the LSBs";
    };

    constants format_status width(4) "" {
        FORMAT_6 = 6 "RGB16-565";
        FORMAT_1 = 1 "BITMAP2 (CLUT is required to be used)";
        FORMAT_10 = 10 "RGBx12-4444";
        FORMAT_7 = 7 "ARGB16-1555";
        FORMAT_13 = 13 "RGBA32-8888";
        FORMAT_0 = 0 "BITMAP1 (CLUT is required to be used)";
        FORMAT_2 = 2 "BITMAP4 (CLUT is required to be used)";
        FORMAT_8 = 8 "xRGB24-8888 (32-bit container)";
        FORMAT_9 = 9 "RGB24-888 (24-bit container)";
        FORMAT_11 = 11 "RGBA12-4444";
        FORMAT_4 = 4 "xRGB12-4444";
        FORMAT_5 = 5 "ARGB16-4444";
        FORMAT_15 = 15 "xRGB15-1555";
        FORMAT_12 = 12 "ARGB32-8888";
        FORMAT_3 = 3 "BITMAP8 (CLUT is required to be used)";
        FORMAT_14 = 14 "RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)";
    };
    
    register dispc_gfx_attributes addr(base, 0xA0) "The register configures the graphics attributes. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero) wr: immediate";
        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. (It does not apply to the palette loading OCP requests using INCR burst only)";
        premultiplyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
        antiflicker 1 rw type(antiflicker_status) "Antiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4, 1/2, 1/4)";
        _ 6 mbz;
        selfrefreshauto 1 rw type(sidlemode_status) "Automatic self-refresh mode";
        _ 1 mbz;
        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the graphics window from its own DMA buffer. This bit should be set only after having set the GO bit of the channel and read back a zero in its field.";
        arbitration 1 rw type(sidlemode_status) "Determines the priority of the graphics pipeline. When the graphics pipeline is one of the high priority pipelines. The arbitration wheel gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
        rotation 2 rw type(rotation_status) "Graphics Rotation Flag";
        bufpreload 1 rw type(sidlemode_status) "Graphics Preload Value";
        _ 1 mbz;
        nibblemode 1 rw type(nibblemode_status) "Graphics Nibble Mode (only for 1-, 2- and 4-bpp)";
        channelout 1 rw type(channelout_status) "Graphics Channel Out configuration: LCD, WB or TV. wr: immediate";
        burstsize 2 rw type(burstsize_status) "Graphics DMA Burst Size";
        replicationenable 1 rw type(replicationenable_status) "Graphics Replication Enabled: RGB . ARGB, and RGBA formats are converted into ARGB32-8888 using replication of the MSBs or '0s";
        format 4 rw type(format_status) "Graphics format. It defines the pixel format when fetching the graphics picture into memory.";
        enable 1 rw type(sidlemode_status) "Graphics Enable";
    };
    
    register dispc_gfx_buf_threshold addr(base, 0xA4) "The register configures the graphics buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
        buflowthreshold 16 rw "DMA buffer Low Threshold Number of 128-bits defining the threshold value. The value put is this register should always be greater than zero.";
    };
    
    register dispc_gfx_buf_size_status addr(base, 0xA8) "The register defines the Graphics buffer size" {
        _ 16 mbz;
        bufsize 16 ro "DMA buffer Size in number of 128-bits";
    };
    
    register dispc_gfx_row_inc rw addr(base, 0xAC) "The register configures the number of bytes to increment at the end of the row. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_gfx_pixel_inc addr(base, 0xB0) "The register configures the number of bytes to increment between two pixels. For more information, see, Predecimation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 24 mbz;
        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels.";
    };
    
    register dispc_gfx_table_ba rw addr(base, 0xB8) "The register configures the base address of the palette buffer or the gamma table buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid1_ba_j_0 rw addr(base, 0xBC) "The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid1_ba_j_1 rw addr(base, 0xC0) "The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid1_position addr(base, 0xC4) "The register configures the position of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        posy 11 rw "Y position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0.";
        _ 5 mbz;
        posx 11 rw "X position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1. The first pixel on the left of the display screen has the X-position 0.";
    };
    
    register dispc_vid1_size addr(base, 0xC8) "The register configures the size of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        sizey 11 rw "Number of lines of the video 1 Encoded value (from 1 to 2048) to specify the number of lines of the video window 1. Program to value minus 1.";
        _ 5 mbz;
        sizex 11 rw "Number of pixels of the video window 1 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 1. Program to value minus 1.";
    };

    constants doublestride_status width(1) "" {
        DOUBLESTRIDE_0 = 0 "The CbCr stride value is equal to the Y stride.";
        DOUBLESTRIDE_1 = 1 "The CbCr stride value is double to the Y stride.";
    };

    constants selfrefreshauto_status width(1) "" {
        SELFREFRESHAUTO_0_1 = 0 "The transition from SELFREFRESH 'disabled' to 'enabled' is controlled by SW.";
        SELFREFRESHAUTO_1_1 = 1 "The transition from SELFREFRESH 'disabled' to 'enabled' is controlled only by hardware.";
    };

    constants replicationenable_status1 width(1) "" {
        REPLICATIONENABLE_0_1 = 0 "Disable Video replication logic";
        REPLICATIONENABLE_1_1 = 1 "Enable Video replication logic";
    };

    constants colorconvenable_status width(1) "" {
        COLORCONVENABLE_0 = 0 "Disable Color Space Conversion YUV to RGB";
        COLORCONVENABLE_1 = 1 "Enable Color Space Conversion YUV to RGB";
    };

    constants resizeenable_status width(2) "" {
        RESIZEENABLE_0 = 0 "Disable both horizontal and vertical resize processing";
        RESIZEENABLE_1 = 1 "Enable the horizontal resize processing";
        RESIZEENABLE_3 = 3 "Enable both horizontal and vertical resize processing";
        RESIZEENABLE_2 = 2 "Enable the vertical resize processing";
    };

    constants format_status1 width(4) "" {
        FORMAT_6_1 = 6 "RGB16-565";
        FORMAT_1_1 = 1 "RGB12x-4444";
        FORMAT_10_1 = 10 "YUV2 4:2:2 co-sited";
        FORMAT_7_1 = 7 "ARGB16-1555";
        FORMAT_13_1 = 13 "RGBA32-8888";
        FORMAT_0_1 = 0 "NV12 4:2:0 2 buffers (Y + UV)";
        FORMAT_2_1 = 2 "RGBA12-4444";
        FORMAT_8_1 = 8 "xRGB24-8888 (32-bit container)";
        FORMAT_9_1 = 9 "RGB24-888 (24-bit container)";
        FORMAT_11_1 = 11 "UYVY 4:2:2 co-sited";
        FORMAT_5_1 = 5 "ARGB16-4444";
        FORMAT_15_1 = 15 "xRGB15-1555";
        FORMAT_12_1 = 12 "ARGB32-8888";
        FORMAT_4_1 = 4 "xRGB12-4444";
        FORMAT_14_1 = 14 "RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)";
    };
    
    register dispc_vid1_attributes addr(base, 0xCC) "The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate";
        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
        premultiphyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the video window from its own DMA buffer only.";
        arbitration 1 rw type(sidlemode_status) "Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
        verticaltaps 1 rw type(sidlemode_status) "Video Vertical Resize Tap Number. The vertical polyphase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap compared to 5-tap.";
        dmaoptimization 1 ro "Write 0s for future compatibility. Reads return 0.";
        bufpreload 1 rw type(sidlemode_status) "Video Preload Value";
        _ 1 mbz;
        selfrefreshauto 1 rw type(selfrefreshauto_status) "Automatic self-refresh mode";
        channelout 1 rw type(channelout_status) "Video Channel Out configuration: LCD, WB or TV. wr: immediate";
        burstsize 2 rw type(burstsize_status) "Video DMA Burst Size";
        rotation 2 rw type(rotation_status) "Video Rotation Flag";
        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
        replicationenable 1 rw type(replicationenable_status1) "Replication Enable";
        colorconvenable 1 rw type(colorconvenable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
        vresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
        hresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
        resizeenable 2 rw type(resizeenable_status) "Video Resize Enable";
        format 4 rw type(format_status1) "Video Format. It defines the pixel format when fetching the video 1 picture into memory.";
        enable 1 rw type(tdmparallelmode_status) "Video Enable";
    };
    
    register dispc_vid1_buf_threshold addr(base, 0xD0) "The register configures the video buffer associated with the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        bufhighthreshold 16 rw "Video DMA buffer High Threshold Number of 128-bits defining the threshold value.";
        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
    };
    
    register dispc_vid1_buf_size_status addr(base, 0xD4) "The register defines the Video buffer size for the video pipeline 1." {
        _ 16 mbz;
        bufsize 16 ro "Video 1 DMA buffer Size in number of 128-bits";
    };
    
    register dispc_vid1_row_inc rw addr(base, 0xD8) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid1_pixel_inc addr(base, 0xDC) "The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 24 mbz;
        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. For YUV4:2:0, Max supported value is 128.";
    };
    
    register dispc_vid1_fir addr(base, 0xE0) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_vid1_picture_size addr(base, 0xE4) "The register configures the size of the video picture associated with the video layer 1 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        orgsizey 11 rw "Number of lines of the video picture. Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 2.";
        _ 5 mbz;
        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 2.";
    };
    
    register dispc_vid1_accu_j_0 addr(base, 0xE8) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid1_accu_j_1 addr(base, 0xEC) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid1_fir_coef_h_i_0 addr(base, 0xF0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h_i_1 addr(base, 0xF8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h_i_2 addr(base, 0x100) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h_i_3 addr(base, 0x108) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h_i_4 addr(base, 0x110) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h_i_5 addr(base, 0x118) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h_i_6 addr(base, 0x120) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h_i_7 addr(base, 0x128) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_0 addr(base, 0xF4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_1 addr(base, 0xFC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_2 addr(base, 0x104) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_3 addr(base, 0x10C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_4 addr(base, 0x114) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_5 addr(base, 0x11C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_6 addr(base, 0x124) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv_i_7 addr(base, 0x12C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_conv_coef0 addr(base, 0x130) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        rcr 11 rw "RCr Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        ry 11 rw "RY Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid1_conv_coef1 addr(base, 0x134) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        gy 11 rw "GY Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        rcb 11 rw "RCb Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid1_conv_coef2 addr(base, 0x138) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        gcb 11 rw "GCb Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        gcr 11 rw "GCr Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid1_conv_coef3 addr(base, 0x13C) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        bcr 11 rw "BCr coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        by 11 rw "BY coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid1_conv_coef4 addr(base, 0x140) "The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 21 mbz;
        bcb 11 rw "BCb Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid2_ba_j_0 rw addr(base, 0x14C) "The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid2_ba_j_1 rw addr(base, 0x150) "The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid2_position addr(base, 0x154) "The register configures the position of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        posy 11 rw "Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0.";
        _ 5 mbz;
        posx 11 rw "X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0.";
    };
    
    register dispc_vid2_size addr(base, 0x158) "The register configures the size of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        sizey 11 rw "Number of lines of the video 2 Encoded value (from 1 to 2048) to specify the number of lines of the video window 2. Program to value minus 1.";
        _ 5 mbz;
        sizex 11 rw "Number of pixels of the video window 2 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 2. Program to value minus 1.";
    };
    
    register dispc_vid2_attributes addr(base, 0x15C) "The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero)";
        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
        premultiplyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the video window from its own DMA buffer only.";
        arbitration 1 rw type(tdmparallelmode_status) "Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
        verticaltaps 1 rw type(tdmparallelmode_status) "Video Vertical Resize Tap Number";
        dmaoptimization 1 ro "Write 0s for future compatibility. Reads return 0.";
        bufpreload 1 rw type(tdmparallelmode_status) "Video Preload Value";
        _ 1 mbz;
        selfrefreshauto 1 rw type(selfrefreshauto_status) "Automatic self-refresh mode";
        channelout 1 rw type(channelout_status) "Video Channel Out configuration: LCD, WB or TV. wr: immediate";
        burstsize 2 rw type(burstsize_status) "Video DMA Burst Size";
        rotation 2 rw type(rotation_status) "Video Rotation Flag";
        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
        replicationenable 1 rw type(replicationenable_status1) "Replication Enable";
        colorconvenable 1 rw type(colorconvenable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
        vresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
        hresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
        resizeenable 2 rw type(resizeenable_status) "Video Resize Enable";
        format 4 rw type(format_status1) "Video Format. It defines the pixel format when fetching the video 2 picture into memory.";
        enable 1 rw type(tdmparallelmode_status) "VidEnable";
    };
    
    register dispc_vid2_buf_threshold addr(base, 0x160) "The register configures the DMA buffer associated with the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
    };
    
    register dispc_vid2_buf_size_status addr(base, 0x164) "The register defines the DMA buffer size for the video pipeline 2." {
        _ 16 mbz;
        bufsize 16 ro "DMA buffer size in number of 128 bits";
    };
    
    register dispc_vid2_row_inc rw addr(base, 0x168) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid2_pixel_inc addr(base, 0x16C) "The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 24 mbz;
        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. For YUV4:2:0, Max supported value is 128.";
    };
    
    register dispc_vid2_fir addr(base, 0x170) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_vid2_picture_size addr(base, 0x174) "The register configures the size of the video picture associated with the video layer 2 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        orgsizey 11 rw "Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
        _ 5 mbz;
        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
    };
    
    register dispc_vid2_accu_j_0 addr(base, 0x178) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid2_accu_j_1 addr(base, 0x17C) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid2_fir_coef_h_i_0 addr(base, 0x180) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h_i_1 addr(base, 0x188) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h_i_2 addr(base, 0x190) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h_i_3 addr(base, 0x198) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h_i_4 addr(base, 0x1A0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h_i_5 addr(base, 0x1A8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h_i_6 addr(base, 0x1B0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h_i_7 addr(base, 0x1B8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_0 addr(base, 0x184) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_1 addr(base, 0x18C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_2 addr(base, 0x194) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_3 addr(base, 0x19C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_4 addr(base, 0x1A4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_5 addr(base, 0x1AC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_6 addr(base, 0x1B4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv_i_7 addr(base, 0x1BC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_conv_coef0 addr(base, 0x1C0) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        rcr 11 rw "RCr Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        ry 11 rw "RY Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid2_conv_coef1 addr(base, 0x1C4) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        gy 11 rw "GY Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        rcb 11 rw "RCb Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid2_conv_coef2 addr(base, 0x1C8) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        gcb 11 rw "GCb Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        gcr 11 rw "GCr Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid2_conv_coef3 addr(base, 0x1CC) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        bcr 11 rw "BCr coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        by 11 rw "BY coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid2_conv_coef4 addr(base, 0x1D0) "The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 21 mbz;
        bcb 11 rw "BCb Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_data1_cycle1 addr(base, 0x1D4) "The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of primary LCD" {
        _ 4 mbz;
        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
        _ 3 mbz;
        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
        _ 4 mbz;
        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
        _ 3 mbz;
        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
    };
    
    register dispc_data1_cycle2 addr(base, 0x1D8) "The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of primary LCD" {
        _ 4 mbz;
        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
        _ 3 mbz;
        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
        _ 4 mbz;
        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
        _ 3 mbz;
        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
    };
    
    register dispc_data1_cycle3 addr(base, 0x1DC) "The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of primary LCD" {
        _ 4 mbz;
        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
        _ 3 mbz;
        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
        _ 4 mbz;
        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
        _ 3 mbz;
        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
    };
    
    register dispc_vid1_fir_coef_v_i_0 addr(base, 0x1E0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v_i_1 addr(base, 0x1E4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v_i_2 addr(base, 0x1E8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v_i_3 addr(base, 0x1EC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v_i_4 addr(base, 0x1F0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v_i_5 addr(base, 0x1F4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v_i_6 addr(base, 0x1F8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v_i_7 addr(base, 0x1FC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_0 addr(base, 0x200) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_1 addr(base, 0x204) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_2 addr(base, 0x208) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_3 addr(base, 0x20C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_4 addr(base, 0x210) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_5 addr(base, 0x214) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_6 addr(base, 0x218) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v_i_7 addr(base, 0x21C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_cpr1_coef_r addr(base, 0x220) "The register configures the color phase rotation matrix coefficients for the Red component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
        rr 10 rw "RR Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        rg 10 rw "RG Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        rb 10 rw "RB Coefficient Encoded signed value (from -512 to 511).";
    };
    
    register dispc_cpr1_coef_g addr(base, 0x224) "The register configures the color phase rotation matrix coefficients for the Green component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
        gr 10 rw "GR Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        gg 10 rw "GG Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        gb 10 rw "GB Coefficient Encoded signed value (from -512 to 511).";
    };
    
    register dispc_cpr1_coef_b addr(base, 0x228) "The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" {
        br 10 rw "BR Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        bg 10 rw "BG Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        bb 10 rw "BB Coefficient Encoded signed value (from -512 to 511).";
    };
    
    register dispc_gfx_preload addr(base, 0x22C) "The register configures the graphics DMA buffer Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 20 mbz;
        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
    };
    
    register dispc_vid1_preload addr(base, 0x230) "The register configures the DMA buffer of the video 1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 20 mbz;
        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
    };
    
    register dispc_vid2_preload addr(base, 0x234) "The register configures the DMA buffer of the video 2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 20 mbz;
        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
    };

    constants stallmode_status1 width(1) "" {
        STALLMODE_0_1 = 0 "Normal mode selected";
        STALLMODE_1_1 = 1 "STALL mode selected. The Display Controller sends the data without considering the VSYNC/HSYNC. The LCD output is disabled at the end of the transfer of the frame. The S/W has to re-enable the LCD output in order to generate a new frame.";
    };

    constants stntft_status1 width(1) "" {
        STNTFT_0_1 = 0 "Passive Matrix display operation enabled. Passive Matrix dither logic is enabled.";
        STNTFT_1_1 = 1 "Active or TFT display operation enabled. STN Dither logic and output FIFO bypassed.";
    };
    
    register dispc_control2 addr(base, 0x238) "The control register configures the Display Controller module for the secondary LCD output. Shadow registers are updated during the VFP start period of the secondary LCD, EVSYNC, or when.GOWB is set to 1 by software and the current WB frame is complete (that is, has no more data in the write-back pipeline)." {
        spatialtemporal_ditheringframes 2 rw type(spatialtemporal_ditheringframes_status) "Spatial/Temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD output";
        _ 3 mbz;
        tdmunused_bits 2 rw type(tdmunusedbits_status) "State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output";
        tdmcycle_format 2 rw type(tdmcycleformat_status) "Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output";
        tdmparallel_mode 2 rw type(tdmparallelmode_status) "Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output";
        tdmenable 1 rw type(tdmenable_status) "Enable the multiple cycle format (TDM mode only used for Active Matrix mode with the RFBI enable bit off) for the secondary LCD output wr: VFP start period of secondary LCD output";
        _ 6 mbz;
        tvoverlay_optimization 1 rw type(tdmparallelmode_status) "Overlay Optimization for the TV output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory";
        overlay_optimization 1 rw type(tdmparallelmode_status) "Overlay Optimization for the secondary LCD output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory";
        stallmode 1 rw type(stallmode_status1) "STALL Mode for the secondary LCD output wr: VFP start period of secondary LCD output";
        _ 1 mbz;
        tftdatalines 2 rw type(tftdatalines_status) "Number of lines of the secondary LCD interface wr: VFP start period of secondary LCD output";
        stdither_enable 1 rw type(tdmparallelmode_status) "Spatial Temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD output";
        gowb 1 rw type(tdmparallelmode_status) "GO Command for the write-back output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the write-back output to the memory. wr:immediate";
        golcd 1 rw type(golcd_status) "GO Command for the secondary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the secondary LCD output. wr:immediate";
        m8b 1 rw type(tdmparallelmode_status) "Mono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD output";
        stntft 1 rw type(stntft_status1) "LCD Display type of the secondary LCD wr: VFP start period of secondary LCD output";
        monocolor 1 rw type(tdmparallelmode_status) "Monochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD output";
        _ 1 mbz;
        lcdenable 1 rw type(lcdenable_status) "Enable the secondary LCD output wr:immediate";
    };
    
    register dispc_vid3_accu_j_0 addr(base, 0x300) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid3_accu_j_1 addr(base, 0x304) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid3_ba_j_0 rw addr(base, 0x308) "The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid3_ba_j_1 rw addr(base, 0x30C) "The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid3_fir_coef_h_i_0 addr(base, 0x310) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h_i_1 addr(base, 0x318) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h_i_2 addr(base, 0x320) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h_i_3 addr(base, 0x328) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h_i_4 addr(base, 0x330) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h_i_5 addr(base, 0x338) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h_i_6 addr(base, 0x340) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h_i_7 addr(base, 0x348) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_0 addr(base, 0x314) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_1 addr(base, 0x31C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_2 addr(base, 0x324) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_3 addr(base, 0x32C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_4 addr(base, 0x334) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_5 addr(base, 0x33C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_6 addr(base, 0x344) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv_i_7 addr(base, 0x34C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_0 addr(base, 0x350) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_1 addr(base, 0x354) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_2 addr(base, 0x358) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_3 addr(base, 0x35C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_4 addr(base, 0x360) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_5 addr(base, 0x364) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_6 addr(base, 0x368) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v_i_7 addr(base, 0x36C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };

    constants format_status2 width(4) "" {
        FORMAT_6_3 = 6 "RGB16-565";
        FORMAT_1_3 = 1 "RGB12x-4444";
        FORMAT_10_3 = 10 "YUV2 4:2:2 co-sited";
        FORMAT_7_3 = 7 "ARGB16-1555";
        FORMAT_13_3 = 13 "RGBA32-8888";
        FORMAT_0_3 = 0 "NV12 4:2:0 2 buffers (Y + UV)";
        FORMAT_2_3 = 2 "RGBA12-4444";
        FORMAT_8_3 = 8 "RGB24-8888 (32-bit container)";
        FORMAT_9_3 = 9 "RGB24-888 (24-bit container)";
        FORMAT_11_3 = 11 "UYVY 4:2:2 co-sited";
        FORMAT_5_3 = 5 "ARGB16-4444";
        FORMAT_15_3 = 15 "xRGB15-1555";
        FORMAT_12_3 = 12 "ARGB32-8888";
        FORMAT_4_3 = 4 "xRGB12-4444";
        FORMAT_14_3 = 14 "RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)";
    };
    
    register dispc_vid3_attributes addr(base, 0x370) "The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        channelout2 2 rw type(channelout2_status) "It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate";
        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
        premultiplyalpha 1 rw type(premultiplyalpha_status) "The field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data.";
        zorder 2 rw type(tdmparallelmode_status) "Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.";
        zorderenable 1 rw type(zorderenable_status) "Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled.";
        selfrefresh 1 rw type(selfrefresh_status) "Enables the self refresh of the video window from its own DMA buffer only.";
        arbitration 1 rw type(tdmparallelmode_status) "Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
        verticaltaps 1 rw type(tdmparallelmode_status) "Video Vertical Resize Tap Number";
        dmaoptimization 1 ro "Write 0s for future compatibility. Reads return 0.";
        bufpreload 1 rw type(tdmparallelmode_status) "Video Preload Value";
        _ 1 mbz;
        selfrefreshauto 1 rw type(selfrefreshauto_status) "Automatic self-refresh mode";
        channelout 1 rw type(channelout_status) "Video Channel Out configuration: LCD, WB or TV. wr: immediate";
        burstsize 2 rw type(burstsize_status) "Video DMA Burst Size";
        rotation 2 rw type(rotation_status) "Video Rotation Flag";
        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
        replicationenable 1 rw type(replicationenable_status1) "Replication Enable";
        colorconvenable 1 rw type(colorconvenable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
        vresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
        hresizeconf 1 ro "Write 0s for future compatibility. Reads return 0.";
        resizeenable 2 rw type(resizeenable_status) "Video Resize Enable";
        format 4 rw type(format_status2) "Video Format. It defines the pixel format when fetching the video 3 picture into memory.";
        enable 1 rw type(tdmparallelmode_status) "Video Enable";
    };
    
    register dispc_vid3_conv_coef0 addr(base, 0x374) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        rcr 11 rw "RCr Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        ry 11 rw "RY Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid3_conv_coef1 addr(base, 0x378) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        gy 11 rw "GY Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        rcb 11 rw "RCb Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid3_conv_coef2 addr(base, 0x37C) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        gcb 11 rw "GCb Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        gcr 11 rw "GCr Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid3_conv_coef3 addr(base, 0x380) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        bcr 11 rw "BCr coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        by 11 rw "BY coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid3_conv_coef4 addr(base, 0x384) "The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 21 mbz;
        bcb 11 rw "BCb Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_vid3_buf_size_status addr(base, 0x388) "The register defines the DMA buffer size for the video pipeline 3." {
        _ 16 mbz;
        bufsize 16 ro "DMA buffer Size in number of 128-bits.";
    };
    
    register dispc_vid3_buf_threshold addr(base, 0x38C) "The register configures the DMA buffer associated with the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
    };
    
    register dispc_vid3_fir addr(base, 0x390) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_vid3_picture_size addr(base, 0x394) "The register configures the size of the video picture associated with the video layer 3 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        orgsizey 11 rw "Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
        _ 5 mbz;
        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2.";
    };
    
    register dispc_vid3_pixel_inc addr(base, 0x398) "The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3. For more information, see, Predecimation. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 24 mbz;
        pixelinc 8 rw "Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. For YUV4:2:0, Max supported value is 128.";
    };
    
    register dispc_vid3_position addr(base, 0x39C) "The register configures the position of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        posy 11 rw "Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0.";
        _ 5 mbz;
        posx 11 rw "X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0.";
    };
    
    register dispc_vid3_preload addr(base, 0x3A0) "The register configures the DMA buffer of the video 3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 20 mbz;
        preload 12 rw "DMA buffer preload value Number of 128-bit words defining the preload value.";
    };
    
    register dispc_vid3_row_inc rw addr(base, 0x3A4) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid3_size addr(base, 0x3A8) "The register configures the size of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        sizey 11 rw "Number of lines of the video 3 Encoded value (from 1 to 2048) to specify the number of lines of the video window 3. Program to value minus 1.";
        _ 5 mbz;
        sizex 11 rw "Number of pixels of the video window 3 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 3. Program to value minus 1.";
    };
    
    register dispc_default_color2 addr(base, 0x3AC) "The control register allows to configure the default solid background color for the secondary LCD Shadow register, updated on VFP start period of secondary LCD" {
        _ 8 mbz;
        defaultcolor 24 rw "24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.";
    };
    
    register dispc_trans_color2 addr(base, 0x3B0) "The register sets the transparency color value for the video/graphics overlays for the secondary LCD output. Shadow register, updated on VFP start period of the secondary LCD" {
        _ 8 mbz;
        transcolorkey 24 rw "Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24";
    };
    
    register dispc_cpr2_coef_b addr(base, 0x3B4) "The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
        br 10 rw "BR Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        bg 10 rw "BG Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        bb 10 rw "BB Coefficient Encoded signed value (from -512 to 511).";
    };
    
    register dispc_cpr2_coef_g addr(base, 0x3B8) "The register configures the color phase rotation matrix coefficients for the Green component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
        gr 10 rw "GR Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        gg 10 rw "GG Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        gb 10 rw "GB Coefficient Encoded signed value (from -512 to 511).";
    };
    
    register dispc_cpr2_coef_r addr(base, 0x3BC) "The register configures the color phase rotation matrix coefficients for the Red component. Shadow register, updated on VFP start period of secondary LCD" {
        rr 10 rw "RR Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        rg 10 rw "RG Coefficient Encoded signed value (from -512 to 511).";
        _ 1 mbz;
        rb 10 rw "RB Coefficient Encoded signed value (from -512 to 511).";
    };
    
    register dispc_data2_cycle1 addr(base, 0x3C0) "The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of secondary LCD" {
        _ 4 mbz;
        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
        _ 3 mbz;
        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
        _ 4 mbz;
        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
        _ 3 mbz;
        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
    };
    
    register dispc_data2_cycle2 addr(base, 0x3C4) "The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of secondary LCD" {
        _ 4 mbz;
        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
        _ 3 mbz;
        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
        _ 4 mbz;
        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
        _ 3 mbz;
        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
    };
    
    register dispc_data2_cycle3 addr(base, 0x3C8) "The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of secondary LCD" {
        _ 4 mbz;
        bitalignmentpixel2 4 rw "Bit alignment. Alignment of the bits from pixel 2 on the output interface";
        _ 3 mbz;
        nbbitspixel2 5 rw "Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
        _ 4 mbz;
        bitalignmentpixel1 4 rw "Bit alignment. Alignment of the bits from pixel 1 on the output interface";
        _ 3 mbz;
        nbbitspixel1 5 rw "Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.";
    };

    constants delta_lpp_status2 width(2) "" {
        DELTA_LPP_0_2 = 0 "same size";
        DELTA_LPP_1_2 = 1 "odd size = even size +1";
        DELTA_LPP_2_2 = 2 "Odd size = even size -1";
    };
    
    register dispc_size_lcd2 addr(base, 0x3CC) "The register configures the panel size (horizontal and vertical). It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." {
        _ 5 mbz;
        lpp 11 rw "Lines per panel Encoded value (from 1 to 2048) to specify the number of lines per panel (program to value minus 1).";
        delta_lpp 2 rw type(delta_lpp_status2) "Indicates the delta size value of the odd field compared to the even field";
        _ 3 mbz;
        ppl 11 rw "Pixels per line Encoded value (from 1 to 2048) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid.";
    };
    
    register dispc_timing_h2 addr(base, 0x400) "The register configures the timing logic for the HSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
        hbp 12 rw "Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1).";
        hfp 12 rw "Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1).";
        hsw 8 rw "Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1).";
    };
    
    register dispc_timing_v2 addr(base, 0x404) "The register configures the timing logic for the VSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
        vbp 12 rw "Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display.";
        vfp 12 rw "Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame.";
        vsw 8 rw "Vertical synchronization pulse width In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode. In passive mode, encoded value (from 1 to 256) to specify the number of extra line clock periods (program to value minus 1) to insert after the vertical front porch (VFP) period has elapsed.";
    };
    
    register dispc_pol_freq2 addr(base, 0x408) "The register configures the signal configuration. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
        _ 13 mbz;
        align 1 rw type(align_status) "Defines the alignment between HSYNC and VSYNC assertion.";
        onoff 1 rw type(onoff_status) "HSYNC/VSYNC Pixel clock Control On/Off";
        rf 1 rw type(onoff_status) "Program HSYNC/VSYNC Rise or Fall";
        ieo 1 rw type(tdmparallelmode_status) "Invert output enable";
        ipc 1 rw type(frame_done2_en_status) "Invert pixel clock";
        ihs 1 rw type(tdmparallelmode_status) "Invert HSYNC";
        ivs 1 rw type(tdmparallelmode_status) "Invert VSYNC";
        acbi 4 rw "AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions";
        acb 8 rw "AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display.";
    };
    
    register dispc_divisor2 addr(base, 0x40C) "The register configures the divisors. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" {
        _ 8 mbz;
        lcd 8 rw "Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK. The value 0 is invalid.";
        _ 8 mbz;
        pcd 8 rw "Pixel Clock Divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided byDISPC_DIVISOR2.LCD value. The values 0 is invalid.";
    };
    
    register dispc_wb_accu_j_0 addr(base, 0x500) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_wb_accu_j_1 addr(base, 0x504) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_wb_ba_j_0 rw addr(base, 0x508) "The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" type(uint32);
    
    register dispc_wb_ba_j_1 rw addr(base, 0x50C) "The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" type(uint32);
    
    register dispc_wb_fir_coef_h_i_0 addr(base, 0x510) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h_i_1 addr(base, 0x518) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h_i_2 addr(base, 0x520) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h_i_3 addr(base, 0x528) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h_i_4 addr(base, 0x530) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h_i_5 addr(base, 0x538) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h_i_6 addr(base, 0x540) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h_i_7 addr(base, 0x548) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_0 addr(base, 0x514) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_1 addr(base, 0x51C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_2 addr(base, 0x524) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_3 addr(base, 0x52C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_4 addr(base, 0x534) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_5 addr(base, 0x53C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_6 addr(base, 0x544) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv_i_7 addr(base, 0x54C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_0 addr(base, 0x550) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_1 addr(base, 0x554) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_2 addr(base, 0x558) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_3 addr(base, 0x55C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_4 addr(base, 0x560) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_5 addr(base, 0x564) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_6 addr(base, 0x568) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v_i_7 addr(base, 0x56C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };

    constants idlesize_status width(1) "" {
        IDLESIZE_0 = 0 "The number of idles between requests is defined by IDLENUMBER as number of cycles.";
        IDLESIZE_1 = 1 "The number of idles between requests is defined by IDLENUMBER multiplied by burst size as number of cycles.";
    };

    constants capturemode_status width(3) "" {
        CAPTUREMODE_6 = 6 "Only one out of six frames is captured. The first one is captured then the second one is skipped and so on.";
        CAPTUREMODE_1 = 1 "Only one frame is captured.";
        CAPTUREMODE_7 = 7 "Only one out of seven frames is captured. The first one is captured then the second one is skipped and so on.";
        CAPTUREMODE_0 = 0 "All frames are captures until the write-back channel is disabled or there is no more data generated by the overlay or the pipeline attached to the write-back channel.";
        CAPTUREMODE_2 = 2 "Only one out of two frames is captured. The first one is captured then the second one is skipped and so on.";
        CAPTUREMODE_4 = 4 "Only one out of four frames is captured. The first one is captured then the second one is skipped and so on.";
        CAPTUREMODE_5 = 5 "Only one out of five frames is captured. The first one is captured then the second one is skipped and so on.";
        CAPTUREMODE_3 = 3 "Only one out of three frames is captured. The first one is captured then the second one is skipped and so on.";
    };

    constants channelin_status width(3) "" {
        CHANNELIN_6 = 6 "Video3 pipeline output";
        CHANNELIN_1 = 1 "Secondary LCD output";
        CHANNELIN_0 = 0 "Primary LCD overlay output";
        CHANNELIN_2 = 2 "TV overlay output";
        CHANNELIN_4 = 4 "Video1 pipeline output";
        CHANNELIN_5 = 5 "Video2 pipeline output";
        CHANNELIN_3 = 3 "Graphics pipeline output";
    };

    constants truncationenable_status width(1) "" {
        TRUNCATIONENABLE_0 = 0 "Disable truncation logic";
        TRUNCATIONENABLE_1 = 1 "Enable truncation logic from ARGB32 to the pixel format defined in the field FORMAT.";
    };

    constants resizeenable_status1 width(2) "" {
        RESIZEENABLE_0_3 = 0 "Disable the resize processing";
        RESIZEENABLE_1_3 = 1 "Enable the horizontal resize processing";
        RESIZEENABLE_3_3 = 3 "Enable both horizontal and vertical resize processing";
        RESIZEENABLE_2_3 = 2 "Enable the vertical resize processing";
    };

    constants enable_status width(1) "" {
        ENABLE_0_4 = 0 "Write-back disabled";
        ENABLE_1_4 = 1 "Write-back enabled";
    };
    
    register dispc_wb_attributes addr(base, 0x570) "The register configures the attributes of the viwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        idlenumber 4 rw "Determines the number of idles between requests on the L3 interconnect. It is only used when the write-back pipeline does data transfer from memory to memory. When the output of an overlay is stored in memory through the write-back pipeline in capture mode, the bit field IDLENUMBER is ignored since a timing generator is used to time the transfer. The number of IDLE cycles is IDLENUMBER (from 0 to 15) if IDLESIZE=0. The number of IDLE cycles is IDLENUMBERx8 (from 0 to 120) if IDLESIZE=1 and BURSTSIZE=2. The number of IDLE cycles is IDLENUMBERx4 (from 0 to 60) if IDLESIZE=1 and BURSTSIZE=1. The number of IDLE cycles is IDLENUMBERx2 (from 0 to 30) if IDLESIZE=1 and BURSTSIZE=0.";
        idlesize 1 rw type(idlesize_status) "Determines if the IDLENUMBER corresponds to a number of bursts or singles.";
        capturemode 3 rw type(capturemode_status) "Defines the frame rate capture.";
        arbitration 1 rw type(tdmparallelmode_status) "Determines the priority of the write-back pipeline. The write-back pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.";
        doublestride 1 rw type(doublestride_status) "Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0.";
        verticaltaps 1 rw type(tdmparallelmode_status) "Video Vertical Resize Tap Number";
        _ 1 mbz;
        writebackmode 1 rw "When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel. 0x0: Capture mode (default mode) 0x1: Memory-to-memory mode";
        channelin 3 rw type(channelin_status) "Video Channel In configuration wr: immediate";
        burstsize 2 rw type(burstsize_status) "Write-back DMA Burst Size";
        _ 2 mbz;
        fullrange 1 rw type(doublestride_status) "Color Space Conversion full range setting.";
        truncationenable 1 rw type(truncationenable_status) "It applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32. If the format is one of the YUV supported formats, the bit field is ignored.";
        colorconvenable 1 rw type(colorconv_enable_status) "Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV.";
        bursttype 1 rw type(bursttype_status) "The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine.";
        alphaenable 1 rw "Premultiplied alpha enable Read 0x1: Enabled Read 0x0: Disabled. This bit also disable the logic present in the associated channel out that compute the alpha component sent to the WB pipe. When the WB is configured to copy back one of the output channels (output of overlay), the following configurations are available: 0x1: The WB pipe copies back to memory the premultiplied alpha calculated through the overlay. 0x0: The alpha value is not written back.";
        resizeenable 2 rw type(resizeenable_status1) "Resize Enable";
        format 4 rw type(format_status1) "Write-back Format. It defines the pixel format when storing the write-back picture into memory.";
        enable 1 rw type(enable_status) "Write-back Enable. wr: immediate";
    };
    
    register dispc_wb_conv_coef0 addr(base, 0x574) "The register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24) Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        yg 11 rw "YG Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        yr 11 rw "YR Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_wb_conv_coef1 addr(base, 0x578) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        crr 11 rw "CrR Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        yb 11 rw "YB Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_wb_conv_coef2 addr(base, 0x57C) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        crb 11 rw "CrB Coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        crg 11 rw "CrG Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_wb_conv_coef3 addr(base, 0x580) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        cbg 11 rw "CbG coefficient Encoded signed value (from -1024 to 1023).";
        _ 5 mbz;
        cbr 11 rw "CbR coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_wb_conv_coef4 addr(base, 0x584) "The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 21 mbz;
        cbb 11 rw "CbB Coefficient Encoded signed value (from -1024 to 1023).";
    };
    
    register dispc_wb_buf_size_status addr(base, 0x588) "The register defines the DMA buffer size for the write back pipeline." {
        _ 16 mbz;
        bufsize 16 ro "DMA buffer Size in number of 128-bits.";
    };
    
    register dispc_wb_buf_threshold addr(base, 0x58C) "The register configures the DMA buffer associated with the write-back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        bufhighthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
        buflowthreshold 16 rw "DMA buffer High Threshold Number of 128-bits defining the threshold value.";
    };
    
    register dispc_wb_fir addr(base, 0x590) "The register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_wb_picture_size addr(base, 0x594) "The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        orgsizey 11 rw "Number of lines of the video picture Encoded value (from 1 to 2048) to specify the number of lines of the video picture in memory (program to value minus 1).";
        _ 5 mbz;
        orgsizex 11 rw "Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit.";
    };
    
    register dispc_wb_pixel_inc addr(base, 0x598) "The register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 24 mbz;
        pixelinc 8 rw "Values other than 1 are invalid";
    };
    
    register dispc_wb_row_inc rw addr(base, 0x5A4) "The register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" type(uint32);
    
    register dispc_wb_size addr(base, 0x5A8) "The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline. When the overlay is output on the primary LCD or secondary LCD or TV outputs, the size of the frame is defined in the, , and respectively. Shadow register, updated when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        sizey 11 rw "Number of lines of the Write-back picture Encoded value (from 1 to 2048) to specify the number of lines of the write-back picture. Program to value minus 1.";
        _ 5 mbz;
        sizex 11 rw "Number of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture. Program to value minus 1.";
    };
    
    register dispc_vid1_ba_uv_j_0 rw addr(base, 0x600) "The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid1_ba_uv_j_1 rw addr(base, 0x604) "The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid2_ba_uv_j_0 rw addr(base, 0x608) "The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid2_ba_uv_j_1 rw addr(base, 0x60C) "The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid3_ba_uv_j_0 rw addr(base, 0x610) "The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_vid3_ba_uv_j_1 rw addr(base, 0x614) "The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_wb_ba_uv_j_0 rw addr(base, 0x618) "The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);
    
    register dispc_wb_ba_uv_j_1 rw addr(base, 0x61C) "The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" type(uint32);

    constants bufferhand_check_status1 width(1) "" {
        BUFFERHAND_CHECK_0_1 = 0 "Only the STALL signal (generated by RFBI or DSI2 depending on which IP uses the LCD output) is used regardless of the DMA buffer fullness information in order to provide data to the RFBI or DS2 module.";
        BUFFERHAND_CHECK_1_1 = 1 "The STALL signal (generated by RFBI or DSI2 depending on which IP uses the LCD output) is used in combination with the DMA buffer fullness information in order to provide data to the RFBI or DSI2 module only when it does not generated buffer underflow.";
    };
    
    register dispc_config2 addr(base, 0x620) "The control register configures the Display Controller module for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD or EVSYNC" {
        _ 6 mbz;
        fullrange 1 rw type(fullrange_status) "Color Space Conversion full range setting.";
        colorconv_enable 1 rw type(colorconv_enable_status) "Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1.";
        fidfirst 1 rw type(fidfirst_status) "Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used.";
        outputmode_enable 1 rw type(outputmode_enable_status) "Selects between progressive and interlace mode for the secondary LCD output.";
        _ 5 mbz;
        bufferhand_check 1 rw type(bufferhand_check_status1) "Controls the handcheck between DMA buffer and STALL signal in order to prevent from underflow. The bit shall be set to 0 when the module is not in STALL mode. (secondary LCD output)";
        cpr 1 rw type(cpr_status) "Color Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD output";
        _ 3 mbz;
        tcklcd_selection 1 rw type(tcktv_selection_status) "Transparency Color Key Selection (secondary LCD output) wr: VFP start period of secondary LCD output";
        tcklcdenable 1 rw type(frame_done2_en_status) "Transparency Color Key Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
        _ 1 mbz;
        acbiasgated 1 rw type(acbiasgated_status) "ACBias Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
        vsyncgated 1 rw type(vsyncgated_status) "VSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
        hsyncgated 1 rw type(hsyncgated_status) "HSYNC Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
        pixelclock_gated 1 rw type(pixelclock_gated_status) "Pixel Clock Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
        pixeldata_gated 1 rw type(pixeldatagated_status) "Pixel Data Gated Enabled (secondary LCD output) wr: VFP start period of secondary LCD output";
        _ 3 mbz;
        pixelgated 1 rw type(tdmparallelmode_status) "Pixel Gated Enable (only for Active Matrix) (secondary LCD output) wr: VFP start period of secondary LCD output";
    };

    constants yuvchromare_sampling_status width(1) "" {
        YUVCHROMARE_SAMPLING_0 = 0 "When input is 4:2:2, the missing chrominance samples are calculated by averaging the adjacent samples if. ROTATION=0 only. Other rotation configurations are not supported.";
        YUVCHROMARE_SAMPLING_1 = 1 "For 4:2:2 (or 4:2:0), the missing chrominance samples are calculated by filtering the adjacent samples (5-tap polyphase filter). See, Configuration 2: Video Pipeline. All rotation configurations are supported.";
    };

    constants vc1enable_status width(1) "" {
        VC1ENABLE_0 = 0 "VC-1 range mapping disabled";
        VC1ENABLE_1 = 1 "VC-1 range mapping enabled";
    };
    
    register dispc_vid1_attributes2 addr(base, 0x624) "The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 23 mbz;
        yuvchromare_sampling 1 rw type(yuvchromare_sampling_status) "The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.";
        _ 1 mbz;
        vc1_range_cbcr 3 rw "Defines the VC-1 range value for the CbCr component from 0 to 7.";
        vc1_range_y 3 rw "Defines the VC-1 range value for the Y component from 0 to 7.";
        vc1enable 1 rw type(vc1enable_status) "Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.";
    };
    
    register dispc_vid2_attributes2 addr(base, 0x628) "The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 23 mbz;
        yuvchromare_sampling 1 rw type(yuvchromare_sampling_status) "The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.";
        _ 1 mbz;
        vc1_range_cbcr 3 rw "Defines the VC-1 range value for the CbCr component from 0 to 7.";
        vc1_range_y 3 rw "Defines the VC-1 range value for the Y component from 0 to 7.";
        vc1enable 1 rw type(vc1enable_status) "Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.";
    };
    
    register dispc_vid3_attributes2 addr(base, 0x62C) "The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 23 mbz;
        yuvchromare_sampling 1 rw type(yuvchromare_sampling_status) "The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.";
        _ 1 mbz;
        vc1_range_cbcr 3 rw "Defines the VC-1 range value for the CbCr component from 0 to 7.";
        vc1_range_y 3 rw "Defines the VC-1 range value for the Y component from 0 to 7.";
        vc1enable 1 rw type(vc1enable_status) "Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.";
    };
    
    register dispc_gamma_table0 addr(base, 0x630) "The register configures the look up table used as color look up table for BITMAP formats (1-, 2-, 4, and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output." {
        index 8 wo "Defines the location in the table where the bit field VALUE is stored.";
        value_r 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
        value_g 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
        value_b 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
    };
    
    register dispc_gamma_table1 addr(base, 0x634) "The register configures the gamma table on the secondary LCD output." {
        index 8 wo "Defines the location in the table where the bit field VALUE is stored.";
        value_r 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
        value_g 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
        value_b 8 wo "8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX.";
    };
    
    register dispc_gamma_table2 addr(base, 0x638) "The register configures the gamma table on the TV output." {
        index 1 wo "Setting this bit to 1 resets the internal index counter to zero. Each subsequent access to the register (with the INDEX bit kept at 0) increments the address for the next storage location into the table memory.";
        _ 1 mbz;
        value_r 10 wo "10-bit color component value to store in the table.";
        value_g 10 wo "10-bit color component value to store in the table.";
        value_b 10 wo "10-bit color component value to store in the table.";
    };
    
    register dispc_vid1_fir2 addr(base, 0x63C) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_vid1_accu2_j_0 addr(base, 0x640) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid1_accu2_j_1 addr(base, 0x644) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid1_fir_coef_h2_i_0 addr(base, 0x648) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h2_i_1 addr(base, 0x650) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h2_i_2 addr(base, 0x658) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h2_i_3 addr(base, 0x660) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h2_i_4 addr(base, 0x668) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h2_i_5 addr(base, 0x670) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h2_i_6 addr(base, 0x678) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_h2_i_7 addr(base, 0x680) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_0 addr(base, 0x64C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_1 addr(base, 0x654) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_2 addr(base, 0x65C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_3 addr(base, 0x664) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_4 addr(base, 0x66C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_5 addr(base, 0x674) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_6 addr(base, 0x67C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_hv2_i_7 addr(base, 0x684) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_0 addr(base, 0x688) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_1 addr(base, 0x68C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_2 addr(base, 0x690) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_3 addr(base, 0x694) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_4 addr(base, 0x698) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_5 addr(base, 0x69C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_6 addr(base, 0x6A0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid1_fir_coef_v2_i_7 addr(base, 0x6A4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir2 addr(base, 0x6A8) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_vid2_accu2_j_0 addr(base, 0x6AC) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid2_accu2_j_1 addr(base, 0x6B0) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid2_fir_coef_h2_i_0 addr(base, 0x6B4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h2_i_1 addr(base, 0x6BC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h2_i_2 addr(base, 0x6C4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h2_i_3 addr(base, 0x6CC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h2_i_4 addr(base, 0x6D4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h2_i_5 addr(base, 0x6DC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h2_i_6 addr(base, 0x6E4) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_h2_i_7 addr(base, 0x6EC) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_0 addr(base, 0x6B8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_1 addr(base, 0x6C0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_2 addr(base, 0x6C8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_3 addr(base, 0x6D0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_4 addr(base, 0x6D8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_5 addr(base, 0x6E0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_6 addr(base, 0x6E8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_hv2_i_7 addr(base, 0x6F0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_0 addr(base, 0x6F4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_1 addr(base, 0x6F8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_2 addr(base, 0x6FC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_3 addr(base, 0x700) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_4 addr(base, 0x704) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_5 addr(base, 0x708) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_6 addr(base, 0x70C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid2_fir_coef_v2_i_7 addr(base, 0x710) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir2 addr(base, 0x724) "The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_vid3_accu2_j_0 addr(base, 0x728) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid3_accu2_j_1 addr(base, 0x72C) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_vid3_fir_coef_h2_i_0 addr(base, 0x730) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h2_i_1 addr(base, 0x738) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h2_i_2 addr(base, 0x740) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h2_i_3 addr(base, 0x748) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h2_i_4 addr(base, 0x750) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h2_i_5 addr(base, 0x758) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h2_i_6 addr(base, 0x760) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_h2_i_7 addr(base, 0x768) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_0 addr(base, 0x734) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_1 addr(base, 0x73C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_2 addr(base, 0x744) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_3 addr(base, 0x74C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_4 addr(base, 0x754) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_5 addr(base, 0x75C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_6 addr(base, 0x764) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_hv2_i_7 addr(base, 0x76C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_0 addr(base, 0x770) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_1 addr(base, 0x774) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_2 addr(base, 0x778) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_3 addr(base, 0x77C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_4 addr(base, 0x780) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_5 addr(base, 0x784) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_6 addr(base, 0x788) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_vid3_fir_coef_v2_i_7 addr(base, 0x78C) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir2 addr(base, 0x790) "The register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 3 mbz;
        firvinc 13 rw "Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
        _ 3 mbz;
        firhinc 13 rw "Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.";
    };
    
    register dispc_wb_accu2_j_0 addr(base, 0x794) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_wb_accu2_j_1 addr(base, 0x798) "The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 5 mbz;
        verticalaccu 11 rw "Vertical initialization accu value Encoded value (from -1024 to 1023).";
        _ 5 mbz;
        horizontalaccu 11 rw "Horizontal initialization accu value Encoded value (from -1024 to 1023).";
    };
    
    register dispc_wb_fir_coef_h2_i_0 addr(base, 0x7A0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h2_i_1 addr(base, 0x7A8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h2_i_2 addr(base, 0x7B0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h2_i_3 addr(base, 0x7B8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h2_i_4 addr(base, 0x7C0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h2_i_5 addr(base, 0x7C8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h2_i_6 addr(base, 0x7D0) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_h2_i_7 addr(base, 0x7D8) "The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firhc3 8 rw "Signed coefficient C3 for the horizontal up/down-scaling with the phase n";
        firhc2 8 rw "Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n";
        firhc1 8 rw "Signed coefficient C1 for the horizontal up/down-scaling with the phase n";
        firhc0 8 rw "Signed coefficient C0 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_0 addr(base, 0x7A4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_1 addr(base, 0x7AC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_2 addr(base, 0x7B4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_3 addr(base, 0x7BC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_4 addr(base, 0x7C4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_5 addr(base, 0x7CC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_6 addr(base, 0x7D4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_hv2_i_7 addr(base, 0x7DC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        firvc2 8 rw "Signed coefficient C2 for the vertical up/down-scaling with the phase n";
        firvc1 8 rw "Unsigned coefficient C1 for the vertical up/down-scaling with the phase n";
        firvc0 8 rw "Signed coefficient C0 for the vertical up/down-scaling with the phase n";
        firhc4 8 rw "Signed coefficient C4 for the horizontal up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_0 addr(base, 0x7E0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_1 addr(base, 0x7E4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_2 addr(base, 0x7E8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_3 addr(base, 0x7EC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_4 addr(base, 0x7F0) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_5 addr(base, 0x7F4) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_6 addr(base, 0x7F8) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };
    
    register dispc_wb_fir_coef_v2_i_7 addr(base, 0x7FC) "The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline) when the WB pipeline is directly connected to one of the pipelines (graphics or video), otherwise updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 16 mbz;
        firvc22 8 rw "Signed coefficient C22 for the vertical up/down-scaling with the phase n";
        firvc00 8 rw "Signed coefficient C00 for the vertical up/down-scaling with the phase n";
    };

    constants wb_bottom_buffer_status width(3) "" {
        WB_BOTTOM_BUFFER_0 = 0 "DMA buffer allocated to the graphics pipeline.";
        WB_BOTTOM_BUFFER_1 = 1 "DMA buffer allocated to the video1 pipeline.";
        WB_BOTTOM_BUFFER_2 = 2 "DMA buffer allocated to the vdieo2 pipeline.";
        WB_BOTTOM_BUFFER_3 = 3 "DMA buffer allocated to the vdieo3 pipeline.";
        WB_BOTTOM_BUFFER_4 = 4 "DMA buffer allocated to the write-back pipeline.";
    };
    
    register dispc_global_buffer addr(base, 0x800) "The register configures the DMA buffers allocations to the pipeline (graphics, video1, video2, video3 and write-back). Both TOP and BOTTOM must be allocated to the same pipeline." {
        _ 2 mbz;
        wb_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Write-back DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline.";
        wb_top_buffer 3 rw type(wb_bottom_buffer_status) "Write-back DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to write-back pipeline.";
        vid3_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Video3 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline.";
        vid3_top_buffer 3 rw type(wb_bottom_buffer_status) "Video3 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video3 pipeline.";
        vid2_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Video2 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline.";
        vid2_top_buffer 3 rw type(wb_bottom_buffer_status) "Video2 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video2 pipeline.";
        vid1_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Video1 DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video1 pipeline.";
        vid1_top_buffer 3 rw type(wb_bottom_buffer_status) "Video1 DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to video 1 pipeline.";
        gfx_bottom_buffer 3 rw type(wb_bottom_buffer_status) "Graphics DMA BOTTOM buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline.";
        gfx_top_buffer 3 rw type(wb_bottom_buffer_status) "Graphics DMA TOP buffer (half of the full DMA buffer) allocation to one of the pipelines. By default to graphics pipeline.";
    };

    constants enable_status1 width(1) "" {
        ENABLE_0_5 = 0 ".LCD bit field is used";
        ENABLE_1_5 = 1 ".LCD bit field is used";
    };
    
    register dispc_divisor addr(base, 0x804) "The register configures the divisor value for generating the core functional clock. There is a backward compatibility mode enabled by default in order to use.LCD value instead of .LCD bit field for generating the core functional clock." {
        _ 8 mbz;
        lcd 8 rw "Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock. The value 0 is invalid.";
        _ 15 mbz;
        enable 1 rw type(enable_status1) "When the bit field is set to 1, the bit field LCD is used to generated the core functional clock from the input clock. When the bit field is set to 0, the valueDISPC_DIVISOR1.LCD is used instead.";
    };
    
    register dispc_wb_attributes2 addr(base, 0x810) "The register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of secondary LCD or EVSYNC depending on which overlay output is selected as an input to the WB pipeline" {
        _ 24 mbz;
        wbdelaycount 8 rw "Delays the WB pipe flush after the end of the frame.delay = n x (1/F_clk) n = 0:255";
    };
};