1/*
2 * Copyright (c) 2012, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * a9scu.dev
11 *
12 * DESCRIPTION: Cortex A9 Snoop Control Unit
13 *
14 * This is derived from:
15 *
16 * ARM Cortex-A9 MPCore Technical Reference Manual
17 *
18 */
19 
20device cortex_a9_scu msbfirst ( addr base ) "Cortex A9 SCU" {
21 
22    register control addr(base, 0x0) "SCU Control" {
23	_			25 rsvd;
24	ic_standby		1 rw	"IC standby enable";
25	scu_standby		1 rw	"SCU standby enable";
26	all_device_to_port0	1 rw	"Force all Device to port 0 enable";
27	spec_linefill	        1 rw	"SCU speculative linefills enable";
28	ram_parity		1 rw	"SCU RAMs parity enable";
29	address_filtering	1 rw	"Address Filtering enable";
30	enable		        1 rw	"SCU enable";
31    };
32 	 
33    register config	ro addr(base, 0x4) "SCU Configuration" {
34	_		16;
35	tag_ram_sizes	8 ro	"Tag RAM sizes";
36	cpu_smp		4 ro	"CPUs SMP bits";
37	_		2;
38	numcpus		2 ro	"Number of CPUs present";
39    };
40    
41    constants cpu_status "CPU Status" {
42	normal	 = 0b00		"Normal mode";
43	dormant	 = 0b10		"Dormant mode";
44	off	 = 0b11		"Powered-off mode";
45    };
46    
47    register powerstatus addr(base, 0x8) "SCU CPU Power Status" {
48	_		6;
49	cpu3		2 rw	"Status CPU3";
50	_		6;
51	cpu2		2 rw	"Status CPU2";
52	_		6;	
53	cpu1		2 rw	"Status CPU1";
54	_		6;
55	cpu0		2 rw	"Status CPU0";
56    };
57    
58    register filterstart addr(base, 0x40) "Filtering Start Address" {
59	addr		12 rw	"Filtering Start address";
60	_		20;
61    };
62    
63    register filterend addr(base, 0x44) "Filtering End Address" {
64	addr		12 rw	"Filtering Start address";
65	_		20;
66    };
67 
68 };
69