/*
 * Copyright (c) 2012, ETH Zurich. All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
 */

/*
 * a9scu.dev
 *
 * DESCRIPTION: Cortex A9 Snoop Control Unit
 *
 * This is derived from:
 *
 * ARM Cortex-A9 MPCore Technical Reference Manual
 *
 */
 
device cortex_a9_scu msbfirst ( addr base ) "Cortex A9 SCU" {
 
    register control addr(base, 0x0) "SCU Control" {
	_			25 rsvd;
	ic_standby		1 rw	"IC standby enable";
	scu_standby		1 rw	"SCU standby enable";
	all_device_to_port0	1 rw	"Force all Device to port 0 enable";
	spec_linefill	        1 rw	"SCU speculative linefills enable";
	ram_parity		1 rw	"SCU RAMs parity enable";
	address_filtering	1 rw	"Address Filtering enable";
	enable		        1 rw	"SCU enable";
    };
 	 
    register config	ro addr(base, 0x4) "SCU Configuration" {
	_		16;
	tag_ram_sizes	8 ro	"Tag RAM sizes";
	cpu_smp		4 ro	"CPUs SMP bits";
	_		2;
	numcpus		2 ro	"Number of CPUs present";
    };
    
    constants cpu_status "CPU Status" {
	normal	 = 0b00		"Normal mode";
	dormant	 = 0b10		"Dormant mode";
	off	 = 0b11		"Powered-off mode";
    };
    
    register powerstatus addr(base, 0x8) "SCU CPU Power Status" {
	_		6;
	cpu3		2 rw	"Status CPU3";
	_		6;
	cpu2		2 rw	"Status CPU2";
	_		6;	
	cpu1		2 rw	"Status CPU1";
	_		6;
	cpu0		2 rw	"Status CPU0";
    };
    
    register filterstart addr(base, 0x40) "Filtering Start Address" {
	addr		12 rw	"Filtering Start address";
	_		20;
    };
    
    register filterend addr(base, 0x44) "Filtering End Address" {
	addr		12 rw	"Filtering Start address";
	_		20;
    };
 
 };