1<html lang="en"> 2<head> 3<title>Machine Constraints - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Constraints.html#Constraints" title="Constraints"> 9<link rel="prev" href="Modifiers.html#Modifiers" title="Modifiers"> 10<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 11<!-- 12Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 131998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 142010 Free Software Foundation, Inc. 15 16Permission is granted to copy, distribute and/or modify this document 17under the terms of the GNU Free Documentation License, Version 1.3 or 18any later version published by the Free Software Foundation; with the 19Invariant Sections being ``Funding Free Software'', the Front-Cover 20Texts being (a) (see below), and with the Back-Cover Texts being (b) 21(see below). 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Failing that, use the constraint letters 62that usually have very similar meanings across architectures. The most 63commonly used constraints are ‘<samp><span class="samp">m</span></samp>’ and ‘<samp><span class="samp">r</span></samp>’ (for memory and 64general-purpose registers respectively; see <a href="Simple-Constraints.html#Simple-Constraints">Simple Constraints</a>), and 65‘<samp><span class="samp">I</span></samp>’, usually the letter indicating the most common 66immediate-constant format. 67 68 <p>Each architecture defines additional constraints. These constraints 69are used by the compiler itself for instruction generation, as well as 70for <code>asm</code> statements; therefore, some of the constraints are not 71particularly useful for <code>asm</code>. Here is a summary of some of the 72machine-dependent constraints available on some particular machines; 73it includes both constraints that are useful for <code>asm</code> and 74constraints that aren't. The compiler source file mentioned in the 75table heading for each architecture is the definitive reference for 76the meanings of that architecture's constraints. 77 78 <dl> 79<dt><em>ARM family—</em><samp><span class="file">config/arm/arm.h</span></samp><dd> 80 <dl> 81<dt><code>f</code><dd>Floating-point register 82 83 <br><dt><code>w</code><dd>VFP floating-point register 84 85 <br><dt><code>F</code><dd>One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 86or 10.0 87 88 <br><dt><code>G</code><dd>Floating-point constant that would satisfy the constraint ‘<samp><span class="samp">F</span></samp>’ if it 89were negated 90 91 <br><dt><code>I</code><dd>Integer that is valid as an immediate operand in a data processing 92instruction. That is, an integer in the range 0 to 255 rotated by a 93multiple of 2 94 95 <br><dt><code>J</code><dd>Integer in the range −4095 to 4095 96 97 <br><dt><code>K</code><dd>Integer that satisfies constraint ‘<samp><span class="samp">I</span></samp>’ when inverted (ones complement) 98 99 <br><dt><code>L</code><dd>Integer that satisfies constraint ‘<samp><span class="samp">I</span></samp>’ when negated (twos complement) 100 101 <br><dt><code>M</code><dd>Integer in the range 0 to 32 102 103 <br><dt><code>Q</code><dd>A memory reference where the exact address is in a single register 104(`‘<samp><span class="samp">m</span></samp>’' is preferable for <code>asm</code> statements) 105 106 <br><dt><code>R</code><dd>An item in the constant pool 107 108 <br><dt><code>S</code><dd>A symbol in the text segment of the current file 109 110 <br><dt><code>Uv</code><dd>A memory reference suitable for VFP load/store insns (reg+constant offset) 111 112 <br><dt><code>Uy</code><dd>A memory reference suitable for iWMMXt load/store instructions. 113 114 <br><dt><code>Uq</code><dd>A memory reference suitable for the ARMv4 ldrsb instruction. 115</dl> 116 117 <br><dt><em>AVR family—</em><samp><span class="file">config/avr/constraints.md</span></samp><dd> 118 <dl> 119<dt><code>l</code><dd>Registers from r0 to r15 120 121 <br><dt><code>a</code><dd>Registers from r16 to r23 122 123 <br><dt><code>d</code><dd>Registers from r16 to r31 124 125 <br><dt><code>w</code><dd>Registers from r24 to r31. These registers can be used in ‘<samp><span class="samp">adiw</span></samp>’ command 126 127 <br><dt><code>e</code><dd>Pointer register (r26–r31) 128 129 <br><dt><code>b</code><dd>Base pointer register (r28–r31) 130 131 <br><dt><code>q</code><dd>Stack pointer register (SPH:SPL) 132 133 <br><dt><code>t</code><dd>Temporary register r0 134 135 <br><dt><code>x</code><dd>Register pair X (r27:r26) 136 137 <br><dt><code>y</code><dd>Register pair Y (r29:r28) 138 139 <br><dt><code>z</code><dd>Register pair Z (r31:r30) 140 141 <br><dt><code>I</code><dd>Constant greater than −1, less than 64 142 143 <br><dt><code>J</code><dd>Constant greater than −64, less than 1 144 145 <br><dt><code>K</code><dd>Constant integer 2 146 147 <br><dt><code>L</code><dd>Constant integer 0 148 149 <br><dt><code>M</code><dd>Constant that fits in 8 bits 150 151 <br><dt><code>N</code><dd>Constant integer −1 152 153 <br><dt><code>O</code><dd>Constant integer 8, 16, or 24 154 155 <br><dt><code>P</code><dd>Constant integer 1 156 157 <br><dt><code>G</code><dd>A floating point constant 0.0 158 159 <br><dt><code>R</code><dd>Integer constant in the range −6 <small class="dots">...</small> 5. 160 161 <br><dt><code>Q</code><dd>A memory address based on Y or Z pointer with displacement. 162</dl> 163 164 <br><dt><em>CRX Architecture—</em><samp><span class="file">config/crx/crx.h</span></samp><dd> 165 <dl> 166<dt><code>b</code><dd>Registers from r0 to r14 (registers without stack pointer) 167 168 <br><dt><code>l</code><dd>Register r16 (64-bit accumulator lo register) 169 170 <br><dt><code>h</code><dd>Register r17 (64-bit accumulator hi register) 171 172 <br><dt><code>k</code><dd>Register pair r16-r17. (64-bit accumulator lo-hi pair) 173 174 <br><dt><code>I</code><dd>Constant that fits in 3 bits 175 176 <br><dt><code>J</code><dd>Constant that fits in 4 bits 177 178 <br><dt><code>K</code><dd>Constant that fits in 5 bits 179 180 <br><dt><code>L</code><dd>Constant that is one of −1, 4, −4, 7, 8, 12, 16, 20, 32, 48 181 182 <br><dt><code>G</code><dd>Floating point constant that is legal for store immediate 183</dl> 184 185 <br><dt><em>Hewlett-Packard PA-RISC—</em><samp><span class="file">config/pa/pa.h</span></samp><dd> 186 <dl> 187<dt><code>a</code><dd>General register 1 188 189 <br><dt><code>f</code><dd>Floating point register 190 191 <br><dt><code>q</code><dd>Shift amount register 192 193 <br><dt><code>x</code><dd>Floating point register (deprecated) 194 195 <br><dt><code>y</code><dd>Upper floating point register (32-bit), floating point register (64-bit) 196 197 <br><dt><code>Z</code><dd>Any register 198 199 <br><dt><code>I</code><dd>Signed 11-bit integer constant 200 201 <br><dt><code>J</code><dd>Signed 14-bit integer constant 202 203 <br><dt><code>K</code><dd>Integer constant that can be deposited with a <code>zdepi</code> instruction 204 205 <br><dt><code>L</code><dd>Signed 5-bit integer constant 206 207 <br><dt><code>M</code><dd>Integer constant 0 208 209 <br><dt><code>N</code><dd>Integer constant that can be loaded with a <code>ldil</code> instruction 210 211 <br><dt><code>O</code><dd>Integer constant whose value plus one is a power of 2 212 213 <br><dt><code>P</code><dd>Integer constant that can be used for <code>and</code> operations in <code>depi</code> 214and <code>extru</code> instructions 215 216 <br><dt><code>S</code><dd>Integer constant 31 217 218 <br><dt><code>U</code><dd>Integer constant 63 219 220 <br><dt><code>G</code><dd>Floating-point constant 0.0 221 222 <br><dt><code>A</code><dd>A <code>lo_sum</code> data-linkage-table memory operand 223 224 <br><dt><code>Q</code><dd>A memory operand that can be used as the destination operand of an 225integer store instruction 226 227 <br><dt><code>R</code><dd>A scaled or unscaled indexed memory operand 228 229 <br><dt><code>T</code><dd>A memory operand for floating-point loads and stores 230 231 <br><dt><code>W</code><dd>A register indirect memory operand 232</dl> 233 234 <br><dt><em>picoChip family—</em><samp><span class="file">picochip.h</span></samp><dd> 235 <dl> 236<dt><code>k</code><dd>Stack register. 237 238 <br><dt><code>f</code><dd>Pointer register. A register which can be used to access memory without 239supplying an offset. Any other register can be used to access memory, 240but will need a constant offset. In the case of the offset being zero, 241it is more efficient to use a pointer register, since this reduces code 242size. 243 244 <br><dt><code>t</code><dd>A twin register. A register which may be paired with an adjacent 245register to create a 32-bit register. 246 247 <br><dt><code>a</code><dd>Any absolute memory address (e.g., symbolic constant, symbolic 248constant + offset). 249 250 <br><dt><code>I</code><dd>4-bit signed integer. 251 252 <br><dt><code>J</code><dd>4-bit unsigned integer. 253 254 <br><dt><code>K</code><dd>8-bit signed integer. 255 256 <br><dt><code>M</code><dd>Any constant whose absolute value is no greater than 4-bits. 257 258 <br><dt><code>N</code><dd>10-bit signed integer 259 260 <br><dt><code>O</code><dd>16-bit signed integer. 261 262 </dl> 263 264 <br><dt><em>PowerPC and IBM RS6000—</em><samp><span class="file">config/rs6000/rs6000.h</span></samp><dd> 265 <dl> 266<dt><code>b</code><dd>Address base register 267 268 <br><dt><code>d</code><dd>Floating point register (containing 64-bit value) 269 270 <br><dt><code>f</code><dd>Floating point register (containing 32-bit value) 271 272 <br><dt><code>v</code><dd>Altivec vector register 273 274 <br><dt><code>wd</code><dd>VSX vector register to hold vector double data 275 276 <br><dt><code>wf</code><dd>VSX vector register to hold vector float data 277 278 <br><dt><code>ws</code><dd>VSX vector register to hold scalar float data 279 280 <br><dt><code>wa</code><dd>Any VSX register 281 282 <br><dt><code>h</code><dd>‘<samp><span class="samp">MQ</span></samp>’, ‘<samp><span class="samp">CTR</span></samp>’, or ‘<samp><span class="samp">LINK</span></samp>’ register 283 284 <br><dt><code>q</code><dd>‘<samp><span class="samp">MQ</span></samp>’ register 285 286 <br><dt><code>c</code><dd>‘<samp><span class="samp">CTR</span></samp>’ register 287 288 <br><dt><code>l</code><dd>‘<samp><span class="samp">LINK</span></samp>’ register 289 290 <br><dt><code>x</code><dd>‘<samp><span class="samp">CR</span></samp>’ register (condition register) number 0 291 292 <br><dt><code>y</code><dd>‘<samp><span class="samp">CR</span></samp>’ register (condition register) 293 294 <br><dt><code>z</code><dd>‘<samp><span class="samp">XER[CA]</span></samp>’ carry bit (part of the XER register) 295 296 <br><dt><code>I</code><dd>Signed 16-bit constant 297 298 <br><dt><code>J</code><dd>Unsigned 16-bit constant shifted left 16 bits (use ‘<samp><span class="samp">L</span></samp>’ instead for 299<code>SImode</code> constants) 300 301 <br><dt><code>K</code><dd>Unsigned 16-bit constant 302 303 <br><dt><code>L</code><dd>Signed 16-bit constant shifted left 16 bits 304 305 <br><dt><code>M</code><dd>Constant larger than 31 306 307 <br><dt><code>N</code><dd>Exact power of 2 308 309 <br><dt><code>O</code><dd>Zero 310 311 <br><dt><code>P</code><dd>Constant whose negation is a signed 16-bit constant 312 313 <br><dt><code>G</code><dd>Floating point constant that can be loaded into a register with one 314instruction per word 315 316 <br><dt><code>H</code><dd>Integer/Floating point constant that can be loaded into a register using 317three instructions 318 319 <br><dt><code>m</code><dd>Memory operand. 320Normally, <code>m</code> does not allow addresses that update the base register. 321If ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’ constraint is also used, they are allowed and 322therefore on PowerPC targets in that case it is only safe 323to use ‘<samp><span class="samp">m<></span></samp>’ in an <code>asm</code> statement if that <code>asm</code> statement 324accesses the operand exactly once. The <code>asm</code> statement must also 325use ‘<samp><span class="samp">%U</span><var><opno></var></samp>’ as a placeholder for the “update” flag in the 326corresponding load or store instruction. For example: 327 328 <pre class="smallexample"> asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val)); 329</pre> 330 <p>is correct but: 331 332 <pre class="smallexample"> asm ("st %1,%0" : "=m<>" (mem) : "r" (val)); 333</pre> 334 <p>is not. 335 336 <br><dt><code>es</code><dd>A “stable” memory operand; that is, one which does not include any 337automodification of the base register. This used to be useful when 338‘<samp><span class="samp">m</span></samp>’ allowed automodification of the base register, but as those are now only 339allowed when ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’ is used, ‘<samp><span class="samp">es</span></samp>’ is basically the same 340as ‘<samp><span class="samp">m</span></samp>’ without ‘<samp><span class="samp"><</span></samp>’ and ‘<samp><span class="samp">></span></samp>’. 341 342 <br><dt><code>Q</code><dd>Memory operand that is an offset from a register (it is usually better 343to use ‘<samp><span class="samp">m</span></samp>’ or ‘<samp><span class="samp">es</span></samp>’ in <code>asm</code> statements) 344 345 <br><dt><code>Z</code><dd>Memory operand that is an indexed or indirect from a register (it is 346usually better to use ‘<samp><span class="samp">m</span></samp>’ or ‘<samp><span class="samp">es</span></samp>’ in <code>asm</code> statements) 347 348 <br><dt><code>R</code><dd>AIX TOC entry 349 350 <br><dt><code>a</code><dd>Address operand that is an indexed or indirect from a register (‘<samp><span class="samp">p</span></samp>’ is 351preferable for <code>asm</code> statements) 352 353 <br><dt><code>S</code><dd>Constant suitable as a 64-bit mask operand 354 355 <br><dt><code>T</code><dd>Constant suitable as a 32-bit mask operand 356 357 <br><dt><code>U</code><dd>System V Release 4 small data area reference 358 359 <br><dt><code>t</code><dd>AND masks that can be performed by two rldic{l, r} instructions 360 361 <br><dt><code>W</code><dd>Vector constant that does not require memory 362 363 <br><dt><code>j</code><dd>Vector constant that is all zeros. 364 365 </dl> 366 367 <br><dt><em>Intel 386—</em><samp><span class="file">config/i386/constraints.md</span></samp><dd> 368 <dl> 369<dt><code>R</code><dd>Legacy register—the eight integer registers available on all 370i386 processors (<code>a</code>, <code>b</code>, <code>c</code>, <code>d</code>, 371<code>si</code>, <code>di</code>, <code>bp</code>, <code>sp</code>). 372 373 <br><dt><code>q</code><dd>Any register accessible as <var>r</var><code>l</code>. In 32-bit mode, <code>a</code>, 374<code>b</code>, <code>c</code>, and <code>d</code>; in 64-bit mode, any integer register. 375 376 <br><dt><code>Q</code><dd>Any register accessible as <var>r</var><code>h</code>: <code>a</code>, <code>b</code>, 377<code>c</code>, and <code>d</code>. 378 379 <br><dt><code>a</code><dd>The <code>a</code> register. 380 381 <br><dt><code>b</code><dd>The <code>b</code> register. 382 383 <br><dt><code>c</code><dd>The <code>c</code> register. 384 385 <br><dt><code>d</code><dd>The <code>d</code> register. 386 387 <br><dt><code>S</code><dd>The <code>si</code> register. 388 389 <br><dt><code>D</code><dd>The <code>di</code> register. 390 391 <br><dt><code>A</code><dd>The <code>a</code> and <code>d</code> registers. This class is used for instructions 392that return double word results in the <code>ax:dx</code> register pair. Single 393word values will be allocated either in <code>ax</code> or <code>dx</code>. 394For example on i386 the following implements <code>rdtsc</code>: 395 396 <pre class="smallexample"> unsigned long long rdtsc (void) 397 { 398 unsigned long long tick; 399 __asm__ __volatile__("rdtsc":"=A"(tick)); 400 return tick; 401 } 402</pre> 403 <p>This is not correct on x86_64 as it would allocate tick in either <code>ax</code> 404or <code>dx</code>. You have to use the following variant instead: 405 406 <pre class="smallexample"> unsigned long long rdtsc (void) 407 { 408 unsigned int tickl, tickh; 409 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh)); 410 return ((unsigned long long)tickh << 32)|tickl; 411 } 412</pre> 413 <br><dt><code>f</code><dd>Any 80387 floating-point (stack) register. 414 415 <br><dt><code>t</code><dd>Top of 80387 floating-point stack (<code>%st(0)</code>). 416 417 <br><dt><code>u</code><dd>Second from top of 80387 floating-point stack (<code>%st(1)</code>). 418 419 <br><dt><code>y</code><dd>Any MMX register. 420 421 <br><dt><code>x</code><dd>Any SSE register. 422 423 <br><dt><code>Yz</code><dd>First SSE register (<code>%xmm0</code>). 424 425 <br><dt><code>I</code><dd>Integer constant in the range 0 <small class="dots">...</small> 31, for 32-bit shifts. 426 427 <br><dt><code>J</code><dd>Integer constant in the range 0 <small class="dots">...</small> 63, for 64-bit shifts. 428 429 <br><dt><code>K</code><dd>Signed 8-bit integer constant. 430 431 <br><dt><code>L</code><dd><code>0xFF</code> or <code>0xFFFF</code>, for andsi as a zero-extending move. 432 433 <br><dt><code>M</code><dd>0, 1, 2, or 3 (shifts for the <code>lea</code> instruction). 434 435 <br><dt><code>N</code><dd>Unsigned 8-bit integer constant (for <code>in</code> and <code>out</code> 436instructions). 437 438 <br><dt><code>G</code><dd>Standard 80387 floating point constant. 439 440 <br><dt><code>C</code><dd>Standard SSE floating point constant. 441 442 <br><dt><code>e</code><dd>32-bit signed integer constant, or a symbolic reference known 443to fit that range (for immediate operands in sign-extending x86-64 444instructions). 445 446 <br><dt><code>Z</code><dd>32-bit unsigned integer constant, or a symbolic reference known 447to fit that range (for immediate operands in zero-extending x86-64 448instructions). 449 450 </dl> 451 452 <br><dt><em>Intel IA-64—</em><samp><span class="file">config/ia64/ia64.h</span></samp><dd> 453 <dl> 454<dt><code>a</code><dd>General register <code>r0</code> to <code>r3</code> for <code>addl</code> instruction 455 456 <br><dt><code>b</code><dd>Branch register 457 458 <br><dt><code>c</code><dd>Predicate register (‘<samp><span class="samp">c</span></samp>’ as in “conditional”) 459 460 <br><dt><code>d</code><dd>Application register residing in M-unit 461 462 <br><dt><code>e</code><dd>Application register residing in I-unit 463 464 <br><dt><code>f</code><dd>Floating-point register 465 466 <br><dt><code>m</code><dd>Memory operand. If used together with ‘<samp><span class="samp"><</span></samp>’ or ‘<samp><span class="samp">></span></samp>’, 467the operand can have postincrement and postdecrement which 468require printing with ‘<samp><span class="samp">%Pn</span></samp>’ on IA-64. 469 470 <br><dt><code>G</code><dd>Floating-point constant 0.0 or 1.0 471 472 <br><dt><code>I</code><dd>14-bit signed integer constant 473 474 <br><dt><code>J</code><dd>22-bit signed integer constant 475 476 <br><dt><code>K</code><dd>8-bit signed integer constant for logical instructions 477 478 <br><dt><code>L</code><dd>8-bit adjusted signed integer constant for compare pseudo-ops 479 480 <br><dt><code>M</code><dd>6-bit unsigned integer constant for shift counts 481 482 <br><dt><code>N</code><dd>9-bit signed integer constant for load and store postincrements 483 484 <br><dt><code>O</code><dd>The constant zero 485 486 <br><dt><code>P</code><dd>0 or −1 for <code>dep</code> instruction 487 488 <br><dt><code>Q</code><dd>Non-volatile memory for floating-point loads and stores 489 490 <br><dt><code>R</code><dd>Integer constant in the range 1 to 4 for <code>shladd</code> instruction 491 492 <br><dt><code>S</code><dd>Memory operand except postincrement and postdecrement. This is 493now roughly the same as ‘<samp><span class="samp">m</span></samp>’ when not used together with ‘<samp><span class="samp"><</span></samp>’ 494or ‘<samp><span class="samp">></span></samp>’. 495</dl> 496 497 <br><dt><em>FRV—</em><samp><span class="file">config/frv/frv.h</span></samp><dd> 498 <dl> 499<dt><code>a</code><dd>Register in the class <code>ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>). 500 501 <br><dt><code>b</code><dd>Register in the class <code>EVEN_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>). 502 503 <br><dt><code>c</code><dd>Register in the class <code>CC_REGS</code> (<code>fcc0</code> to <code>fcc3</code> and 504<code>icc0</code> to <code>icc3</code>). 505 506 <br><dt><code>d</code><dd>Register in the class <code>GPR_REGS</code> (<code>gr0</code> to <code>gr63</code>). 507 508 <br><dt><code>e</code><dd>Register in the class <code>EVEN_REGS</code> (<code>gr0</code> to <code>gr63</code>). 509Odd registers are excluded not in the class but through the use of a machine 510mode larger than 4 bytes. 511 512 <br><dt><code>f</code><dd>Register in the class <code>FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>). 513 514 <br><dt><code>h</code><dd>Register in the class <code>FEVEN_REGS</code> (<code>fr0</code> to <code>fr63</code>). 515Odd registers are excluded not in the class but through the use of a machine 516mode larger than 4 bytes. 517 518 <br><dt><code>l</code><dd>Register in the class <code>LR_REG</code> (the <code>lr</code> register). 519 520 <br><dt><code>q</code><dd>Register in the class <code>QUAD_REGS</code> (<code>gr2</code> to <code>gr63</code>). 521Register numbers not divisible by 4 are excluded not in the class but through 522the use of a machine mode larger than 8 bytes. 523 524 <br><dt><code>t</code><dd>Register in the class <code>ICC_REGS</code> (<code>icc0</code> to <code>icc3</code>). 525 526 <br><dt><code>u</code><dd>Register in the class <code>FCC_REGS</code> (<code>fcc0</code> to <code>fcc3</code>). 527 528 <br><dt><code>v</code><dd>Register in the class <code>ICR_REGS</code> (<code>cc4</code> to <code>cc7</code>). 529 530 <br><dt><code>w</code><dd>Register in the class <code>FCR_REGS</code> (<code>cc0</code> to <code>cc3</code>). 531 532 <br><dt><code>x</code><dd>Register in the class <code>QUAD_FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>). 533Register numbers not divisible by 4 are excluded not in the class but through 534the use of a machine mode larger than 8 bytes. 535 536 <br><dt><code>z</code><dd>Register in the class <code>SPR_REGS</code> (<code>lcr</code> and <code>lr</code>). 537 538 <br><dt><code>A</code><dd>Register in the class <code>QUAD_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>). 539 540 <br><dt><code>B</code><dd>Register in the class <code>ACCG_REGS</code> (<code>accg0</code> to <code>accg7</code>). 541 542 <br><dt><code>C</code><dd>Register in the class <code>CR_REGS</code> (<code>cc0</code> to <code>cc7</code>). 543 544 <br><dt><code>G</code><dd>Floating point constant zero 545 546 <br><dt><code>I</code><dd>6-bit signed integer constant 547 548 <br><dt><code>J</code><dd>10-bit signed integer constant 549 550 <br><dt><code>L</code><dd>16-bit signed integer constant 551 552 <br><dt><code>M</code><dd>16-bit unsigned integer constant 553 554 <br><dt><code>N</code><dd>12-bit signed integer constant that is negative—i.e. in the 555range of −2048 to −1 556 557 <br><dt><code>O</code><dd>Constant zero 558 559 <br><dt><code>P</code><dd>12-bit signed integer constant that is greater than zero—i.e. in the 560range of 1 to 2047. 561 562 </dl> 563 564 <br><dt><em>Blackfin family—</em><samp><span class="file">config/bfin/constraints.md</span></samp><dd> 565 <dl> 566<dt><code>a</code><dd>P register 567 568 <br><dt><code>d</code><dd>D register 569 570 <br><dt><code>z</code><dd>A call clobbered P register. 571 572 <br><dt><code>q</code><var>n</var><dd>A single register. If <var>n</var> is in the range 0 to 7, the corresponding D 573register. If it is <code>A</code>, then the register P0. 574 575 <br><dt><code>D</code><dd>Even-numbered D register 576 577 <br><dt><code>W</code><dd>Odd-numbered D register 578 579 <br><dt><code>e</code><dd>Accumulator register. 580 581 <br><dt><code>A</code><dd>Even-numbered accumulator register. 582 583 <br><dt><code>B</code><dd>Odd-numbered accumulator register. 584 585 <br><dt><code>b</code><dd>I register 586 587 <br><dt><code>v</code><dd>B register 588 589 <br><dt><code>f</code><dd>M register 590 591 <br><dt><code>c</code><dd>Registers used for circular buffering, i.e. I, B, or L registers. 592 593 <br><dt><code>C</code><dd>The CC register. 594 595 <br><dt><code>t</code><dd>LT0 or LT1. 596 597 <br><dt><code>k</code><dd>LC0 or LC1. 598 599 <br><dt><code>u</code><dd>LB0 or LB1. 600 601 <br><dt><code>x</code><dd>Any D, P, B, M, I or L register. 602 603 <br><dt><code>y</code><dd>Additional registers typically used only in prologues and epilogues: RETS, 604RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP. 605 606 <br><dt><code>w</code><dd>Any register except accumulators or CC. 607 608 <br><dt><code>Ksh</code><dd>Signed 16 bit integer (in the range −32768 to 32767) 609 610 <br><dt><code>Kuh</code><dd>Unsigned 16 bit integer (in the range 0 to 65535) 611 612 <br><dt><code>Ks7</code><dd>Signed 7 bit integer (in the range −64 to 63) 613 614 <br><dt><code>Ku7</code><dd>Unsigned 7 bit integer (in the range 0 to 127) 615 616 <br><dt><code>Ku5</code><dd>Unsigned 5 bit integer (in the range 0 to 31) 617 618 <br><dt><code>Ks4</code><dd>Signed 4 bit integer (in the range −8 to 7) 619 620 <br><dt><code>Ks3</code><dd>Signed 3 bit integer (in the range −3 to 4) 621 622 <br><dt><code>Ku3</code><dd>Unsigned 3 bit integer (in the range 0 to 7) 623 624 <br><dt><code>P</code><var>n</var><dd>Constant <var>n</var>, where <var>n</var> is a single-digit constant in the range 0 to 4. 625 626 <br><dt><code>PA</code><dd>An integer equal to one of the MACFLAG_XXX constants that is suitable for 627use with either accumulator. 628 629 <br><dt><code>PB</code><dd>An integer equal to one of the MACFLAG_XXX constants that is suitable for 630use only with accumulator A1. 631 632 <br><dt><code>M1</code><dd>Constant 255. 633 634 <br><dt><code>M2</code><dd>Constant 65535. 635 636 <br><dt><code>J</code><dd>An integer constant with exactly a single bit set. 637 638 <br><dt><code>L</code><dd>An integer constant with all bits set except exactly one. 639 640 <br><dt><code>H</code> 641<br><dt><code>Q</code><dd>Any SYMBOL_REF. 642</dl> 643 644 <br><dt><em>M32C—</em><samp><span class="file">config/m32c/m32c.c</span></samp><dd> 645 <dl> 646<dt><code>Rsp</code><dt><code>Rfb</code><dt><code>Rsb</code><dd>‘<samp><span class="samp">$sp</span></samp>’, ‘<samp><span class="samp">$fb</span></samp>’, ‘<samp><span class="samp">$sb</span></samp>’. 647 648 <br><dt><code>Rcr</code><dd>Any control register, when they're 16 bits wide (nothing if control 649registers are 24 bits wide) 650 651 <br><dt><code>Rcl</code><dd>Any control register, when they're 24 bits wide. 652 653 <br><dt><code>R0w</code><dt><code>R1w</code><dt><code>R2w</code><dt><code>R3w</code><dd>$r0, $r1, $r2, $r3. 654 655 <br><dt><code>R02</code><dd>$r0 or $r2, or $r2r0 for 32 bit values. 656 657 <br><dt><code>R13</code><dd>$r1 or $r3, or $r3r1 for 32 bit values. 658 659 <br><dt><code>Rdi</code><dd>A register that can hold a 64 bit value. 660 661 <br><dt><code>Rhl</code><dd>$r0 or $r1 (registers with addressable high/low bytes) 662 663 <br><dt><code>R23</code><dd>$r2 or $r3 664 665 <br><dt><code>Raa</code><dd>Address registers 666 667 <br><dt><code>Raw</code><dd>Address registers when they're 16 bits wide. 668 669 <br><dt><code>Ral</code><dd>Address registers when they're 24 bits wide. 670 671 <br><dt><code>Rqi</code><dd>Registers that can hold QI values. 672 673 <br><dt><code>Rad</code><dd>Registers that can be used with displacements ($a0, $a1, $sb). 674 675 <br><dt><code>Rsi</code><dd>Registers that can hold 32 bit values. 676 677 <br><dt><code>Rhi</code><dd>Registers that can hold 16 bit values. 678 679 <br><dt><code>Rhc</code><dd>Registers chat can hold 16 bit values, including all control 680registers. 681 682 <br><dt><code>Rra</code><dd>$r0 through R1, plus $a0 and $a1. 683 684 <br><dt><code>Rfl</code><dd>The flags register. 685 686 <br><dt><code>Rmm</code><dd>The memory-based pseudo-registers $mem0 through $mem15. 687 688 <br><dt><code>Rpi</code><dd>Registers that can hold pointers (16 bit registers for r8c, m16c; 24 689bit registers for m32cm, m32c). 690 691 <br><dt><code>Rpa</code><dd>Matches multiple registers in a PARALLEL to form a larger register. 692Used to match function return values. 693 694 <br><dt><code>Is3</code><dd>−8 <small class="dots">...</small> 7 695 696 <br><dt><code>IS1</code><dd>−128 <small class="dots">...</small> 127 697 698 <br><dt><code>IS2</code><dd>−32768 <small class="dots">...</small> 32767 699 700 <br><dt><code>IU2</code><dd>0 <small class="dots">...</small> 65535 701 702 <br><dt><code>In4</code><dd>−8 <small class="dots">...</small> −1 or 1 <small class="dots">...</small> 8 703 704 <br><dt><code>In5</code><dd>−16 <small class="dots">...</small> −1 or 1 <small class="dots">...</small> 16 705 706 <br><dt><code>In6</code><dd>−32 <small class="dots">...</small> −1 or 1 <small class="dots">...</small> 32 707 708 <br><dt><code>IM2</code><dd>−65536 <small class="dots">...</small> −1 709 710 <br><dt><code>Ilb</code><dd>An 8 bit value with exactly one bit set. 711 712 <br><dt><code>Ilw</code><dd>A 16 bit value with exactly one bit set. 713 714 <br><dt><code>Sd</code><dd>The common src/dest memory addressing modes. 715 716 <br><dt><code>Sa</code><dd>Memory addressed using $a0 or $a1. 717 718 <br><dt><code>Si</code><dd>Memory addressed with immediate addresses. 719 720 <br><dt><code>Ss</code><dd>Memory addressed using the stack pointer ($sp). 721 722 <br><dt><code>Sf</code><dd>Memory addressed using the frame base register ($fb). 723 724 <br><dt><code>Ss</code><dd>Memory addressed using the small base register ($sb). 725 726 <br><dt><code>S1</code><dd>$r1h 727</dl> 728 729 <br><dt><em>MeP—</em><samp><span class="file">config/mep/constraints.md</span></samp><dd> 730 <dl> 731<dt><code>a</code><dd>The $sp register. 732 733 <br><dt><code>b</code><dd>The $tp register. 734 735 <br><dt><code>c</code><dd>Any control register. 736 737 <br><dt><code>d</code><dd>Either the $hi or the $lo register. 738 739 <br><dt><code>em</code><dd>Coprocessor registers that can be directly loaded ($c0-$c15). 740 741 <br><dt><code>ex</code><dd>Coprocessor registers that can be moved to each other. 742 743 <br><dt><code>er</code><dd>Coprocessor registers that can be moved to core registers. 744 745 <br><dt><code>h</code><dd>The $hi register. 746 747 <br><dt><code>j</code><dd>The $rpc register. 748 749 <br><dt><code>l</code><dd>The $lo register. 750 751 <br><dt><code>t</code><dd>Registers which can be used in $tp-relative addressing. 752 753 <br><dt><code>v</code><dd>The $gp register. 754 755 <br><dt><code>x</code><dd>The coprocessor registers. 756 757 <br><dt><code>y</code><dd>The coprocessor control registers. 758 759 <br><dt><code>z</code><dd>The $0 register. 760 761 <br><dt><code>A</code><dd>User-defined register set A. 762 763 <br><dt><code>B</code><dd>User-defined register set B. 764 765 <br><dt><code>C</code><dd>User-defined register set C. 766 767 <br><dt><code>D</code><dd>User-defined register set D. 768 769 <br><dt><code>I</code><dd>Offsets for $gp-rel addressing. 770 771 <br><dt><code>J</code><dd>Constants that can be used directly with boolean insns. 772 773 <br><dt><code>K</code><dd>Constants that can be moved directly to registers. 774 775 <br><dt><code>L</code><dd>Small constants that can be added to registers. 776 777 <br><dt><code>M</code><dd>Long shift counts. 778 779 <br><dt><code>N</code><dd>Small constants that can be compared to registers. 780 781 <br><dt><code>O</code><dd>Constants that can be loaded into the top half of registers. 782 783 <br><dt><code>S</code><dd>Signed 8-bit immediates. 784 785 <br><dt><code>T</code><dd>Symbols encoded for $tp-rel or $gp-rel addressing. 786 787 <br><dt><code>U</code><dd>Non-constant addresses for loading/saving coprocessor registers. 788 789 <br><dt><code>W</code><dd>The top half of a symbol's value. 790 791 <br><dt><code>Y</code><dd>A register indirect address without offset. 792 793 <br><dt><code>Z</code><dd>Symbolic references to the control bus. 794 795 </dl> 796 797 <br><dt><em>MicroBlaze—</em><samp><span class="file">config/microblaze/constraints.md</span></samp><dd> 798 <dl> 799<dt><code>d</code><dd>A general register (<code>r0</code> to <code>r31</code>). 800 801 <br><dt><code>z</code><dd>A status register (<code>rmsr</code>, <code>$fcc1</code> to <code>$fcc7</code>). 802 803 </dl> 804 805 <br><dt><em>MIPS—</em><samp><span class="file">config/mips/constraints.md</span></samp><dd> 806 <dl> 807<dt><code>d</code><dd>An address register. This is equivalent to <code>r</code> unless 808generating MIPS16 code. 809 810 <br><dt><code>f</code><dd>A floating-point register (if available). 811 812 <br><dt><code>h</code><dd>Formerly the <code>hi</code> register. This constraint is no longer supported. 813 814 <br><dt><code>l</code><dd>The <code>lo</code> register. Use this register to store values that are 815no bigger than a word. 816 817 <br><dt><code>x</code><dd>The concatenated <code>hi</code> and <code>lo</code> registers. Use this register 818to store doubleword values. 819 820 <br><dt><code>c</code><dd>A register suitable for use in an indirect jump. This will always be 821<code>$25</code> for <samp><span class="option">-mabicalls</span></samp>. 822 823 <br><dt><code>v</code><dd>Register <code>$3</code>. Do not use this constraint in new code; 824it is retained only for compatibility with glibc. 825 826 <br><dt><code>y</code><dd>Equivalent to <code>r</code>; retained for backwards compatibility. 827 828 <br><dt><code>z</code><dd>A floating-point condition code register. 829 830 <br><dt><code>I</code><dd>A signed 16-bit constant (for arithmetic instructions). 831 832 <br><dt><code>J</code><dd>Integer zero. 833 834 <br><dt><code>K</code><dd>An unsigned 16-bit constant (for logic instructions). 835 836 <br><dt><code>L</code><dd>A signed 32-bit constant in which the lower 16 bits are zero. 837Such constants can be loaded using <code>lui</code>. 838 839 <br><dt><code>M</code><dd>A constant that cannot be loaded using <code>lui</code>, <code>addiu</code> 840or <code>ori</code>. 841 842 <br><dt><code>N</code><dd>A constant in the range −65535 to −1 (inclusive). 843 844 <br><dt><code>O</code><dd>A signed 15-bit constant. 845 846 <br><dt><code>P</code><dd>A constant in the range 1 to 65535 (inclusive). 847 848 <br><dt><code>G</code><dd>Floating-point zero. 849 850 <br><dt><code>R</code><dd>An address that can be used in a non-macro load or store. 851</dl> 852 853 <br><dt><em>Motorola 680x0—</em><samp><span class="file">config/m68k/constraints.md</span></samp><dd> 854 <dl> 855<dt><code>a</code><dd>Address register 856 857 <br><dt><code>d</code><dd>Data register 858 859 <br><dt><code>f</code><dd>68881 floating-point register, if available 860 861 <br><dt><code>I</code><dd>Integer in the range 1 to 8 862 863 <br><dt><code>J</code><dd>16-bit signed number 864 865 <br><dt><code>K</code><dd>Signed number whose magnitude is greater than 0x80 866 867 <br><dt><code>L</code><dd>Integer in the range −8 to −1 868 869 <br><dt><code>M</code><dd>Signed number whose magnitude is greater than 0x100 870 871 <br><dt><code>N</code><dd>Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate 872 873 <br><dt><code>O</code><dd>16 (for rotate using swap) 874 875 <br><dt><code>P</code><dd>Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate 876 877 <br><dt><code>R</code><dd>Numbers that mov3q can handle 878 879 <br><dt><code>G</code><dd>Floating point constant that is not a 68881 constant 880 881 <br><dt><code>S</code><dd>Operands that satisfy 'm' when -mpcrel is in effect 882 883 <br><dt><code>T</code><dd>Operands that satisfy 's' when -mpcrel is not in effect 884 885 <br><dt><code>Q</code><dd>Address register indirect addressing mode 886 887 <br><dt><code>U</code><dd>Register offset addressing 888 889 <br><dt><code>W</code><dd>const_call_operand 890 891 <br><dt><code>Cs</code><dd>symbol_ref or const 892 893 <br><dt><code>Ci</code><dd>const_int 894 895 <br><dt><code>C0</code><dd>const_int 0 896 897 <br><dt><code>Cj</code><dd>Range of signed numbers that don't fit in 16 bits 898 899 <br><dt><code>Cmvq</code><dd>Integers valid for mvq 900 901 <br><dt><code>Capsw</code><dd>Integers valid for a moveq followed by a swap 902 903 <br><dt><code>Cmvz</code><dd>Integers valid for mvz 904 905 <br><dt><code>Cmvs</code><dd>Integers valid for mvs 906 907 <br><dt><code>Ap</code><dd>push_operand 908 909 <br><dt><code>Ac</code><dd>Non-register operands allowed in clr 910 911 </dl> 912 913 <br><dt><em>Motorola 68HC11 & 68HC12 families—</em><samp><span class="file">config/m68hc11/m68hc11.h</span></samp><dd> 914 <dl> 915<dt><code>a</code><dd>Register `a' 916 917 <br><dt><code>b</code><dd>Register `b' 918 919 <br><dt><code>d</code><dd>Register `d' 920 921 <br><dt><code>q</code><dd>An 8-bit register 922 923 <br><dt><code>t</code><dd>Temporary soft register _.tmp 924 925 <br><dt><code>u</code><dd>A soft register _.d1 to _.d31 926 927 <br><dt><code>w</code><dd>Stack pointer register 928 929 <br><dt><code>x</code><dd>Register `x' 930 931 <br><dt><code>y</code><dd>Register `y' 932 933 <br><dt><code>z</code><dd>Pseudo register `z' (replaced by `x' or `y' at the end) 934 935 <br><dt><code>A</code><dd>An address register: x, y or z 936 937 <br><dt><code>B</code><dd>An address register: x or y 938 939 <br><dt><code>D</code><dd>Register pair (x:d) to form a 32-bit value 940 941 <br><dt><code>L</code><dd>Constants in the range −65536 to 65535 942 943 <br><dt><code>M</code><dd>Constants whose 16-bit low part is zero 944 945 <br><dt><code>N</code><dd>Constant integer 1 or −1 946 947 <br><dt><code>O</code><dd>Constant integer 16 948 949 <br><dt><code>P</code><dd>Constants in the range −8 to 2 950 951 </dl> 952 953 <br><dt><em>Moxie—</em><samp><span class="file">config/moxie/constraints.md</span></samp><dd> 954 <dl> 955<dt><code>A</code><dd>An absolute address 956 957 <br><dt><code>B</code><dd>An offset address 958 959 <br><dt><code>W</code><dd>A register indirect memory operand 960 961 <br><dt><code>I</code><dd>A constant in the range of 0 to 255. 962 963 <br><dt><code>N</code><dd>A constant in the range of 0 to −255. 964 965 </dl> 966 967 <br><dt><em>PDP-11—</em><samp><span class="file">config/pdp11/constraints.md</span></samp><dd> 968 <dl> 969<dt><code>a</code><dd>Floating point registers AC0 through AC3. These can be loaded from/to 970memory with a single instruction. 971 972 <br><dt><code>d</code><dd>Odd numbered general registers (R1, R3, R5). These are used for 97316-bit multiply operations. 974 975 <br><dt><code>f</code><dd>Any of the floating point registers (AC0 through AC5). 976 977 <br><dt><code>G</code><dd>Floating point constant 0. 978 979 <br><dt><code>I</code><dd>An integer constant that fits in 16 bits. 980 981 <br><dt><code>J</code><dd>An integer constant whose low order 16 bits are zero. 982 983 <br><dt><code>K</code><dd>An integer constant that does not meet the constraints for codes 984‘<samp><span class="samp">I</span></samp>’ or ‘<samp><span class="samp">J</span></samp>’. 985 986 <br><dt><code>L</code><dd>The integer constant 1. 987 988 <br><dt><code>M</code><dd>The integer constant −1. 989 990 <br><dt><code>N</code><dd>The integer constant 0. 991 992 <br><dt><code>O</code><dd>Integer constants −4 through −1 and 1 through 4; shifts by these 993amounts are handled as multiple single-bit shifts rather than a single 994variable-length shift. 995 996 <br><dt><code>Q</code><dd>A memory reference which requires an additional word (address or 997offset) after the opcode. 998 999 <br><dt><code>R</code><dd>A memory reference that is encoded within the opcode. 1000 1001 </dl> 1002 1003 <br><dt><em>RX—</em><samp><span class="file">config/rx/constraints.md</span></samp><dd> 1004 <dl> 1005<dt><code>Q</code><dd>An address which does not involve register indirect addressing or 1006pre/post increment/decrement addressing. 1007 1008 <br><dt><code>Symbol</code><dd>A symbol reference. 1009 1010 <br><dt><code>Int08</code><dd>A constant in the range −256 to 255, inclusive. 1011 1012 <br><dt><code>Sint08</code><dd>A constant in the range −128 to 127, inclusive. 1013 1014 <br><dt><code>Sint16</code><dd>A constant in the range −32768 to 32767, inclusive. 1015 1016 <br><dt><code>Sint24</code><dd>A constant in the range −8388608 to 8388607, inclusive. 1017 1018 <br><dt><code>Uint04</code><dd>A constant in the range 0 to 15, inclusive. 1019 1020 </dl> 1021 1022 <br><dt><em>SPARC—</em><samp><span class="file">config/sparc/sparc.h</span></samp><dd> 1023 <dl> 1024<dt><code>f</code><dd>Floating-point register on the SPARC-V8 architecture and 1025lower floating-point register on the SPARC-V9 architecture. 1026 1027 <br><dt><code>e</code><dd>Floating-point register. It is equivalent to ‘<samp><span class="samp">f</span></samp>’ on the 1028SPARC-V8 architecture and contains both lower and upper 1029floating-point registers on the SPARC-V9 architecture. 1030 1031 <br><dt><code>c</code><dd>Floating-point condition code register. 1032 1033 <br><dt><code>d</code><dd>Lower floating-point register. It is only valid on the SPARC-V9 1034architecture when the Visual Instruction Set is available. 1035 1036 <br><dt><code>b</code><dd>Floating-point register. It is only valid on the SPARC-V9 architecture 1037when the Visual Instruction Set is available. 1038 1039 <br><dt><code>h</code><dd>64-bit global or out register for the SPARC-V8+ architecture. 1040 1041 <br><dt><code>D</code><dd>A vector constant 1042 1043 <br><dt><code>I</code><dd>Signed 13-bit constant 1044 1045 <br><dt><code>J</code><dd>Zero 1046 1047 <br><dt><code>K</code><dd>32-bit constant with the low 12 bits clear (a constant that can be 1048loaded with the <code>sethi</code> instruction) 1049 1050 <br><dt><code>L</code><dd>A constant in the range supported by <code>movcc</code> instructions 1051 1052 <br><dt><code>M</code><dd>A constant in the range supported by <code>movrcc</code> instructions 1053 1054 <br><dt><code>N</code><dd>Same as ‘<samp><span class="samp">K</span></samp>’, except that it verifies that bits that are not in the 1055lower 32-bit range are all zero. Must be used instead of ‘<samp><span class="samp">K</span></samp>’ for 1056modes wider than <code>SImode</code> 1057 1058 <br><dt><code>O</code><dd>The constant 4096 1059 1060 <br><dt><code>G</code><dd>Floating-point zero 1061 1062 <br><dt><code>H</code><dd>Signed 13-bit constant, sign-extended to 32 or 64 bits 1063 1064 <br><dt><code>Q</code><dd>Floating-point constant whose integral representation can 1065be moved into an integer register using a single sethi 1066instruction 1067 1068 <br><dt><code>R</code><dd>Floating-point constant whose integral representation can 1069be moved into an integer register using a single mov 1070instruction 1071 1072 <br><dt><code>S</code><dd>Floating-point constant whose integral representation can 1073be moved into an integer register using a high/lo_sum 1074instruction sequence 1075 1076 <br><dt><code>T</code><dd>Memory address aligned to an 8-byte boundary 1077 1078 <br><dt><code>U</code><dd>Even register 1079 1080 <br><dt><code>W</code><dd>Memory address for ‘<samp><span class="samp">e</span></samp>’ constraint registers 1081 1082 <br><dt><code>Y</code><dd>Vector zero 1083 1084 </dl> 1085 1086 <br><dt><em>SPU—</em><samp><span class="file">config/spu/spu.h</span></samp><dd> 1087 <dl> 1088<dt><code>a</code><dd>An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value. 1089 1090 <br><dt><code>c</code><dd>An immediate for and/xor/or instructions. const_int is treated as a 64 bit value. 1091 1092 <br><dt><code>d</code><dd>An immediate for the <code>iohl</code> instruction. const_int is treated as a 64 bit value. 1093 1094 <br><dt><code>f</code><dd>An immediate which can be loaded with <code>fsmbi</code>. 1095 1096 <br><dt><code>A</code><dd>An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value. 1097 1098 <br><dt><code>B</code><dd>An immediate for most arithmetic instructions. const_int is treated as a 32 bit value. 1099 1100 <br><dt><code>C</code><dd>An immediate for and/xor/or instructions. const_int is treated as a 32 bit value. 1101 1102 <br><dt><code>D</code><dd>An immediate for the <code>iohl</code> instruction. const_int is treated as a 32 bit value. 1103 1104 <br><dt><code>I</code><dd>A constant in the range [−64, 63] for shift/rotate instructions. 1105 1106 <br><dt><code>J</code><dd>An unsigned 7-bit constant for conversion/nop/channel instructions. 1107 1108 <br><dt><code>K</code><dd>A signed 10-bit constant for most arithmetic instructions. 1109 1110 <br><dt><code>M</code><dd>A signed 16 bit immediate for <code>stop</code>. 1111 1112 <br><dt><code>N</code><dd>An unsigned 16-bit constant for <code>iohl</code> and <code>fsmbi</code>. 1113 1114 <br><dt><code>O</code><dd>An unsigned 7-bit constant whose 3 least significant bits are 0. 1115 1116 <br><dt><code>P</code><dd>An unsigned 3-bit constant for 16-byte rotates and shifts 1117 1118 <br><dt><code>R</code><dd>Call operand, reg, for indirect calls 1119 1120 <br><dt><code>S</code><dd>Call operand, symbol, for relative calls. 1121 1122 <br><dt><code>T</code><dd>Call operand, const_int, for absolute calls. 1123 1124 <br><dt><code>U</code><dd>An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit. 1125 1126 <br><dt><code>W</code><dd>An immediate for shift and rotate instructions. const_int is treated as a 32 bit value. 1127 1128 <br><dt><code>Y</code><dd>An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit. 1129 1130 <br><dt><code>Z</code><dd>An immediate for the <code>iohl</code> instruction. const_int is sign extended to 128 bit. 1131 1132 </dl> 1133 1134 <br><dt><em>S/390 and zSeries—</em><samp><span class="file">config/s390/s390.h</span></samp><dd> 1135 <dl> 1136<dt><code>a</code><dd>Address register (general purpose register except r0) 1137 1138 <br><dt><code>c</code><dd>Condition code register 1139 1140 <br><dt><code>d</code><dd>Data register (arbitrary general purpose register) 1141 1142 <br><dt><code>f</code><dd>Floating-point register 1143 1144 <br><dt><code>I</code><dd>Unsigned 8-bit constant (0–255) 1145 1146 <br><dt><code>J</code><dd>Unsigned 12-bit constant (0–4095) 1147 1148 <br><dt><code>K</code><dd>Signed 16-bit constant (−32768–32767) 1149 1150 <br><dt><code>L</code><dd>Value appropriate as displacement. 1151 <dl> 1152<dt><code>(0..4095)</code><dd>for short displacement 1153<br><dt><code>(−524288..524287)</code><dd>for long displacement 1154</dl> 1155 1156 <br><dt><code>M</code><dd>Constant integer with a value of 0x7fffffff. 1157 1158 <br><dt><code>N</code><dd>Multiple letter constraint followed by 4 parameter letters. 1159 <dl> 1160<dt><code>0..9:</code><dd>number of the part counting from most to least significant 1161<br><dt><code>H,Q:</code><dd>mode of the part 1162<br><dt><code>D,S,H:</code><dd>mode of the containing operand 1163<br><dt><code>0,F:</code><dd>value of the other parts (F—all bits set) 1164</dl> 1165 The constraint matches if the specified part of a constant 1166has a value different from its other parts. 1167 1168 <br><dt><code>Q</code><dd>Memory reference without index register and with short displacement. 1169 1170 <br><dt><code>R</code><dd>Memory reference with index register and short displacement. 1171 1172 <br><dt><code>S</code><dd>Memory reference without index register but with long displacement. 1173 1174 <br><dt><code>T</code><dd>Memory reference with index register and long displacement. 1175 1176 <br><dt><code>U</code><dd>Pointer with short displacement. 1177 1178 <br><dt><code>W</code><dd>Pointer with long displacement. 1179 1180 <br><dt><code>Y</code><dd>Shift count operand. 1181 1182 </dl> 1183 1184 <br><dt><em>Score family—</em><samp><span class="file">config/score/score.h</span></samp><dd> 1185 <dl> 1186<dt><code>d</code><dd>Registers from r0 to r32. 1187 1188 <br><dt><code>e</code><dd>Registers from r0 to r16. 1189 1190 <br><dt><code>t</code><dd>r8—r11 or r22—r27 registers. 1191 1192 <br><dt><code>h</code><dd>hi register. 1193 1194 <br><dt><code>l</code><dd>lo register. 1195 1196 <br><dt><code>x</code><dd>hi + lo register. 1197 1198 <br><dt><code>q</code><dd>cnt register. 1199 1200 <br><dt><code>y</code><dd>lcb register. 1201 1202 <br><dt><code>z</code><dd>scb register. 1203 1204 <br><dt><code>a</code><dd>cnt + lcb + scb register. 1205 1206 <br><dt><code>c</code><dd>cr0—cr15 register. 1207 1208 <br><dt><code>b</code><dd>cp1 registers. 1209 1210 <br><dt><code>f</code><dd>cp2 registers. 1211 1212 <br><dt><code>i</code><dd>cp3 registers. 1213 1214 <br><dt><code>j</code><dd>cp1 + cp2 + cp3 registers. 1215 1216 <br><dt><code>I</code><dd>High 16-bit constant (32-bit constant with 16 LSBs zero). 1217 1218 <br><dt><code>J</code><dd>Unsigned 5 bit integer (in the range 0 to 31). 1219 1220 <br><dt><code>K</code><dd>Unsigned 16 bit integer (in the range 0 to 65535). 1221 1222 <br><dt><code>L</code><dd>Signed 16 bit integer (in the range −32768 to 32767). 1223 1224 <br><dt><code>M</code><dd>Unsigned 14 bit integer (in the range 0 to 16383). 1225 1226 <br><dt><code>N</code><dd>Signed 14 bit integer (in the range −8192 to 8191). 1227 1228 <br><dt><code>Z</code><dd>Any SYMBOL_REF. 1229</dl> 1230 1231 <br><dt><em>Xstormy16—</em><samp><span class="file">config/stormy16/stormy16.h</span></samp><dd> 1232 <dl> 1233<dt><code>a</code><dd>Register r0. 1234 1235 <br><dt><code>b</code><dd>Register r1. 1236 1237 <br><dt><code>c</code><dd>Register r2. 1238 1239 <br><dt><code>d</code><dd>Register r8. 1240 1241 <br><dt><code>e</code><dd>Registers r0 through r7. 1242 1243 <br><dt><code>t</code><dd>Registers r0 and r1. 1244 1245 <br><dt><code>y</code><dd>The carry register. 1246 1247 <br><dt><code>z</code><dd>Registers r8 and r9. 1248 1249 <br><dt><code>I</code><dd>A constant between 0 and 3 inclusive. 1250 1251 <br><dt><code>J</code><dd>A constant that has exactly one bit set. 1252 1253 <br><dt><code>K</code><dd>A constant that has exactly one bit clear. 1254 1255 <br><dt><code>L</code><dd>A constant between 0 and 255 inclusive. 1256 1257 <br><dt><code>M</code><dd>A constant between −255 and 0 inclusive. 1258 1259 <br><dt><code>N</code><dd>A constant between −3 and 0 inclusive. 1260 1261 <br><dt><code>O</code><dd>A constant between 1 and 4 inclusive. 1262 1263 <br><dt><code>P</code><dd>A constant between −4 and −1 inclusive. 1264 1265 <br><dt><code>Q</code><dd>A memory reference that is a stack push. 1266 1267 <br><dt><code>R</code><dd>A memory reference that is a stack pop. 1268 1269 <br><dt><code>S</code><dd>A memory reference that refers to a constant address of known value. 1270 1271 <br><dt><code>T</code><dd>The register indicated by Rx (not implemented yet). 1272 1273 <br><dt><code>U</code><dd>A constant that is not between 2 and 15 inclusive. 1274 1275 <br><dt><code>Z</code><dd>The constant 0. 1276 1277 </dl> 1278 1279 <br><dt><em>Xtensa—</em><samp><span class="file">config/xtensa/constraints.md</span></samp><dd> 1280 <dl> 1281<dt><code>a</code><dd>General-purpose 32-bit register 1282 1283 <br><dt><code>b</code><dd>One-bit boolean register 1284 1285 <br><dt><code>A</code><dd>MAC16 40-bit accumulator register 1286 1287 <br><dt><code>I</code><dd>Signed 12-bit integer constant, for use in MOVI instructions 1288 1289 <br><dt><code>J</code><dd>Signed 8-bit integer constant, for use in ADDI instructions 1290 1291 <br><dt><code>K</code><dd>Integer constant valid for BccI instructions 1292 1293 <br><dt><code>L</code><dd>Unsigned constant valid for BccUI instructions 1294 1295 </dl> 1296 1297 </dl> 1298 1299<!-- Each of the following nodes are wrapped in separate --> 1300<!-- "@ifset INTERNALS" to work around memory limits for the default --> 1301<!-- configuration in older tetex distributions. Known to not work: --> 1302<!-- tetex-1.0.7, known to work: tetex-2.0.2. --> 1303 </body></html> 1304 1305