6.42.4 Constraints for Particular Machines
Whenever possible, you should use the general-purpose constraint letters
in asm
arguments, since they will convey meaning more readily to
people reading your code. Failing that, use the constraint letters
that usually have very similar meanings across architectures. The most
commonly used constraints are ‘m’ and ‘r’ (for memory and
general-purpose registers respectively; see Simple Constraints), and
‘I’, usually the letter indicating the most common
immediate-constant format.
Each architecture defines additional constraints. These constraints
are used by the compiler itself for instruction generation, as well as
for asm
statements; therefore, some of the constraints are not
particularly useful for asm
. Here is a summary of some of the
machine-dependent constraints available on some particular machines;
it includes both constraints that are useful for asm
and
constraints that aren't. The compiler source file mentioned in the
table heading for each architecture is the definitive reference for
the meanings of that architecture's constraints.
- ARM family—config/arm/arm.h
-
f
- Floating-point register
w
- VFP floating-point register
F
- One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
or 10.0
G
- Floating-point constant that would satisfy the constraint ‘F’ if it
were negated
I
- Integer that is valid as an immediate operand in a data processing
instruction. That is, an integer in the range 0 to 255 rotated by a
multiple of 2
J
- Integer in the range −4095 to 4095
K
- Integer that satisfies constraint ‘I’ when inverted (ones complement)
L
- Integer that satisfies constraint ‘I’ when negated (twos complement)
M
- Integer in the range 0 to 32
Q
- A memory reference where the exact address is in a single register
(`‘m’' is preferable for
asm
statements)
R
- An item in the constant pool
S
- A symbol in the text segment of the current file
Uv
- A memory reference suitable for VFP load/store insns (reg+constant offset)
Uy
- A memory reference suitable for iWMMXt load/store instructions.
Uq
- A memory reference suitable for the ARMv4 ldrsb instruction.
- AVR family—config/avr/constraints.md
-
l
- Registers from r0 to r15
a
- Registers from r16 to r23
d
- Registers from r16 to r31
w
- Registers from r24 to r31. These registers can be used in ‘adiw’ command
e
- Pointer register (r26–r31)
b
- Base pointer register (r28–r31)
q
- Stack pointer register (SPH:SPL)
t
- Temporary register r0
x
- Register pair X (r27:r26)
y
- Register pair Y (r29:r28)
z
- Register pair Z (r31:r30)
I
- Constant greater than −1, less than 64
J
- Constant greater than −64, less than 1
K
- Constant integer 2
L
- Constant integer 0
M
- Constant that fits in 8 bits
N
- Constant integer −1
O
- Constant integer 8, 16, or 24
P
- Constant integer 1
G
- A floating point constant 0.0
R
- Integer constant in the range −6 ... 5.
Q
- A memory address based on Y or Z pointer with displacement.
- CRX Architecture—config/crx/crx.h
-
b
- Registers from r0 to r14 (registers without stack pointer)
l
- Register r16 (64-bit accumulator lo register)
h
- Register r17 (64-bit accumulator hi register)
k
- Register pair r16-r17. (64-bit accumulator lo-hi pair)
I
- Constant that fits in 3 bits
J
- Constant that fits in 4 bits
K
- Constant that fits in 5 bits
L
- Constant that is one of −1, 4, −4, 7, 8, 12, 16, 20, 32, 48
G
- Floating point constant that is legal for store immediate
- Hewlett-Packard PA-RISC—config/pa/pa.h
-
a
- General register 1
f
- Floating point register
q
- Shift amount register
x
- Floating point register (deprecated)
y
- Upper floating point register (32-bit), floating point register (64-bit)
Z
- Any register
I
- Signed 11-bit integer constant
J
- Signed 14-bit integer constant
K
- Integer constant that can be deposited with a
zdepi
instruction
L
- Signed 5-bit integer constant
M
- Integer constant 0
N
- Integer constant that can be loaded with a
ldil
instruction
O
- Integer constant whose value plus one is a power of 2
P
- Integer constant that can be used for
and
operations in depi
and extru
instructions
S
- Integer constant 31
U
- Integer constant 63
G
- Floating-point constant 0.0
A
- A
lo_sum
data-linkage-table memory operand
Q
- A memory operand that can be used as the destination operand of an
integer store instruction
R
- A scaled or unscaled indexed memory operand
T
- A memory operand for floating-point loads and stores
W
- A register indirect memory operand
- picoChip family—picochip.h
-
k
- Stack register.
f
- Pointer register. A register which can be used to access memory without
supplying an offset. Any other register can be used to access memory,
but will need a constant offset. In the case of the offset being zero,
it is more efficient to use a pointer register, since this reduces code
size.
t
- A twin register. A register which may be paired with an adjacent
register to create a 32-bit register.
a
- Any absolute memory address (e.g., symbolic constant, symbolic
constant + offset).
I
- 4-bit signed integer.
J
- 4-bit unsigned integer.
K
- 8-bit signed integer.
M
- Any constant whose absolute value is no greater than 4-bits.
N
- 10-bit signed integer
O
- 16-bit signed integer.
- PowerPC and IBM RS6000—config/rs6000/rs6000.h
-
b
- Address base register
d
- Floating point register (containing 64-bit value)
f
- Floating point register (containing 32-bit value)
v
- Altivec vector register
wd
- VSX vector register to hold vector double data
wf
- VSX vector register to hold vector float data
ws
- VSX vector register to hold scalar float data
wa
- Any VSX register
h
- ‘MQ’, ‘CTR’, or ‘LINK’ register
q
- ‘MQ’ register
c
- ‘CTR’ register
l
- ‘LINK’ register
x
- ‘CR’ register (condition register) number 0
y
- ‘CR’ register (condition register)
z
- ‘XER[CA]’ carry bit (part of the XER register)
I
- Signed 16-bit constant
J
- Unsigned 16-bit constant shifted left 16 bits (use ‘L’ instead for
SImode
constants)
K
- Unsigned 16-bit constant
L
- Signed 16-bit constant shifted left 16 bits
M
- Constant larger than 31
N
- Exact power of 2
O
- Zero
P
- Constant whose negation is a signed 16-bit constant
G
- Floating point constant that can be loaded into a register with one
instruction per word
H
- Integer/Floating point constant that can be loaded into a register using
three instructions
m
- Memory operand.
Normally,
m
does not allow addresses that update the base register.
If ‘<’ or ‘>’ constraint is also used, they are allowed and
therefore on PowerPC targets in that case it is only safe
to use ‘m<>’ in an asm
statement if that asm
statement
accesses the operand exactly once. The asm
statement must also
use ‘%U<opno>’ as a placeholder for the “update” flag in the
corresponding load or store instruction. For example:
asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
is correct but:
asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
is not.
es
- A “stable” memory operand; that is, one which does not include any
automodification of the base register. This used to be useful when
‘m’ allowed automodification of the base register, but as those are now only
allowed when ‘<’ or ‘>’ is used, ‘es’ is basically the same
as ‘m’ without ‘<’ and ‘>’.
Q
- Memory operand that is an offset from a register (it is usually better
to use ‘m’ or ‘es’ in
asm
statements)
Z
- Memory operand that is an indexed or indirect from a register (it is
usually better to use ‘m’ or ‘es’ in
asm
statements)
R
- AIX TOC entry
a
- Address operand that is an indexed or indirect from a register (‘p’ is
preferable for
asm
statements)
S
- Constant suitable as a 64-bit mask operand
T
- Constant suitable as a 32-bit mask operand
U
- System V Release 4 small data area reference
t
- AND masks that can be performed by two rldic{l, r} instructions
W
- Vector constant that does not require memory
j
- Vector constant that is all zeros.
- Intel 386—config/i386/constraints.md
-
R
- Legacy register—the eight integer registers available on all
i386 processors (
a
, b
, c
, d
,
si
, di
, bp
, sp
).
q
- Any register accessible as r
l
. In 32-bit mode, a
,
b
, c
, and d
; in 64-bit mode, any integer register.
Q
- Any register accessible as r
h
: a
, b
,
c
, and d
.
a
- The
a
register.
b
- The
b
register.
c
- The
c
register.
d
- The
d
register.
S
- The
si
register.
D
- The
di
register.
A
- The
a
and d
registers. This class is used for instructions
that return double word results in the ax:dx
register pair. Single
word values will be allocated either in ax
or dx
.
For example on i386 the following implements rdtsc
:
unsigned long long rdtsc (void)
{
unsigned long long tick;
__asm__ __volatile__("rdtsc":"=A"(tick));
return tick;
}
This is not correct on x86_64 as it would allocate tick in either ax
or dx
. You have to use the following variant instead:
unsigned long long rdtsc (void)
{
unsigned int tickl, tickh;
__asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
return ((unsigned long long)tickh << 32)|tickl;
}
f
- Any 80387 floating-point (stack) register.
t
- Top of 80387 floating-point stack (
%st(0)
).
u
- Second from top of 80387 floating-point stack (
%st(1)
).
y
- Any MMX register.
x
- Any SSE register.
Yz
- First SSE register (
%xmm0
).
I
- Integer constant in the range 0 ... 31, for 32-bit shifts.
J
- Integer constant in the range 0 ... 63, for 64-bit shifts.
K
- Signed 8-bit integer constant.
L
0xFF
or 0xFFFF
, for andsi as a zero-extending move.
M
- 0, 1, 2, or 3 (shifts for the
lea
instruction).
N
- Unsigned 8-bit integer constant (for
in
and out
instructions).
G
- Standard 80387 floating point constant.
C
- Standard SSE floating point constant.
e
- 32-bit signed integer constant, or a symbolic reference known
to fit that range (for immediate operands in sign-extending x86-64
instructions).
Z
- 32-bit unsigned integer constant, or a symbolic reference known
to fit that range (for immediate operands in zero-extending x86-64
instructions).
- Intel IA-64—config/ia64/ia64.h
-
a
- General register
r0
to r3
for addl
instruction
b
- Branch register
c
- Predicate register (‘c’ as in “conditional”)
d
- Application register residing in M-unit
e
- Application register residing in I-unit
f
- Floating-point register
m
- Memory operand. If used together with ‘<’ or ‘>’,
the operand can have postincrement and postdecrement which
require printing with ‘%Pn’ on IA-64.
G
- Floating-point constant 0.0 or 1.0
I
- 14-bit signed integer constant
J
- 22-bit signed integer constant
K
- 8-bit signed integer constant for logical instructions
L
- 8-bit adjusted signed integer constant for compare pseudo-ops
M
- 6-bit unsigned integer constant for shift counts
N
- 9-bit signed integer constant for load and store postincrements
O
- The constant zero
P
- 0 or −1 for
dep
instruction
Q
- Non-volatile memory for floating-point loads and stores
R
- Integer constant in the range 1 to 4 for
shladd
instruction
S
- Memory operand except postincrement and postdecrement. This is
now roughly the same as ‘m’ when not used together with ‘<’
or ‘>’.
- FRV—config/frv/frv.h
-
a
- Register in the class
ACC_REGS
(acc0
to acc7
).
b
- Register in the class
EVEN_ACC_REGS
(acc0
to acc7
).
c
- Register in the class
CC_REGS
(fcc0
to fcc3
and
icc0
to icc3
).
d
- Register in the class
GPR_REGS
(gr0
to gr63
).
e
- Register in the class
EVEN_REGS
(gr0
to gr63
).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
f
- Register in the class
FPR_REGS
(fr0
to fr63
).
h
- Register in the class
FEVEN_REGS
(fr0
to fr63
).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
l
- Register in the class
LR_REG
(the lr
register).
q
- Register in the class
QUAD_REGS
(gr2
to gr63
).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
t
- Register in the class
ICC_REGS
(icc0
to icc3
).
u
- Register in the class
FCC_REGS
(fcc0
to fcc3
).
v
- Register in the class
ICR_REGS
(cc4
to cc7
).
w
- Register in the class
FCR_REGS
(cc0
to cc3
).
x
- Register in the class
QUAD_FPR_REGS
(fr0
to fr63
).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
z
- Register in the class
SPR_REGS
(lcr
and lr
).
A
- Register in the class
QUAD_ACC_REGS
(acc0
to acc7
).
B
- Register in the class
ACCG_REGS
(accg0
to accg7
).
C
- Register in the class
CR_REGS
(cc0
to cc7
).
G
- Floating point constant zero
I
- 6-bit signed integer constant
J
- 10-bit signed integer constant
L
- 16-bit signed integer constant
M
- 16-bit unsigned integer constant
N
- 12-bit signed integer constant that is negative—i.e. in the
range of −2048 to −1
O
- Constant zero
P
- 12-bit signed integer constant that is greater than zero—i.e. in the
range of 1 to 2047.
- Blackfin family—config/bfin/constraints.md
-
a
- P register
d
- D register
z
- A call clobbered P register.
q
n- A single register. If n is in the range 0 to 7, the corresponding D
register. If it is
A
, then the register P0.
D
- Even-numbered D register
W
- Odd-numbered D register
e
- Accumulator register.
A
- Even-numbered accumulator register.
B
- Odd-numbered accumulator register.
b
- I register
v
- B register
f
- M register
c
- Registers used for circular buffering, i.e. I, B, or L registers.
C
- The CC register.
t
- LT0 or LT1.
k
- LC0 or LC1.
u
- LB0 or LB1.
x
- Any D, P, B, M, I or L register.
y
- Additional registers typically used only in prologues and epilogues: RETS,
RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
w
- Any register except accumulators or CC.
Ksh
- Signed 16 bit integer (in the range −32768 to 32767)
Kuh
- Unsigned 16 bit integer (in the range 0 to 65535)
Ks7
- Signed 7 bit integer (in the range −64 to 63)
Ku7
- Unsigned 7 bit integer (in the range 0 to 127)
Ku5
- Unsigned 5 bit integer (in the range 0 to 31)
Ks4
- Signed 4 bit integer (in the range −8 to 7)
Ks3
- Signed 3 bit integer (in the range −3 to 4)
Ku3
- Unsigned 3 bit integer (in the range 0 to 7)
P
n- Constant n, where n is a single-digit constant in the range 0 to 4.
PA
- An integer equal to one of the MACFLAG_XXX constants that is suitable for
use with either accumulator.
PB
- An integer equal to one of the MACFLAG_XXX constants that is suitable for
use only with accumulator A1.
M1
- Constant 255.
M2
- Constant 65535.
J
- An integer constant with exactly a single bit set.
L
- An integer constant with all bits set except exactly one.
H
Q
- Any SYMBOL_REF.
- M32C—config/m32c/m32c.c
-
Rsp
Rfb
Rsb
- ‘$sp’, ‘$fb’, ‘$sb’.
Rcr
- Any control register, when they're 16 bits wide (nothing if control
registers are 24 bits wide)
Rcl
- Any control register, when they're 24 bits wide.
R0w
R1w
R2w
R3w
- $r0, $r1, $r2, $r3.
R02
- $r0 or $r2, or $r2r0 for 32 bit values.
R13
- $r1 or $r3, or $r3r1 for 32 bit values.
Rdi
- A register that can hold a 64 bit value.
Rhl
- $r0 or $r1 (registers with addressable high/low bytes)
R23
- $r2 or $r3
Raa
- Address registers
Raw
- Address registers when they're 16 bits wide.
Ral
- Address registers when they're 24 bits wide.
Rqi
- Registers that can hold QI values.
Rad
- Registers that can be used with displacements ($a0, $a1, $sb).
Rsi
- Registers that can hold 32 bit values.
Rhi
- Registers that can hold 16 bit values.
Rhc
- Registers chat can hold 16 bit values, including all control
registers.
Rra
- $r0 through R1, plus $a0 and $a1.
Rfl
- The flags register.
Rmm
- The memory-based pseudo-registers $mem0 through $mem15.
Rpi
- Registers that can hold pointers (16 bit registers for r8c, m16c; 24
bit registers for m32cm, m32c).
Rpa
- Matches multiple registers in a PARALLEL to form a larger register.
Used to match function return values.
Is3
- −8 ... 7
IS1
- −128 ... 127
IS2
- −32768 ... 32767
IU2
- 0 ... 65535
In4
- −8 ... −1 or 1 ... 8
In5
- −16 ... −1 or 1 ... 16
In6
- −32 ... −1 or 1 ... 32
IM2
- −65536 ... −1
Ilb
- An 8 bit value with exactly one bit set.
Ilw
- A 16 bit value with exactly one bit set.
Sd
- The common src/dest memory addressing modes.
Sa
- Memory addressed using $a0 or $a1.
Si
- Memory addressed with immediate addresses.
Ss
- Memory addressed using the stack pointer ($sp).
Sf
- Memory addressed using the frame base register ($fb).
Ss
- Memory addressed using the small base register ($sb).
S1
- $r1h
- MeP—config/mep/constraints.md
-
a
- The $sp register.
b
- The $tp register.
c
- Any control register.
d
- Either the $hi or the $lo register.
em
- Coprocessor registers that can be directly loaded ($c0-$c15).
ex
- Coprocessor registers that can be moved to each other.
er
- Coprocessor registers that can be moved to core registers.
h
- The $hi register.
j
- The $rpc register.
l
- The $lo register.
t
- Registers which can be used in $tp-relative addressing.
v
- The $gp register.
x
- The coprocessor registers.
y
- The coprocessor control registers.
z
- The $0 register.
A
- User-defined register set A.
B
- User-defined register set B.
C
- User-defined register set C.
D
- User-defined register set D.
I
- Offsets for $gp-rel addressing.
J
- Constants that can be used directly with boolean insns.
K
- Constants that can be moved directly to registers.
L
- Small constants that can be added to registers.
M
- Long shift counts.
N
- Small constants that can be compared to registers.
O
- Constants that can be loaded into the top half of registers.
S
- Signed 8-bit immediates.
T
- Symbols encoded for $tp-rel or $gp-rel addressing.
U
- Non-constant addresses for loading/saving coprocessor registers.
W
- The top half of a symbol's value.
Y
- A register indirect address without offset.
Z
- Symbolic references to the control bus.
- MicroBlaze—config/microblaze/constraints.md
-
d
- A general register (
r0
to r31
).
z
- A status register (
rmsr
, $fcc1
to $fcc7
).
- MIPS—config/mips/constraints.md
-
d
- An address register. This is equivalent to
r
unless
generating MIPS16 code.
f
- A floating-point register (if available).
h
- Formerly the
hi
register. This constraint is no longer supported.
l
- The
lo
register. Use this register to store values that are
no bigger than a word.
x
- The concatenated
hi
and lo
registers. Use this register
to store doubleword values.
c
- A register suitable for use in an indirect jump. This will always be
$25
for -mabicalls.
v
- Register
$3
. Do not use this constraint in new code;
it is retained only for compatibility with glibc.
y
- Equivalent to
r
; retained for backwards compatibility.
z
- A floating-point condition code register.
I
- A signed 16-bit constant (for arithmetic instructions).
J
- Integer zero.
K
- An unsigned 16-bit constant (for logic instructions).
L
- A signed 32-bit constant in which the lower 16 bits are zero.
Such constants can be loaded using
lui
.
M
- A constant that cannot be loaded using
lui
, addiu
or ori
.
N
- A constant in the range −65535 to −1 (inclusive).
O
- A signed 15-bit constant.
P
- A constant in the range 1 to 65535 (inclusive).
G
- Floating-point zero.
R
- An address that can be used in a non-macro load or store.
- Motorola 680x0—config/m68k/constraints.md
-
a
- Address register
d
- Data register
f
- 68881 floating-point register, if available
I
- Integer in the range 1 to 8
J
- 16-bit signed number
K
- Signed number whose magnitude is greater than 0x80
L
- Integer in the range −8 to −1
M
- Signed number whose magnitude is greater than 0x100
N
- Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
O
- 16 (for rotate using swap)
P
- Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
R
- Numbers that mov3q can handle
G
- Floating point constant that is not a 68881 constant
S
- Operands that satisfy 'm' when -mpcrel is in effect
T
- Operands that satisfy 's' when -mpcrel is not in effect
Q
- Address register indirect addressing mode
U
- Register offset addressing
W
- const_call_operand
Cs
- symbol_ref or const
Ci
- const_int
C0
- const_int 0
Cj
- Range of signed numbers that don't fit in 16 bits
Cmvq
- Integers valid for mvq
Capsw
- Integers valid for a moveq followed by a swap
Cmvz
- Integers valid for mvz
Cmvs
- Integers valid for mvs
Ap
- push_operand
Ac
- Non-register operands allowed in clr
- Motorola 68HC11 & 68HC12 families—config/m68hc11/m68hc11.h
-
a
- Register `a'
b
- Register `b'
d
- Register `d'
q
- An 8-bit register
t
- Temporary soft register _.tmp
u
- A soft register _.d1 to _.d31
w
- Stack pointer register
x
- Register `x'
y
- Register `y'
z
- Pseudo register `z' (replaced by `x' or `y' at the end)
A
- An address register: x, y or z
B
- An address register: x or y
D
- Register pair (x:d) to form a 32-bit value
L
- Constants in the range −65536 to 65535
M
- Constants whose 16-bit low part is zero
N
- Constant integer 1 or −1
O
- Constant integer 16
P
- Constants in the range −8 to 2
- Moxie—config/moxie/constraints.md
-
A
- An absolute address
B
- An offset address
W
- A register indirect memory operand
I
- A constant in the range of 0 to 255.
N
- A constant in the range of 0 to −255.
- PDP-11—config/pdp11/constraints.md
-
a
- Floating point registers AC0 through AC3. These can be loaded from/to
memory with a single instruction.
d
- Odd numbered general registers (R1, R3, R5). These are used for
16-bit multiply operations.
f
- Any of the floating point registers (AC0 through AC5).
G
- Floating point constant 0.
I
- An integer constant that fits in 16 bits.
J
- An integer constant whose low order 16 bits are zero.
K
- An integer constant that does not meet the constraints for codes
‘I’ or ‘J’.
L
- The integer constant 1.
M
- The integer constant −1.
N
- The integer constant 0.
O
- Integer constants −4 through −1 and 1 through 4; shifts by these
amounts are handled as multiple single-bit shifts rather than a single
variable-length shift.
Q
- A memory reference which requires an additional word (address or
offset) after the opcode.
R
- A memory reference that is encoded within the opcode.
- RX—config/rx/constraints.md
-
Q
- An address which does not involve register indirect addressing or
pre/post increment/decrement addressing.
Symbol
- A symbol reference.
Int08
- A constant in the range −256 to 255, inclusive.
Sint08
- A constant in the range −128 to 127, inclusive.
Sint16
- A constant in the range −32768 to 32767, inclusive.
Sint24
- A constant in the range −8388608 to 8388607, inclusive.
Uint04
- A constant in the range 0 to 15, inclusive.
- SPARC—config/sparc/sparc.h
-
f
- Floating-point register on the SPARC-V8 architecture and
lower floating-point register on the SPARC-V9 architecture.
e
- Floating-point register. It is equivalent to ‘f’ on the
SPARC-V8 architecture and contains both lower and upper
floating-point registers on the SPARC-V9 architecture.
c
- Floating-point condition code register.
d
- Lower floating-point register. It is only valid on the SPARC-V9
architecture when the Visual Instruction Set is available.
b
- Floating-point register. It is only valid on the SPARC-V9 architecture
when the Visual Instruction Set is available.
h
- 64-bit global or out register for the SPARC-V8+ architecture.
D
- A vector constant
I
- Signed 13-bit constant
J
- Zero
K
- 32-bit constant with the low 12 bits clear (a constant that can be
loaded with the
sethi
instruction)
L
- A constant in the range supported by
movcc
instructions
M
- A constant in the range supported by
movrcc
instructions
N
- Same as ‘K’, except that it verifies that bits that are not in the
lower 32-bit range are all zero. Must be used instead of ‘K’ for
modes wider than
SImode
O
- The constant 4096
G
- Floating-point zero
H
- Signed 13-bit constant, sign-extended to 32 or 64 bits
Q
- Floating-point constant whose integral representation can
be moved into an integer register using a single sethi
instruction
R
- Floating-point constant whose integral representation can
be moved into an integer register using a single mov
instruction
S
- Floating-point constant whose integral representation can
be moved into an integer register using a high/lo_sum
instruction sequence
T
- Memory address aligned to an 8-byte boundary
U
- Even register
W
- Memory address for ‘e’ constraint registers
Y
- Vector zero
- SPU—config/spu/spu.h
-
a
- An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
c
- An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
d
- An immediate for the
iohl
instruction. const_int is treated as a 64 bit value.
f
- An immediate which can be loaded with
fsmbi
.
A
- An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
B
- An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
C
- An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
D
- An immediate for the
iohl
instruction. const_int is treated as a 32 bit value.
I
- A constant in the range [−64, 63] for shift/rotate instructions.
J
- An unsigned 7-bit constant for conversion/nop/channel instructions.
K
- A signed 10-bit constant for most arithmetic instructions.
M
- A signed 16 bit immediate for
stop
.
N
- An unsigned 16-bit constant for
iohl
and fsmbi
.
O
- An unsigned 7-bit constant whose 3 least significant bits are 0.
P
- An unsigned 3-bit constant for 16-byte rotates and shifts
R
- Call operand, reg, for indirect calls
S
- Call operand, symbol, for relative calls.
T
- Call operand, const_int, for absolute calls.
U
- An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
W
- An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
Y
- An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
Z
- An immediate for the
iohl
instruction. const_int is sign extended to 128 bit.
- S/390 and zSeries—config/s390/s390.h
-
a
- Address register (general purpose register except r0)
c
- Condition code register
d
- Data register (arbitrary general purpose register)
f
- Floating-point register
I
- Unsigned 8-bit constant (0–255)
J
- Unsigned 12-bit constant (0–4095)
K
- Signed 16-bit constant (−32768–32767)
L
- Value appropriate as displacement.
(0..4095)
- for short displacement
(−524288..524287)
- for long displacement
M
- Constant integer with a value of 0x7fffffff.
N
- Multiple letter constraint followed by 4 parameter letters.
0..9:
- number of the part counting from most to least significant
H,Q:
- mode of the part
D,S,H:
- mode of the containing operand
0,F:
- value of the other parts (F—all bits set)
The constraint matches if the specified part of a constant
has a value different from its other parts.
Q
- Memory reference without index register and with short displacement.
R
- Memory reference with index register and short displacement.
S
- Memory reference without index register but with long displacement.
T
- Memory reference with index register and long displacement.
U
- Pointer with short displacement.
W
- Pointer with long displacement.
Y
- Shift count operand.
- Score family—config/score/score.h
-
d
- Registers from r0 to r32.
e
- Registers from r0 to r16.
t
- r8—r11 or r22—r27 registers.
h
- hi register.
l
- lo register.
x
- hi + lo register.
q
- cnt register.
y
- lcb register.
z
- scb register.
a
- cnt + lcb + scb register.
c
- cr0—cr15 register.
b
- cp1 registers.
f
- cp2 registers.
i
- cp3 registers.
j
- cp1 + cp2 + cp3 registers.
I
- High 16-bit constant (32-bit constant with 16 LSBs zero).
J
- Unsigned 5 bit integer (in the range 0 to 31).
K
- Unsigned 16 bit integer (in the range 0 to 65535).
L
- Signed 16 bit integer (in the range −32768 to 32767).
M
- Unsigned 14 bit integer (in the range 0 to 16383).
N
- Signed 14 bit integer (in the range −8192 to 8191).
Z
- Any SYMBOL_REF.
- Xstormy16—config/stormy16/stormy16.h
-
a
- Register r0.
b
- Register r1.
c
- Register r2.
d
- Register r8.
e
- Registers r0 through r7.
t
- Registers r0 and r1.
y
- The carry register.
z
- Registers r8 and r9.
I
- A constant between 0 and 3 inclusive.
J
- A constant that has exactly one bit set.
K
- A constant that has exactly one bit clear.
L
- A constant between 0 and 255 inclusive.
M
- A constant between −255 and 0 inclusive.
N
- A constant between −3 and 0 inclusive.
O
- A constant between 1 and 4 inclusive.
P
- A constant between −4 and −1 inclusive.
Q
- A memory reference that is a stack push.
R
- A memory reference that is a stack pop.
S
- A memory reference that refers to a constant address of known value.
T
- The register indicated by Rx (not implemented yet).
U
- A constant that is not between 2 and 15 inclusive.
Z
- The constant 0.
- Xtensa—config/xtensa/constraints.md
-
a
- General-purpose 32-bit register
b
- One-bit boolean register
A
- MAC16 40-bit accumulator register
I
- Signed 12-bit integer constant, for use in MOVI instructions
J
- Signed 8-bit integer constant, for use in ADDI instructions
K
- Integer constant valid for BccI instructions
L
- Unsigned constant valid for BccUI instructions