1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * PCI Configuration File: pciconf.c 5 * 6 ********************************************************************* 7 * 8 * Copyright 2001,2002,2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 43/* 44 * Based in part on the algor p5064 version of pciconf.c: 45 * generic PCI bus configuration 46 * Copyright (c) 1999 Algorithmics Ltd 47 * which in turn appears to be based on PMON code. 48 */ 49 50#include "cfe_pci.h" 51#include "cfe_timer.h" 52#include "lib_types.h" 53#include "lib_string.h" 54#include "lib_printf.h" 55#include "lib_malloc.h" 56 57#include "pcivar.h" 58#include "pcireg.h" 59#include "pcidevs.h" 60#include "ldtreg.h" 61 62#ifndef MIN 63#define MIN(a,b) ((a) < (b) ? (a) : (b)) 64#endif 65 66#ifndef MAX 67#define MAX(a,b) ((a) > (b) ? (a) : (b)) 68#endif 69 70#define PRINTF printf 71#define VPRINTF vprintf 72 73extern void cfe_ledstr(const char *); 74#define SBD_DISPLAY(msg) cfe_ledstr(msg) 75 76int _pciverbose; 77 78/* pci_devinfo uses sprintf(), and we don't necessarily want to drag 79 in all those tables for a minimal build, so set this function 80 pointer if it is required. */ 81void (*_pci_devinfo_func) (pcireg_t, pcireg_t, int, char *); 82 83int _pci_enumerated = 0; 84 85/* The "devices" here are actually PCI "functions" */ 86#ifndef PCIMAX_DEV 87#define PCIMAX_DEV 16 /* arbitrary */ 88#endif 89#ifndef PCIMAX_MEMWIN 90#define PCIMAX_MEMWIN 3 /* arbitrary per device */ 91#endif 92#ifndef PCIMAX_IOWIN 93#define PCIMAX_IOWIN 1 /* arbitrary per device */ 94#endif 95 96/* Summary data structures retained after configuration. */ 97 98struct pci_tree { 99 int nargs; 100 struct pci_attach_args *args; 101}; 102 103static struct pci_tree pcitree[PCI_HOST_PORTS]; 104 105 106/* Additional configuration-time data structures. */ 107 108struct pcidev { 109 struct pci_attach_args *pa; 110 int bus; 111 unsigned char min_gnt; 112 unsigned char max_lat; 113 short nmemwin; 114 short niowin; 115}; 116 117struct pciwin { 118 struct pcidev *dev; 119 int reg; 120 size_t size; 121 pcireg_t address; 122}; 123 124struct pcirange { 125 pcireg_t base; 126 pcireg_t next; 127 pcireg_t limit; 128}; 129 130static struct pci_attach_args *pciarg; /* the array of devices (external) */ 131static struct pcidev *pcidev; /* parallel attr array (internal) */ 132 133static int pci_nbus; 134static int pcindev; 135static int pcimaxdev; 136 137static struct pciwin *pcimemwin; /* the array of memory windows */ 138static int pcinmemwin; 139static int pcimaxmemwin; 140static struct pcirange pcimemaddr; 141 142static struct pciwin *pciiowin; /* the array of i/o windows */ 143static int pciniowin; 144static int pcimaxiowin; 145static struct pcirange pciioaddr; 146 147 148 149static int lhb_secondary_bus; 150static int lhb_subordinate_bus; 151 152 153static void 154print_bdf (int port, int bus, int device, int function) 155{ 156 PRINTF ("PCI"); 157 if (PCI_HOST_PORTS > 1 && port >= 0) 158 PRINTF ("[%d]", port); 159 if (bus >= 0) 160 PRINTF (" bus %d", bus); 161 if (device >= 0) 162 PRINTF (" slot %d", device); 163 if (function >= 0) 164 PRINTF ("/%d", function); 165 PRINTF (": "); 166} 167 168static void 169pci_bdfprintf (int port, int bus, int device, int function, 170 const char *fmt, ...) 171{ 172 va_list arg; 173 174 print_bdf (port, bus, device, function); 175#ifdef __VARARGS_H 176 va_start(arg); 177#else 178 va_start(arg, fmt); 179#endif 180 VPRINTF (fmt, arg); 181 va_end(arg); 182} 183 184void 185pci_tagprintf (pcitag_t tag, const char *fmt, ...) 186{ 187 va_list arg; 188 int port, bus, device, function; 189 190 pci_break_tag (tag, &port, &bus, &device, &function); 191 print_bdf (port, bus, device, function); 192 193#ifdef __VARARGS_H 194 va_start(arg); 195#else 196 va_start(arg, fmt); 197#endif 198 VPRINTF (fmt, arg); 199 va_end(arg); 200} 201 202 203/* Initialize the pci-pci bridges and bus hierarchy. */ 204 205/* let rec */ 206static void pci_businit (int port, int bus, pci_flags_t flags); 207 208static void 209pci_businit_dev_func (pcitag_t tag, pci_flags_t flags) 210{ 211 pcireg_t id, class, bhlc; 212 213 class = pci_conf_read(tag, PCI_CLASS_REG); 214 id = pci_conf_read(tag, PCI_ID_REG); 215 bhlc = pci_conf_read(tag, PCI_BHLC_REG); 216 217 pcindev++; 218 219 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && PCI_HDRTYPE_TYPE(bhlc) == 1) { 220 enum {NONE, PCI, LDT} sec_type; 221 int offset; 222 int port, bus, device, function; 223 int bus2; 224 struct pci_bus *ppri, *psec; 225 pcireg_t data; 226 227 sec_type = NONE; 228 offset = 0; 229 switch (PCI_SUBCLASS(class)) { 230 case PCI_SUBCLASS_BRIDGE_PCI: 231 /* See if there is an LDT capability for the secondary. */ 232 offset = pci_find_ldt_cap(tag, LDT_SECONDARY); 233 sec_type = offset == 0 ? PCI : LDT; 234 break; 235 case PCI_SUBCLASS_BRIDGE_HOST: 236 case PCI_SUBCLASS_BRIDGE_MISC: 237 /* A Type 1 host bridge (e.g., SB-1250 LDT) or an 238 X-to-LDT bridge with unassigned subclass (LDT?). 239 Probe iff the secondary is LDT (best policy?) */ 240 offset = pci_find_ldt_cap(tag, LDT_SECONDARY); 241 if (offset != 0) sec_type = LDT; 242 break; 243 } 244 245 if (sec_type == NONE) 246 return; 247 248 if (sec_type == LDT && offset != 0) { 249 pcireg_t cr = pci_conf_read(tag, offset+LDT_COMMAND_CAP_OFF); 250 if ((cr & LDT_COMMAND_DOUBLE_ENDED) != 0) 251 return; 252 } 253 254 bus2 = pci_nextbus(port); 255 if (bus2 < 0) 256 return; 257 pci_nbus = bus2 + 1; 258 259 pci_break_tag(tag, &port, &bus, &device, &function); 260 ppri = pci_businfo(port, bus); 261 262 psec = pci_businfo(port, bus2); 263 psec->tag = tag; 264 psec->primary = bus; 265 psec->port = port; 266 267 /* 268 * set primary to bus, secondary to bus2, and 269 * subordinate to max possible bus number 270 */ 271 data = (PCI_BUSMAX << 16) | (bus2 << 8) | bus; 272 pci_conf_write(tag, PPB_BUSINFO_REG, data); 273 274 /* 275 * set base interrupt mapping. 276 */ 277 if (bus == 0) { 278 /* We assume board-specific wiring for bus 0 devices. */ 279 psec->inta_shift = pci_int_shift_0(tag); 280 } else { 281 /* We assume expansion boards wired per PCI Bridge spec */ 282 psec->inta_shift = (ppri->inta_shift + device) % 4; 283 } 284 285 /* if the new bus is LDT, do the fabric initialization */ 286 if (sec_type == LDT) 287 psec->no_probe = ldt_chain_init(tag, port, bus2, flags); 288 else 289 psec->no_probe = 0; 290 291#ifdef _CSWARM_ 292 /* We must avoid attempting to scan the secondary bus of the 293 diagnostic sturgeon on a cswarm (MasterAbortMode == 0 294 appears not to suppress propagation of aborts). We know 295 its secondary bus number will be 2 on cswarm. */ 296 if (bus2 == 2) { 297 psec->no_probe = 1; 298 } 299#endif 300 301 if (psec->no_probe) { 302 psec->min_io_addr = 0xffffffff; 303 psec->max_io_addr = 0; 304 psec->min_mem_addr = 0xffffffff; 305 psec->max_mem_addr = 0; 306 } else 307 pci_businit(port, bus2, flags); 308 309 /* reset subordinate bus number */ 310 data = (data & 0xff00ffff) | ((pci_nbus - 1) << 16); 311 pci_conf_write(tag, PPB_BUSINFO_REG, data); 312 313 /* SB-1250 pass 1 work-around: remember the buses behind the 314 LDT host bridge. This is not the far end of a 315 double-hosted chain. */ 316 if (PCI_VENDOR(id) == PCI_VENDOR_SIBYTE && 317 PCI_PRODUCT(id) == PCI_PRODUCT_SIBYTE_SB1250_LDT && 318 PCI_REVISION(class) == 1) { 319 lhb_secondary_bus = bus2; 320 lhb_subordinate_bus = pci_nbus - 1; 321 } 322 } 323} 324 325static void 326pci_businit_dev (int port, int bus, int device, pci_flags_t flags) 327{ 328 pcitag_t tag; 329 pcireg_t bhlc; 330 int function, maxfunc; 331 332 tag = pci_make_tag(port, bus, device, 0); 333 if (!pci_canscan (tag)) 334 return; 335 336 if (!pci_probe_tag(tag)) 337 return; 338 339 bhlc = pci_conf_read(tag, PCI_BHLC_REG); 340 maxfunc = PCI_HDRTYPE_MULTIFN(bhlc) ? PCI_FUNCMAX : 0; 341 342 for (function = 0; function <= maxfunc; function++) { 343 tag = pci_make_tag(port, bus, device, function); 344 if (pci_probe_tag(tag)) 345 pci_businit_dev_func(tag, flags); 346 } 347} 348 349 350static void 351pci_businit (int port, int bus, pci_flags_t flags) 352{ 353 int device; 354 struct pci_bus *ppri = pci_businfo(port, bus); 355 356 ppri->min_io_addr = 0xffffffff; 357 ppri->max_io_addr = 0; 358 ppri->min_mem_addr = 0xffffffff; 359 ppri->max_mem_addr = 0; 360 361 /* Pass 1 errata: we must number the buses in ascending order to 362 avoid problems with the LDT host bridge capturing all 363 configuration cycles. */ 364 365 for (device = 0; device <= PCI_DEVMAX; device++) 366 pci_businit_dev (port, bus, device, flags); 367} 368 369 370/* Scan each PCI device on the system and record its configuration 371 requirements. */ 372 373static void 374pci_query_dev_func (pcitag_t tag) 375{ 376 pcireg_t id, class; 377 pcireg_t old, mask; 378 pcireg_t stat; 379 pcireg_t bparam; 380 pcireg_t icr; 381 pcireg_t bhlc; 382 pcireg_t t; /* used for pushing writes to cfg registers */ 383 unsigned int x; 384 int reg, mapreg_end, mapreg_rom; 385 struct pci_bus *pb; 386 struct pci_attach_args *pa; 387 struct pcidev *pd; 388 struct pciwin *pm, *pi; 389 int port, bus, device, function, incr; 390 uint16_t cmd; 391 uint8_t pin, pci_int; 392 393 class = pci_conf_read(tag, PCI_CLASS_REG); 394 id = pci_conf_read(tag, PCI_ID_REG); 395 pci_break_tag(tag, &port, &bus, &device, &function); 396 397 if (_pciverbose && _pci_devinfo_func) { 398 char devinfo[256]; 399 (*_pci_devinfo_func)(id, class, 1, devinfo); 400 pci_tagprintf(tag, "%s\n", devinfo); 401 } 402 403 if (pcindev >= pcimaxdev) { 404 panic ("pci: unexpected device number\n"); 405 return; 406 } 407 408 pa = &pciarg[pcindev]; 409 pa->pa_tag = tag; 410 pa->pa_id = id; 411 pa->pa_class = class; 412 413 pd = &pcidev[pcindev++]; 414 pd->pa = pa; 415 pd->bus = bus; 416 pd->nmemwin = 0; 417 pd->niowin = 0; 418 419 pb = pci_businfo(port, bus); 420 pb->ndev++; 421 422 stat = pci_conf_read(tag, PCI_COMMAND_STATUS_REG); 423 424 /* do all devices support fast back-to-back */ 425 if ((stat & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 426 pb->fast_b2b = 0; /* no, sorry */ 427 428 /* do all devices run at 66 MHz */ 429 if ((stat & PCI_STATUS_66MHZ_SUPPORT) == 0) 430 pb->freq66 = 0; /* no, sorry */ 431 432 /* find slowest devsel */ 433 x = PCI_STATUS_DEVSEL(stat); 434 if (x > pb->devsel) 435 pb->devsel = x; 436 437 bparam = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG); 438 439 pd->min_gnt = PCI_BPARAM_GRANT (bparam); 440 pd->max_lat = PCI_BPARAM_LATENCY (bparam); 441 442 if (pd->min_gnt != 0 || pd->max_lat != 0) { 443 /* find largest minimum grant time of all devices */ 444 if (pd->min_gnt != 0 && pd->min_gnt > pb->min_gnt) 445 pb->min_gnt = pd->min_gnt; 446 447 /* find smallest maximum latency time of all devices */ 448 if (pd->max_lat != 0 && pd->max_lat < pb->max_lat) 449 pb->max_lat = pd->max_lat; 450 451 if (pd->max_lat != 0) 452 /* subtract our minimum on-bus time per sec from bus bandwidth */ 453 pb->bandwidth -= pd->min_gnt * 4000000 / 454 (pd->min_gnt + pd->max_lat); 455 } 456 457 /* Hook any special setup code and test for skipping resource 458 allocation, e.g., for our own host bridges. */ 459 if (pci_device_preset(tag) != 0) 460 return; 461 462 /* Does the function need an interrupt mapping? */ 463 icr = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG); 464 pin = PCI_INTERRUPT_PIN(icr); 465 icr &=~ (PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 466 if (pin == PCI_INTERRUPT_PIN_NONE) 467 pci_int = 0; 468 else if (bus == 0) 469 pci_int = pci_int_map_0(tag); 470 else 471 pci_int = (pb->inta_shift + device + (pin - 1)) % 4 + 1; 472 icr |= pci_int_line(pci_int) << PCI_INTERRUPT_LINE_SHIFT; 473 pci_conf_write(tag, PCI_BPARAM_INTERRUPT_REG, icr); 474 475 /* Find and size the BARs */ 476 bhlc = pci_conf_read(tag, PCI_BHLC_REG); 477 switch (PCI_HDRTYPE_TYPE(bhlc)) { 478 case 0: /* Type 0 */ 479 mapreg_end = PCI_MAPREG_END; 480 mapreg_rom = PCI_MAPREG_ROM; 481 break; 482 case 1: /* Type 1 (bridge) */ 483 mapreg_end = PCI_MAPREG_PPB_END; 484 mapreg_rom = PCI_MAPREG_PPB_ROM; 485 break; 486 case 2: /* Type 2 (cardbus) */ 487 mapreg_end = PCI_MAPREG_PCB_END; 488 mapreg_rom = PCI_MAPREG_NONE; 489 break; 490 default: /* unknown */ 491 mapreg_end = PCI_MAPREG_START; /* assume none */ 492 mapreg_rom = PCI_MAPREG_NONE; 493 break; 494 } 495 496 cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG); 497 cmd &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT); /* don't clear status */ 498 pci_conf_write(tag, PCI_COMMAND_STATUS_REG, 499 cmd & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)); 500 t = pci_conf_read(tag, PCI_COMMAND_STATUS_REG); /* push the write */ 501 502 for (reg = PCI_MAPREG_START; reg < mapreg_end; reg += incr) { 503 old = pci_conf_read(tag, reg); 504 pci_conf_write(tag, reg, 0xffffffff); 505 mask = pci_conf_read(tag, reg); 506 pci_conf_write(tag, reg, old); 507 508 /* Assume 4 byte reg, unless we find out otherwise below. */ 509 incr = 4; 510 511 /* 0 if not implemented, all-1s if (for some reason) 2nd half 512 of 64-bit BAR or if device broken and reg not implemented 513 (should return 0). */ 514 if (mask == 0 || mask == 0xffffffff) 515 continue; 516 517 if (_pciverbose >= 3) 518 pci_tagprintf (tag, "reg 0x%x = 0x%x\n", reg, mask); 519 520 if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) { 521 522 mask |= 0xffff0000; /* must be ones */ 523 524 if (pciniowin >= pcimaxiowin) { 525 PRINTF ("pci: too many i/o windows\n"); 526 continue; 527 } 528 pi = &pciiowin[pciniowin++]; 529 530 pi->dev = pd; 531 pi->reg = reg; 532 pi->size = -(PCI_MAPREG_IO_ADDR(mask)); 533 pd->niowin++; 534 } else { 535 switch (PCI_MAPREG_MEM_TYPE(mask)) { 536 case PCI_MAPREG_MEM_TYPE_32BIT: 537 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 538 break; 539 case PCI_MAPREG_MEM_TYPE_64BIT: 540 incr = 8; 541 { 542 pcireg_t oldhi, maskhi; 543 544 if (reg + 4 >= PCI_MAPREG_END) { 545 pci_tagprintf (tag, 546 "misplaced 64-bit region ignored\n"); 547 continue; 548 } 549 550 oldhi = pci_conf_read(tag, reg + 4); 551 pci_conf_write(tag, reg + 4, 0xffffffff); 552 maskhi = pci_conf_read(tag, reg + 4); 553 pci_conf_write(tag, reg + 4, oldhi); 554 555 if (maskhi != 0xffffffff && maskhi != 0x00000000) { 556 /* First, fix malformed 0*1* */ 557 if ((maskhi & (maskhi+1)) == 0x00000000) { 558 pci_tagprintf (tag, 559 "Warning: " 560 "ill-formed 64-bit BAR (%08x)\n", 561 maskhi); 562 maskhi = 0xffffffff; 563 } 564 } 565 /* Check for 1*0*. */ 566 if ((-maskhi & ~maskhi) != 0x00000000) { 567 pci_tagprintf (tag, 568 "true 64-bit region (%08x) ignored\n", 569 maskhi); 570 continue; 571 } 572 } 573 break; 574 default: 575 pci_tagprintf (tag, "reserved mapping type 0x%x\n", 576 PCI_MAPREG_MEM_TYPE(mask)); 577 continue; 578 } 579 580 if (!PCI_MAPREG_MEM_PREFETCHABLE(mask)) 581 pb->prefetch = 0; 582 583 if (pcinmemwin >= pcimaxmemwin) { 584 PRINTF ("pci: too many memory windows\n"); 585 continue; 586 } 587 pm = &pcimemwin[pcinmemwin++]; 588 589 pm->dev = pd; 590 pm->reg = reg; 591 pm->size = -(PCI_MAPREG_MEM_ADDR(mask)); 592 pd->nmemwin++; 593 } 594 } 595 596 /* Finally check for Expansion ROM */ 597 if (mapreg_rom != PCI_MAPREG_NONE) { 598 reg = mapreg_rom; 599 old = pci_conf_read(tag, reg); 600 pci_conf_write(tag, reg, 0xfffffffe); 601 mask = pci_conf_read(tag, reg); 602 pci_conf_write(tag, reg, old); 603 604 /* 0 if not implemented, 0xfffffffe or 0xffffffff if device 605 broken and/or register not implemented. */ 606 if (mask != 0 && mask != 0xfffffffe && mask != 0xffffffff) { 607 if (_pciverbose >= 3) 608 pci_tagprintf (tag, "reg 0x%x = 0x%x\n", reg, mask); 609 610 if (pcinmemwin >= pcimaxmemwin) { 611 PRINTF ("pci: too many memory windows\n"); 612 goto done; 613 } 614 615 pm = &pcimemwin[pcinmemwin++]; 616 pm->dev = pd; 617 pm->reg = reg; 618 pm->size = -(PCI_MAPREG_ROM_ADDR(mask)); 619 pd->nmemwin++; 620 } 621 } 622 623done: 624 cmd |= PCI_COMMAND_INVALIDATE_ENABLE; /* any reason not to? */ 625 pci_conf_write(tag, PCI_COMMAND_STATUS_REG, cmd); 626} 627 628static void 629pci_query_dev (int port, int bus, int device) 630{ 631 pcitag_t tag; 632 pcireg_t bhlc; 633 int probed, function, maxfunc; 634 635 tag = pci_make_tag(port, bus, device, 0); 636 if (!pci_canscan (tag)) 637 return; 638 639 if (_pciverbose >= 2) 640 pci_bdfprintf (port, bus, device, -1, "probe..."); 641 642 probed = pci_probe_tag(tag); 643 644 if (_pciverbose >= 2) 645 PRINTF ("completed\n"); 646 647 if (!probed) 648 return; 649 650 bhlc = pci_conf_read(tag, PCI_BHLC_REG); 651 maxfunc = PCI_HDRTYPE_MULTIFN(bhlc) ? PCI_FUNCMAX : 0; 652 653 for (function = 0; function <= maxfunc; function++) { 654 tag = pci_make_tag(port, bus, device, function); 655 if (pci_probe_tag(tag)) 656 pci_query_dev_func(tag); 657 } 658 659 if (_pciverbose >= 2) 660 pci_bdfprintf (port, bus, device, -1, "done\n"); 661} 662 663 664static void 665pci_query (int port, int bus) 666{ 667 struct pci_bus *pb = pci_businfo(port, bus); 668 int device; 669 pcireg_t sec_status; 670 unsigned int def_ltim, max_ltim; 671 672 if (bus != 0) { 673 sec_status = pci_conf_read(pb->tag, PPB_IO_STATUS_REG); 674 pb->fast_b2b = (sec_status & PCI_STATUS_BACKTOBACK_SUPPORT) ? 1 : 0; 675 pb->freq66 = (sec_status & PCI_STATUS_66MHZ_SUPPORT) ? 1 : 0; 676 } 677 678 if (pb->no_probe) 679 pb->ndev = 0; 680 else { 681 for (device = 0; device <= PCI_DEVMAX; device++) 682 pci_query_dev (port, bus, device); 683 } 684 685 if (pb->ndev != 0) { 686 /* convert largest minimum grant time to cycle count */ 687 max_ltim = pb->min_gnt * (pb->freq66 ? 66 : 33) / 4; 688 689 /* now see how much bandwidth is left to distribute */ 690 if (pb->bandwidth <= 0) { 691 pci_bdfprintf (port, bus, -1, -1, 692 "warning: total bandwidth exceeded\n"); 693 def_ltim = 1; 694 } else { 695 /* calculate a fair share for each device */ 696 def_ltim = pb->bandwidth / pb->ndev; 697 if (def_ltim > pb->max_lat) 698 /* that would exceed critical time for some device */ 699 def_ltim = pb->max_lat; 700 /* convert to cycle count */ 701 def_ltim = def_ltim * (pb->freq66 ? 66 : 33) / 4; 702 } 703 /* most devices don't implement bottom three bits, so round up */ 704 def_ltim = (def_ltim + 7) & ~7; 705 max_ltim = (max_ltim + 7) & ~7; 706 707 pb->def_ltim = MIN (def_ltim, 255); 708 pb->max_ltim = MIN (MAX (max_ltim, def_ltim), 255); 709 } 710} 711 712 713static int 714wincompare (const void *a, const void *b) 715{ 716 const struct pciwin *wa = a, *wb = b; 717 if (wa->dev->bus != wb->dev->bus) 718 /* sort into ascending order of bus number */ 719 return (int)(wa->dev->bus - wb->dev->bus); 720 else 721 /* sort into descending order of size */ 722 return (int)(wb->size - wa->size); 723} 724 725 726static pcireg_t 727pci_allocate_io(pcitag_t tag, size_t size) 728{ 729 pcireg_t address; 730 731 /* allocate upwards after rounding to size boundary */ 732 address = (pciioaddr.next + (size - 1)) & ~(size - 1); 733 if (size != 0) { 734 if (address < pciioaddr.next || address + size > pciioaddr.limit) 735 return -1; 736 pciioaddr.next = address + size; 737 } 738 return address; 739} 740 741static pcireg_t 742pci_align_io_addr(pcireg_t addr) 743{ 744 /* align to appropriate bridge boundaries (4K for Rev 1.1 Bridge Arch). 745 Over/underflow will show up in subsequent allocations. */ 746 return (addr + ((1 << 12)-1)) & ~((1 << 12)-1); 747} 748 749static void 750pci_assign_iowins(int port, int bus, 751 struct pciwin *pi_first, struct pciwin *pi_limit) 752{ 753 struct pciwin *pi; 754 struct pci_bus *pb = pci_businfo(port, bus); 755 pcireg_t t; /* for pushing writes */ 756 757 pciioaddr.next = pci_align_io_addr(pciioaddr.next); 758 759 /* Pass 1 errata work around. Avoid assigning any real devices 760 at the base address of the LDT host bridge. */ 761 if (bus == lhb_secondary_bus) { 762 pb->min_io_addr = pciioaddr.next; 763 pciioaddr.next += (1 << 12); 764 pb->max_io_addr = pciioaddr.next - 1; 765 } 766 767 for (pi = pi_first; pi < pi_limit; pi++) { 768 struct pcidev *pd = pi->dev; 769 pcitag_t tag = pd->pa->pa_tag; 770 pcireg_t base; 771 772 if (pd->niowin < 0) 773 continue; 774 pi->address = pci_allocate_io (tag, pi->size); 775 if (pi->address == -1) { 776 pci_tagprintf (tag, 777 "(%d) not enough PCI i/o space (%ld requested)\n", 778 pi->reg, (long)pi->size); 779 pd->nmemwin = pd->niowin = -1; 780 continue; 781 } 782 783 if (pi->address < pb->min_io_addr) 784 pb->min_io_addr = pi->address; 785 if (pi->address + pi->size - 1 > pb->max_io_addr) 786 pb->max_io_addr = pi->address + pi->size - 1; 787 788 if (_pciverbose >= 2) 789 pci_tagprintf (tag, 790 "I/O BAR at 0x%x gets %ld bytes @ 0x%x\n", 791 pi->reg, (long)pi->size, pi->address); 792 base = pci_conf_read(tag, pi->reg); 793 base = (base & ~PCI_MAPREG_IO_ADDR_MASK) | pi->address; 794 pci_conf_write(tag, pi->reg, base); 795 t = pci_conf_read(tag, pi->reg); 796 } 797 798 if (pb->min_io_addr < pb->max_io_addr) { 799 /* if any io on bus, expand to valid bridge limit */ 800 pb->max_io_addr |= ((1 << 12)-1); 801 pciioaddr.next = pb->max_io_addr + 1; 802 } 803 804 /* More Pass 1 errata work around. Make sure the 32 bytes beyond 805 the LDT window are not allocated by reserving an entire quantum 806 of io space. */ 807 if (bus == lhb_subordinate_bus) { 808 pciioaddr.next = pci_align_io_addr(pciioaddr.next) + (1 << 12); 809 } 810} 811 812static void 813pci_setup_iowins (int port) 814{ 815 struct pciwin *pi, *pi_first, *pi_limit; 816 int bus; 817 818 qsort(pciiowin, pciniowin, sizeof(struct pciwin), wincompare); 819 pi_first = pciiowin; 820 pi_limit = &pciiowin[pciniowin]; 821 822 for (bus = 0; bus < pci_nbus; bus++) { 823 pi = pi_first; 824 while (pi != pi_limit && pi->dev->bus == bus) 825 pi++; 826 pci_assign_iowins(port, bus, pi_first, pi); 827 pi_first = pi; 828 } 829} 830 831 832static pcireg_t 833pci_allocate_mem(pcitag_t tag, size_t size) 834{ 835 pcireg_t address; 836 837 /* allocate upwards after rounding to size boundary */ 838 address = (pcimemaddr.next + (size - 1)) & ~(size - 1); 839 if (size != 0) { 840 if (address < pcimemaddr.next || address + size > pcimemaddr.limit) 841 return -1; 842 pcimemaddr.next = address + size; 843 } 844 return address; 845} 846 847static pcireg_t 848pci_align_mem_addr(pcireg_t addr) 849{ 850 /* align to appropriate bridge boundaries (1M for Rev 1.1 Bridge Arch). 851 Over/underflow will show up in subsequent allocations. */ 852 return (addr + ((1 << 20)-1)) & ~((1 << 20)-1); 853} 854 855static void 856pci_assign_memwins(int port, int bus, 857 struct pciwin *pm_first, struct pciwin *pm_limit) 858{ 859 struct pciwin *pm; 860 struct pci_bus *pb = pci_businfo(port, bus); 861 pcireg_t t; /* for pushing writes */ 862 863 pcimemaddr.next = pci_align_mem_addr(pcimemaddr.next); 864 865 /* Pass 1 errata work around. Avoid assigning any real devices 866 at the base address of the LDT host bridge. */ 867 if (bus == lhb_secondary_bus) { 868 pb->min_mem_addr = pcimemaddr.next; 869 pcimemaddr.next += (1 << 20); 870 pb->max_mem_addr = pcimemaddr.next - 1; 871 } 872 873 for (pm = pm_first; pm < pm_limit; ++pm) { 874 struct pcidev *pd = pm->dev; 875 pcitag_t tag = pd->pa->pa_tag; 876 877 if (pd->nmemwin < 0) 878 continue; 879 pm->address = pci_allocate_mem (tag, pm->size); 880 if (pm->address == -1) { 881 pci_tagprintf (tag, 882 "(%d) not enough PCI mem space (%ld requested)\n", 883 pm->reg, (long)pm->size); 884 pd->nmemwin = pd->niowin = -1; 885 continue; 886 } 887 if (_pciverbose >= 2) 888 pci_tagprintf (tag, 889 "%s BAR at 0x%x gets %ld bytes @ 0x%x\n", 890 pm->reg != PCI_MAPREG_ROM ? "MEM" : "ROM", 891 pm->reg, (long)pm->size, pm->address); 892 893 if (pm->address < pb->min_mem_addr) 894 pb->min_mem_addr = pm->address; 895 if (pm->address + pm->size - 1 > pb->max_mem_addr) 896 pb->max_mem_addr = pm->address + pm->size - 1; 897 898 if (pm->reg != PCI_MAPREG_ROM) { 899 /* normal memory - expansion rom done below */ 900 pcireg_t base = pci_conf_read(tag, pm->reg); 901 base = pm->address | (base & ~PCI_MAPREG_MEM_ADDR_MASK); 902 pci_conf_write(tag, pm->reg, base); 903 t = pci_conf_read(tag, pm->reg); 904 if (PCI_MAPREG_MEM_TYPE(t) == PCI_MAPREG_MEM_TYPE_64BIT) { 905 pci_conf_write(tag, pm->reg + 4, 0); 906 t = pci_conf_read(tag, pm->reg + 4); 907 } 908 } 909 } 910 911 /* align final bus window */ 912 if (pb->min_mem_addr < pb->max_mem_addr) { 913 pb->max_mem_addr |= ((1 << 20) - 1); 914 pcimemaddr.next = pb->max_mem_addr + 1; 915 } 916 917 /* More pass 1 errata work around. Make sure the next 32 bytes 918 beyond the LDT window are not used by reserving an entire 919 quantum of PCI memory space. */ 920 if (bus == lhb_subordinate_bus) { 921 pcimemaddr.next = pci_align_mem_addr(pcimemaddr.next) + (1 << 20); 922 } 923} 924 925static void 926pci_setup_memwins (int port) 927{ 928 struct pciwin *pm, *pm_first, *pm_limit; 929 int bus; 930 931 qsort(pcimemwin, pcinmemwin, sizeof(struct pciwin), wincompare); 932 pm_first = pcimemwin; 933 pm_limit = &pcimemwin[pcinmemwin]; 934 935 for (bus = 0; bus < pci_nbus; bus++) { 936 pm = pm_first; 937 while (pm != pm_limit && pm->dev->bus == bus) 938 pm++; 939 pci_assign_memwins(port, bus, pm_first, pm); 940 pm_first = pm; 941 } 942 943 /* Program expansion rom address base after normal memory base, 944 to keep DEC ethernet chip happy */ 945 for (pm = pcimemwin; pm < pm_limit; pm++) { 946 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 947 struct pcidev *pd = pm->dev; /* expansion rom */ 948 pcitag_t tag = pd->pa->pa_tag; 949 pcireg_t base; 950 pcireg_t t; /* for pushing writes */ 951 952 /* Do not enable ROM at this time -- PCI spec 2.2 s6.2.5.2 last 953 paragraph, says that if the expansion ROM is enabled, accesses 954 to other registers via the BARs may not be done by portable 955 software!!! */ 956 base = pci_conf_read(tag, pm->reg); 957 base = pm->address | (base & ~PCI_MAPREG_ROM_ADDR_MASK); 958 base &= ~PCI_MAPREG_ROM_ENABLE; 959 pci_conf_write(tag, pm->reg, base); 960 t = pci_conf_read(tag, pm->reg); 961 } 962 } 963} 964 965 966static void 967pci_setup_ppb(int port, pci_flags_t flags) 968{ 969 int i; 970 971 for (i = pci_nbus - 1; i > 0; i--) { 972 struct pci_bus *psec = pci_businfo(port, i); 973 struct pci_bus *ppri = pci_businfo(port, psec->primary); 974 if (ppri->min_io_addr > psec->min_io_addr) 975 ppri->min_io_addr = psec->min_io_addr; 976 if (ppri->max_io_addr < psec->max_io_addr) 977 ppri->max_io_addr = psec->max_io_addr; 978 if (ppri->min_mem_addr > psec->min_mem_addr) 979 ppri->min_mem_addr = psec->min_mem_addr; 980 if (ppri->max_mem_addr < psec->max_mem_addr) 981 ppri->max_mem_addr = psec->max_mem_addr; 982 } 983 984 if (_pciverbose >= 2) { 985 struct pci_bus *pb = pci_businfo(port, 0); 986 if (pb->min_io_addr < pb->max_io_addr) 987 pci_bdfprintf (port, 0, -1, -1, "io 0x%08x-0x%08x\n", 988 pb->min_io_addr, pb->max_io_addr); 989 if (pb->min_mem_addr < pb->max_mem_addr) 990 pci_bdfprintf (port, 0, -1, -1, "mem 0x%08x-0x%08x\n", 991 pb->min_mem_addr, pb->max_mem_addr); 992 } 993 994 for (i = 1; i < pci_nbus; i++) { 995 struct pci_bus *pb = pci_businfo(port, i); 996 pcireg_t cmd; 997 pcireg_t iodata, memdata; 998 pcireg_t brctl; 999 pcireg_t t; /* for pushing writes */ 1000 1001 cmd = pci_conf_read(pb->tag, PCI_COMMAND_STATUS_REG); 1002 if (_pciverbose >= 2) 1003 pci_bdfprintf (port, i, -1, -1, 1004 "subordinate to bus %d\n", pb->primary); 1005 1006 cmd |= PCI_COMMAND_MASTER_ENABLE; 1007 if (pb->min_io_addr < pb->max_io_addr) { 1008 uint32_t io_limit; 1009 1010 /* Pass 1 work-round: limits are next free, not last used. */ 1011 io_limit = pb->max_io_addr; 1012 if (i == lhb_secondary_bus) 1013 io_limit++; 1014 1015 cmd |= PCI_COMMAND_IO_ENABLE; 1016 if (_pciverbose >= 2) 1017 pci_bdfprintf (port, i, -1, -1, "io 0x%08x-0x%08x\n", 1018 pb->min_io_addr, io_limit); 1019 iodata = pci_conf_read(pb->tag, PPB_IO_STATUS_REG); 1020 if ((iodata & PPB_IO_ADDR_CAP_MASK) == PPB_IO_ADDR_CAP_32) { 1021 pcireg_t upperdata; 1022 1023 upperdata = ((pb->min_io_addr) >> 16) & PPB_IO_UPPER_BASE_MASK; 1024 upperdata |= (io_limit & PPB_IO_UPPER_LIMIT_MASK); 1025 pci_conf_write(pb->tag, PPB_IO_UPPER_REG, upperdata); 1026 } 1027 iodata = (iodata & ~PPB_IO_BASE_MASK) 1028 | ((pb->min_io_addr >> 8) & 0xf0); 1029 iodata = (iodata & ~PPB_IO_LIMIT_MASK) 1030 | ((io_limit & PPB_IO_LIMIT_MASK) & 0xf000); 1031 } else { 1032 /* Force an empty window */ 1033 iodata = pci_conf_read(pb->tag, PPB_IO_STATUS_REG); 1034 iodata &=~ (PPB_IO_BASE_MASK | PPB_IO_LIMIT_MASK); 1035 iodata |= (1 << 4) | (0 << (8+4)); 1036 } 1037 pci_conf_write(pb->tag, PPB_IO_STATUS_REG, iodata); 1038 /* Push the write (see SB-1250 Errata, Section 8.10) */ 1039 t = pci_conf_read(pb->tag, PPB_IO_STATUS_REG); 1040 1041 if (pb->min_mem_addr < pb->max_mem_addr) { 1042 uint32_t mem_limit; 1043 1044 mem_limit = pb->max_mem_addr; 1045 if (i == lhb_secondary_bus) 1046 mem_limit++; 1047 1048 cmd |= PCI_COMMAND_MEM_ENABLE; 1049 if (_pciverbose >= 2) 1050 pci_bdfprintf (port, i, -1, -1, "mem 0x%08x-0x%08x\n", 1051 pb->min_mem_addr, mem_limit); 1052 memdata = pci_conf_read(pb->tag, PPB_MEM_REG); 1053 memdata = (memdata & ~PPB_MEM_BASE_MASK) 1054 | ((pb->min_mem_addr >> 16) & 0xfff0); 1055 memdata = (memdata & ~PPB_MEM_LIMIT_MASK) 1056 | ((mem_limit & PPB_MEM_LIMIT_MASK) & 0xfff00000); 1057 } else { 1058 /* Force an empty window */ 1059 memdata = pci_conf_read(pb->tag, PPB_MEM_REG); 1060 memdata &=~ (PPB_MEM_BASE_MASK | PPB_MEM_LIMIT_MASK); 1061 memdata |= (1 << 4) | (0 << (16+4)); 1062 } 1063 pci_conf_write(pb->tag, PPB_MEM_REG, memdata); 1064 /* Push the write (see SB-1250 Errata, Section 8.10) */ 1065 t = pci_conf_read(pb->tag, PPB_MEM_REG); 1066 1067 /* Force an empty prefetchable memory window */ 1068 memdata = pci_conf_read(pb->tag, PPB_PREFMEM_REG); 1069 memdata &=~ (PPB_MEM_BASE_MASK | PPB_MEM_LIMIT_MASK); 1070 memdata |= (1 << 4) | (0 << (16+4)); 1071 pci_conf_write(pb->tag, PPB_PREFMEM_REG, memdata); 1072 /* Push the write (see SB-1250 Errata, Section 8.10) */ 1073 t = pci_conf_read(pb->tag, PPB_PREFMEM_REG); 1074 1075 /* Do any final bridge dependent initialization */ 1076 pci_bridge_setup(pb->tag, flags); 1077 1078 brctl = pci_conf_read(pb->tag, PPB_BRCTL_INTERRUPT_REG); 1079#ifdef _SB1250_PASS2_ 1080 /* LDT MasterAborts _will_ cause bus errors in pass 2 when 1081 enabled. Pending negotiations with clients, leave 1082 MasterAbortMode off to disable their propagation. */ 1083#else 1084 brctl |= (PPB_BRCTL_SERR_ENABLE | PPB_BRCTL_MASTER_ABORT_MODE); 1085#endif 1086 if (pb->fast_b2b) 1087 brctl |= PPB_BRCTL_BACKTOBACK_ENABLE; 1088 pci_conf_write(pb->tag, PPB_BRCTL_INTERRUPT_REG, brctl); 1089 t = pci_conf_read(pb->tag, PPB_BRCTL_INTERRUPT_REG); /* push */ 1090 1091 pci_conf_write(pb->tag, PCI_COMMAND_STATUS_REG, cmd); 1092 } 1093} 1094 1095 1096int 1097pci_cacheline_log2 (void) 1098{ 1099 /* default to 8 words == 2^3 */ 1100 return 3; 1101} 1102 1103 1104int 1105pci_maxburst_log2 (void) 1106{ 1107 return 32; /* no limit */ 1108} 1109 1110static void 1111pci_setup_devices (int port, pci_flags_t flags) 1112{ 1113 struct pcidev *pd; 1114 1115 /* Enable each PCI interface */ 1116 for (pd = pcidev; pd < &pcidev[pcindev]; pd++) { 1117 struct pci_bus *pb = pci_businfo(port, pd->bus); 1118 pcitag_t tag = pd->pa->pa_tag; 1119 pcireg_t cmd, misc; 1120 unsigned int ltim; 1121 1122 /* Consider setting interrupt line here */ 1123 1124 cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG); 1125 cmd |= PCI_COMMAND_MASTER_ENABLE 1126 | PCI_COMMAND_SERR_ENABLE 1127 | PCI_COMMAND_PARITY_ENABLE; 1128 /* Always enable i/o & memory space, in case this card is 1129 just snarfing space from the fixed ISA block and doesn't 1130 declare separate PCI space. */ 1131 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 1132 if (pb->fast_b2b) 1133 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1134 1135 /* Write status too, to clear any pending error bits. */ 1136 pci_conf_write(tag, PCI_COMMAND_STATUS_REG, cmd); 1137 1138 ltim = pd->min_gnt * (pb->freq66 ? 66 : 33) / 4; 1139 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1140 1141 misc = pci_conf_read (tag, PCI_BHLC_REG); 1142 PCI_LATTIMER_SET (misc, ltim); 1143 PCI_CACHELINE_SET (misc, 1 << pci_cacheline_log2()); 1144 pci_conf_write (tag, PCI_BHLC_REG, misc); 1145 1146 pci_device_setup (tag); /* hook for post setup */ 1147 } 1148} 1149 1150 1151static void 1152pci_configure_tree (int port, pci_flags_t flags) 1153{ 1154 int bus; 1155 1156 pciarg = NULL; 1157 1158 lhb_secondary_bus = lhb_subordinate_bus = -1; 1159 1160 /* initialise the host bridge(s) */ 1161 SBD_DISPLAY ("PCIH"); 1162 if (pci_hwinit(port, flags) < 0) 1163 return; 1164 1165 /* initialise any PCI-PCI bridges, discover and number buses */ 1166 SBD_DISPLAY ("PCIB"); 1167 pci_nbus = pci_maxbus(port) + 1; 1168 pcindev = 0; 1169 pci_businit(port, 0, flags); 1170 1171 /* scan configuration space of all devices to collect attributes */ 1172 SBD_DISPLAY ("PCIS"); 1173 pcimaxdev = pcindev; 1174 pciarg = (struct pci_attach_args *) KMALLOC (pcimaxdev * sizeof(struct pci_attach_args), 0); 1175 if (pciarg == NULL) { 1176 PRINTF ("pci: no memory for device table\n"); 1177 pcimaxdev = 0; 1178 } else { 1179 pcidev = (struct pcidev *) KMALLOC (pcimaxdev * sizeof(struct pcidev), 0); 1180 if (pcidev == NULL) { 1181 KFREE (pciarg); pciarg = NULL; 1182 PRINTF ("pci: no memory for device attribute table\n"); 1183 pcimaxdev = 0; 1184 } 1185 } 1186 pcindev = 0; 1187 1188 pcimaxmemwin = PCIMAX_DEV * PCIMAX_MEMWIN; 1189 pcimemwin = (struct pciwin *) KMALLOC (pcimaxmemwin * sizeof(struct pciwin), 0); 1190 if (pcimemwin == NULL) { 1191 PRINTF ("pci: no memory for window table\n"); 1192 pcimaxmemwin = 0; 1193 } 1194 pcimaxiowin = PCIMAX_DEV * PCIMAX_IOWIN; 1195 pciiowin = (struct pciwin *) KMALLOC (pcimaxiowin * sizeof(struct pciwin), 0); 1196 if (pciiowin == NULL) { 1197 PRINTF ("pci: no memory for window table\n"); 1198 pcimaxiowin = 0; 1199 } 1200 1201 pcinmemwin = pciniowin = 0; 1202 for (bus = 0; bus < pci_nbus; bus++) { 1203 pci_query (port, bus); 1204 } 1205 1206 if (pcindev != pcimaxdev) { 1207 panic ("Inconsistent device count\n"); 1208 return; 1209 } 1210 1211 /* alter PCI bridge parameters based on query data */ 1212 pci_hwreinit (port, flags); 1213 1214 /* setup the individual device windows */ 1215 pcimemaddr.base = pci_minmemaddr(port); 1216 pcimemaddr.limit = pci_maxmemaddr(port); 1217 pciioaddr.base = pci_minioaddr(port); 1218 pciioaddr.limit = pci_maxioaddr(port); 1219 1220 pcimemaddr.next = pcimemaddr.base; 1221 pciioaddr.next = pciioaddr.base; 1222 pci_setup_iowins (port); 1223 pci_setup_memwins (port); 1224 1225 /* set up and enable each device */ 1226 if (pci_nbus > 1) 1227 pci_setup_ppb (port, flags); 1228 pci_setup_devices (port, flags); 1229 1230 KFREE (pciiowin); pciiowin = NULL; 1231 KFREE (pcimemwin); pcimemwin = NULL; 1232 KFREE (pcidev); pcidev = NULL; 1233 1234 pcitree[port].nargs = pcindev; 1235 pcitree[port].args = pciarg; 1236} 1237 1238void 1239pci_configure (pci_flags_t flags) 1240{ 1241 int port; 1242 1243 if (!_pci_enumerated) { 1244 _pciverbose = (PCI_DEBUG > 1) ? 3 : (flags & PCI_FLG_VERBOSE); 1245 _pci_devinfo_func = (_pciverbose != 0) ? pci_devinfo : NULL; 1246 1247 for (port = 0; port < PCI_HOST_PORTS; port++) 1248 pci_configure_tree(port, flags); 1249 1250 _pci_enumerated = 1; 1251 } 1252} 1253 1254 1255int 1256pci_foreachdev(int (*fn)(pcitag_t tag)) 1257{ 1258 int port, i; 1259 1260 for (port = 0; port < PCI_HOST_PORTS; port++) 1261 for (i = 0; i < pcitree[port].nargs; i++) { 1262 int rv = (*fn)(pcitree[port].args[i].pa_tag); 1263 if (rv != 0) 1264 return rv; 1265 } 1266 1267 return 0; 1268} 1269 1270 1271static int 1272dump_configuration(pcitag_t tag) 1273{ 1274 pci_tagprintf(tag, "dump of "); 1275 pci_conf_print(tag); 1276 return 0; 1277} 1278 1279void 1280pci_show_configuration(void) 1281{ 1282 pci_foreachdev(dump_configuration); 1283} 1284 1285int 1286pci_find_class(uint32_t class, int enumidx, pcitag_t *tag) 1287{ 1288 int port, i; 1289 struct pci_attach_args *thisdev; 1290 1291 for (port = 0; port < PCI_HOST_PORTS; port++) { 1292 thisdev = pcitree[port].args; 1293 for (i = 0; i < pcitree[port].nargs && enumidx >= 0; i++) { 1294 if (PCI_CLASS(thisdev->pa_class) == class) { 1295 if (enumidx == 0) { 1296 *tag = thisdev->pa_tag; 1297 return 0; 1298 } else { 1299 enumidx--; 1300 } 1301 } 1302 thisdev++; 1303 } 1304 } 1305 1306 return -1; 1307} 1308 1309int 1310pci_find_device(uint32_t vid, uint32_t did, int enumidx, pcitag_t *tag) 1311{ 1312 int port, i; 1313 struct pci_attach_args *thisdev; 1314 1315 for (port = 0; port < PCI_HOST_PORTS; port++) { 1316 thisdev = pcitree[port].args; 1317 for (i = 0; i < pcitree[port].nargs && enumidx >= 0; i++) { 1318 if ((PCI_VENDOR(thisdev->pa_id) == vid) && 1319 (PCI_PRODUCT(thisdev->pa_id) == did)) { 1320 if (enumidx == 0) { 1321 *tag = thisdev->pa_tag; 1322 return 0; 1323 } else { 1324 enumidx--; 1325 } 1326 } 1327 thisdev++; 1328 } 1329 } 1330 1331 return -1; 1332} 1333