1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * BCM570X (10/100/1K EthernetMAC) registers File: bcm5700.c 5 * 6 ********************************************************************* 7 * 8 * Copyright 2000,2001,2002,2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43#ifndef _BCM5700_H_ 44#define _BCM5700_H_ 45 46/* 47 * Register and bit definitions for the Broadcom BCM570X family (aka 48 * Tigon3) of Integrated MACs. 49 * 50 * The 5700 option for external SSRAM is ignored, since no subsequent 51 * chips support it, nor do the 5700 evaluation boards. 52 * 53 * References: 54 * 55 * Host Programmer Interface Specification for the BCM570X Family 56 * of Highly-Integrated Media Access Controllers, 570X-PG106-R. 57 * Broadcom Corp., 16215 Alton Parkway, Irvine CA, 09/27/02 58 * 59 * Simplified Programmer Interface Specification for the BCM570X Family 60 * of Highly Integrated Media Access Controllers, 570X-PG202-R. 61 * Broadcom Corp., 16215 Alton Parkway, Irvine CA, 10/14/02 62 */ 63 64#define K_PCI_VENDOR_BROADCOM 0x14e4 65#define K_PCI_ID_BCM5700 0x1644 66#define K_PCI_ID_BCM5701 0x1645 67#define K_PCI_ID_BCM5702 0x16A6 68#define K_PCI_ID_BCM5703 0x1647 69#define K_PCI_ID_BCM5703a 0x16A7 70#define K_PCI_ID_BCM5703b 0x16C7 71#define K_PCI_ID_BCM5704C 0x1648 72#define K_PCI_ID_BCM5704S 0x16A8 73#define K_PCI_ID_BCM5705 0x1653 74#define K_PCI_ID_BCM5750 0x1676 75#define K_PCI_ID_BCM471F 0x471F 76 77#define K_PCI_ID_BCM5705_OR_BCM5750(_coreID) \ 78 ((_coreID == K_PCI_ID_BCM5705) || \ 79 (_coreID == K_PCI_ID_BCM5750)) 80 81#define _DD_MAKEMASK1(n) (1 << (n)) 82#define _DD_MAKEMASK(v,n) ((((1)<<(v))-1) << (n)) 83#define _DD_MAKEVALUE(v,n) ((v) << (n)) 84#define _DD_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 85 86 87/* Registers 0x0000 - 0x00FF are PCI Configuration registers (shadow) */ 88 89#define PCI_PCIX_CMD_REG 0x40 90#define PCI_PCIX_STAT_REG 0x44 91 92#define PCI_PMC_REG 0x48 93#define PCI_PMCSR_REG 0x4C 94 95#define PCI_VPD_CAP_REG 0x50 96#define PCI_VPD_DATA_REG 0x54 97 98#define PCI_MSI_CTL_REG 0x58 99#define PCI_MSI_ADDR_REG 0x5C /* 8 bytes */ 100#define PCI_MSI_DATA_REG 0x64 101 102#define R_MISC_HOST_CTRL 0x0068 103#define R_DMA_RW_CTRL 0x006C 104#define R_PCI_STATE 0x0070 105#define R_PCI_CLK_CTRL 0x0074 106#define R_REG_BASE_ADDR 0x0078 107#define R_MEMWIN_BASE_ADDR 0x007C 108#define R_REG_DATA 0x0080 109#define R_MEMWIN_DATA 0x0084 110/* For 5700 and 5701, 0x0088-0x0090 shadow 0x6800-0x6808 */ 111#define R_INT_MBOX0 0x00B0 /* 8 bytes, shadows R_INT_MBOX(0) */ 112 113/* Registers 0x0200 - 0x03FF are High Priority Mailbox registers */ 114 115#define R_INT_MBOX(n) (0x0200 + 8*(n)) /* 0 <= n < 4 */ 116#define R_GEN_MBOX(n) (0x0220 + 8*(n)-8) /* 1 <= n <= 8 */ 117#define R_RELOAD_STATS_MBOX 0x0260 118#define R_RCV_BD_STD_PI 0x0268 119#define R_RCV_BD_JUMBO_PI 0x0270 120#define R_RCV_BD_MINI_PI 0x0278 121#define R_RCV_BD_RTN_CI(n) (0x0280 + 8*(n)-8) /* 1 <= n <= 16 */ 122#define R_SND_BD_PI(n) (0x0300 + 8*(n)-8) /* 1 <= n <= 16 */ 123#define R_SND_BD_NIC_PI(n) (0x0380 + 8*(n)-8) /* 1 <= n <= 16 */ 124 125/* Registers 0x0400 - 0x0BFF are MAC Control registers */ 126 127#define R_MAC_MODE 0x0400 128#define R_MAC_STATUS 0x0404 129#define R_MAC_EVENT_ENB 0x0408 130#define R_MAC_LED_CTRL 0x040C 131 132#define R_MAC_ADDR1_HIGH 0x0410 133#define R_MAC_ADDR1_LOW 0x0414 134#define R_MAC_ADDR2_HIGH 0x0418 135#define R_MAC_ADDR2_LOW 0x041C 136#define R_MAC_ADDR3_HIGH 0x0420 137#define R_MAC_ADDR3_LOW 0x0424 138#define R_MAC_ADDR4_HIGH 0x0428 139#define R_MAC_ADDR4_LOW 0x042C 140 141#define R_WOL_PATTERN_PTR 0x0430 142#define R_WOL_PATTERN_CFG 0x0434 143#define R_TX_BACKOFF 0x0438 144#define R_RX_MTU 0x043C 145#define R_PCS_TEST 0x0440 146#define R_TX_AUTONEG 0x0444 147#define R_RX_AUTONEG 0x0448 148 149#define R_MI_COMM 0x044C 150#define R_MI_STATUS 0x0450 151#define R_MI_MODE 0x0454 152 153#define R_AUTOPOLL_STAT 0x0458 154#define R_TX_MODE 0x045C 155#define R_TX_STAT 0x0460 156#define R_TX_LENS 0x0464 157#define R_RX_MODE 0x0468 158#define R_RX_STAT 0x046C 159 160#define R_MAC_HASH(n) (0x0470 + 4*(n)) /* 0 <= n < 4 */ 161 162#define R_RX_BD_RULES_CTRL(n) (0x0480 + 8*(n)) /* 0 <= n < 16 */ 163#define R_RX_BD_RULES_MASK(n) (0x0484 + 8*(n)) 164 165#define R_RX_RULES_CFG 0x0500 166#define R_RX_FRAMES_LOW 0x0504 167#define R_MAC_HASH_EXT(n) (0x0520 + 4*(n)) /* 0 <= n < 4 */ 168#define R_MAC_ADDR_EXT(n) (0x0530 + 8*(n)) /* 0 <= n < 12 */ 169#define R_SERDES_CTRL 0x0590 170#define R_SERDES_STAT 0x0594 171#define R_RX_STATS_MEM 0x0800 172#define R_TX_STATS_MEM 0x0880 173 174 175/* 176 * Note on Buffer Descriptor (BD) Ring indices: 177 * Numbering follows Broadcom literature, which uses indices 1-16. 178 * PI = producer index, CI = consumer index. 179 */ 180 181/* Registers 0x0C00 - 0x0FFF are Send Data Initiator Control registers */ 182 183#define R_SND_DATA_MODE 0x0C00 184#define R_SND_DATA_STAT 0x0C04 185#define R_SND_DATA_STATS_CTRL 0x0C08 186#define R_SND_DATA_STATS_ENB 0x0C0C 187#define R_SND_DATA_STATS_INCR 0x0C10 188 189#define R_STATS_CTR_SND_COS(n) (0x0C80 + 4*(n)-4) /* 1 <= n <= 16 */ 190#define R_STATS_DMA_RDQ_FULL 0x0CC0 191#define R_STATS_DMA_HP_RDQ_FULL 0x0CC4 192#define R_STATS_SDCQ_FULL 0x0CC8 193#define R_STATS_NIC_SET_SND_PI 0x0CCC 194#define R_STATS_STAT_UPDATED 0x0CD0 195#define R_STATS_IRQS 0x0CD4 196#define R_STATS_IRQS_AVOIDED 0x0CD8 197#define R_STATS_SND_THRSH_HIT 0x0CDC 198 199/* Registers 0x1000 - 0x13FF are Send Data Completion Control registers */ 200 201#define R_SND_DATA_COMP_MODE 0x1000 202 203/* Registers 0x1400 - 0x17FF are Send BD Ring Selection Control registers */ 204 205#define R_SND_BD_SEL_MODE 0x1400 206#define R_SND_BD_SEL_STAT 0x1404 207#define R_SND_BD_DIAG 0x1408 208#define R_SND_BD_SEL_CI(n) (0x1440 + 4*(n)-4) /* 1 <= n <= 16 */ 209 210/* Registers 0x1800 - 0x1BFF are Send BD Initiator Control registers */ 211 212#define R_SND_BD_INIT_MODE 0x1800 213#define R_SND_BD_INIT_STAT 0x1804 214#define R_SND_BD_INIT_PI(n) (0x1808 + 4*(n)-4) /* 1 <= n <= 16 */ 215 216/* Registers 0x1C00 - 0x1FFF are Send BD Completion Control registers */ 217 218#define R_SND_BD_COMP_MODE 0x1C00 219 220/* Registers 0x2000 - 0x23FF are Receive List Placement Control registers */ 221 222#define R_RCV_LIST_MODE 0x2000 223#define R_RCV_LIST_STAT 0x2004 224#define R_RCV_LIST_LOCK 0x2008 225#define R_RCV_NONEMPTY_BITS 0x200C 226#define R_RCV_LIST_CFG 0x2010 227#define R_RCV_LIST_STATS_CTRL 0x2014 228#define R_RCV_LIST_STATS_ENB 0x2018 229#define R_RCV_LIST_STATS_INC 0x201C 230#define R_RCV_LIST_HEAD(n) (0x2100 + 16*(n)-16) /* 1 <= n <= 16 */ 231#define R_RCV_LIST_TAIL(n) (0x2104 + 16*(n)-16) 232#define R_RCV_LIST_CNT(n) (0x2108 + 16*(n)-16) 233#define R_STATS_CTR_RCV_COS(n) (0x2200 + 4*(n)-4) /* 1 <= n <= 16 */ 234#define R_STATS_FILT_DROP 0x2240 235#define R_STATS_DMA_WRQ_FULL 0x2244 236#define R_STATS_DMA_HP_WRQ_FULL 0x2248 237#define R_STATS_NO_RCV_BDS 0x224C 238#define R_STATS_IN_DISCARDS 0x2250 239#define R_STATS_IN_ERRORS 0x2254 240#define R_STATS_RCV_THRSH_HIT 0x2258 241 242/* Registers 0x2400 - 0x27FF are Receive Data/BD Initiator Control registers */ 243 244#define R_RCV_DATA_INIT_MODE 0x2400 245#define R_RCV_DATA_INIT_STAT 0x2404 246#define R_JUMBO_RCV_BD_RCB 0x2440 /* 16 bytes */ 247#define R_STD_RCV_BD_RCB 0x2450 /* 16 bytes */ 248#define R_MINI_RCV_BD_RCB 0x2460 /* 16 bytes */ 249#define R_RCV_BD_INIT_JUMBO_CI 0x2470 250#define R_RCV_BD_INIT_STD_CI 0x2474 251#define R_RCV_BD_INIT_MINI_CI 0x2478 252#define R_RCV_BD_INIT_RTN_PI(n) (0x2480 + 4*(n)-4) /* 1 <= n <= 16 */ 253#define R_RCV_BD_INIT_DIAG 0x24C0 254 255/* Registers 0x2800 - 0x2BFF are Receive Data Completion Control registers */ 256 257#define R_RCV_COMP_MODE 0x2800 258 259/* Registers 0x2C00 - 0x2FFF are Receive BD Initiator Control registers */ 260 261#define R_RCV_BD_INIT_MODE 0x2C00 262#define R_RCV_BD_INIT_STAT 0x2C04 263#define R_RCV_BD_INIT_JUMBO_PI 0x2C08 264#define R_RCV_BD_INIT_STD_PI 0x2C0C 265#define R_RCV_BD_INIT_MINI_PI 0x2C10 266#define R_MINI_RCV_BD_THRESH 0x2C14 267#define R_STD_RCV_BD_THRESH 0x2C18 268#define R_JUMBO_RCV_BD_THRESH 0x2C1C 269 270/* Registers 0x3000 - 0x33FF are Receive BD Completion Control registers */ 271 272#define R_RCV_BD_COMP_MODE 0x3000 273#define R_RCV_BD_COMP_STAT 0x3004 274#define R_NIC_JUMBO_RCV_BD_PI 0x3008 275#define R_NIC_STD_RCV_BD_PI 0x300C 276#define R_NIC_MINI_RCV_BD_PI 0x3010 277 278/* Registers 0x3400 - 0x37FF are Receive List Selector Control registers */ 279 280#define R_RCV_LIST_SEL_MODE 0x3400 281#define R_RCV_LIST_SEL_STATUS 0x3404 282 283/* Registers 0x3800 - 0x3BFF are Mbuf Cluster Free registers */ 284 285#define R_MBUF_FREE_MODE 0x3800 286#define R_MBUF_FREE_STATUS 0x3804 287 288/* Registers 0x3C00 - 0x3FFF are Host Coalescing Control registers */ 289 290#define R_HOST_COAL_MODE 0x3C00 291#define R_HOST_COAL_STAT 0x3C04 292#define R_RCV_COAL_TICKS 0x3C08 293#define R_SND_COAL_TICKS 0x3C0C 294#define R_RCV_COAL_MAX_CNT 0x3C10 295#define R_SND_COAL_MAX_CNT 0x3C14 296#define R_RCV_COAL_INT_TICKS 0x3C18 297#define R_SND_COAL_INT_TICKS 0x3C1C 298#define R_RCV_COAL_INT_CNT 0x3C20 299#define R_SND_COAL_INT_CNT 0x3C24 300#define R_STATS_TICKS 0x3C28 301#define R_STATS_HOST_ADDR 0x3C30 /* 8 bytes */ 302#define R_STATUS_HOST_ADDR 0x3C38 /* 8 bytes */ 303#define R_STATS_BASE_ADDR 0x3C40 304#define R_STATUS_BASE_ADDR 0x3C44 305#define R_FLOW_ATTN 0x3C48 306#define R_NIC_JUMBO_RCV_BD_CI 0x3C50 307#define R_NIC_STD_RCV_BD_CI 0x3C54 308#define R_NIC_MINI_RCV_BD_CI 0x3C58 309#define R_NIC_RTN_PI(n) (0x3C80 + 4*(n)-4) /* 1 <= n <= 16 */ 310#define R_NIC_SND_BD_CD(n) (0x3CC0 + 4*(n)-4) /* 1 <= n <= 16 */ 311 312/* Registers 0x4000 - 0x43FF are Memory Arbiter registers */ 313 314#define R_MEM_MODE 0x4000 315#define R_MEM_STATUS 0x4004 316#define R_MEM_TRAP_LOW 0x4008 317#define R_MEM_TRAP_HIGH 0x400C 318 319 320/* Registers 0x4400 - 0x47FF are Buffer Manager Control registers */ 321 322#define R_BMGR_MODE 0x4400 323#define R_BMGR_STATUS 0x4404 324#define R_BMGR_MBUF_BASE 0x4408 325#define R_BMGR_MBUF_LEN 0x440C 326#define R_BMGR_MBUF_DMA_LOW 0x4410 327#define R_BMGR_MBUF_RX_LOW 0x4414 328#define R_BMGR_MBUF_HIGH 0x4418 329 330#define R_BMGR_DMA_BASE 0x442C 331#define R_BMGR_DMA_LEN 0x4430 332#define R_BMGR_DMA_LOW 0x4434 333#define R_BMGR_DMA_HIGH 0x4438 334 335#define R_BMGR_DIAG1 0x444C 336#define R_BMGR_DIAG2 0x4450 337#define R_BMGR_DIAG3 0x4454 338#define R_BMGR_RCV_FLOW_THRESH 0x4458 339 340/* Registers 0x4800 - 0x4BFF are Read DMA Control registers */ 341 342#define R_RD_DMA_MODE 0x4800 343#define R_RD_DMA_STAT 0x4804 344 345/* Registers 0x4C00 - 0x4FFF are Write DMA Control registers */ 346 347#define R_WR_DMA_MODE 0x4C00 348#define R_WR_DMA_STAT 0x4C04 349 350/* Registers 0x5000 - 0x53FF are RX RISC registers */ 351 352#define R_RX_RISC_MODE 0x5000 353#define R_RX_RISC_STATE 0x5004 354#define R_RX_RISC_PC 0x501C 355 356/* Registers 0x5400 - 0x57FF are TX RISC registers */ 357 358#define R_TX_RISC_MODE 0x5400 359#define R_TX_RISC_STATE 0x5404 360#define R_TX_RISC_PC 0x541C 361 362/* Registers 0x5800 - 0x5BFF are Low Priority Mailbox registers (8 bytes) */ 363 364#define R_LP_INT_MBOX(n) (0x5800 + 8*(n)) /* 0 <= n < 4 */ 365#define R_LP_GEN_MBOX(n) (0x5820 + 8*(n)-8) /* 1 <= n <= 8 */ 366#define R_LP_RELOAD_STATS_MBOX 0x5860 367#define R_LP_RCV_BD_STD_PI 0x5868 368#define R_LP_RCV_BD_JUMBO_PI 0x5870 369#define R_LP_RCV_BD_MINI_PI 0x5878 370#define R_LP_RCV_BD_RTN_CI(n) (0x5880 + 8*(n)-8) /* 1 <= n <= 16 */ 371#define R_LP_SND_BD_PI(n) (0x5900 + 8*(n)-8) /* 1 <= n <= 16 */ 372 373/* Registers 0x5C00 - 0x5C03 are Flow Through Queues */ 374 375#define R_FTQ_RESET 0x5C00 376 377/* Registers 0x6000 - 0x63FF are Message Signaled Interrupt registers */ 378 379#define R_MSI_MODE 0x6000 380#define R_MSI_STATUS 0x6004 381#define R_MSI_FIFO_ACCESS 0x6008 382 383/* Registers 0x6400 - 0x67FF are DMA Completion registers */ 384 385#define R_DMA_COMP_MODE 0x6400 386 387/* Registers 0x6800 - 0x68ff are General Control registers */ 388 389#define R_MODE_CTRL 0x6800 390#define R_MISC_CFG 0x6804 391#define R_MISC_LOCAL_CTRL 0x6808 392#define R_TIMER 0x680C 393#define R_MEM_PWRUP 0x6030 /* 8 bytes */ 394#define R_EEPROM_ADDR 0x6838 395#define R_EEPROM_DATA 0x683C 396#define R_EEPROM_CTRL 0x6840 397#define R_MDI_CTRL 0x6844 398#define R_EEPROM_DELAY 0x6848 399 400/* Registers 0x6C00 - 0x6CFF are ASF Support registers (NYI) */ 401 402/* Registers 0x7000 - 0x7024 are NVM Interface registers (NYI) */ 403 404 405/* PCI Capability registers (should be moved to PCI headers) */ 406 407/* PCI-X Capability and Command Register (0x40) */ 408 409#define PCIX_CMD_DPREC_ENABLE 0x00010000 410#define PCIX_CMD_RLXORDER_ENABLE 0x00020000 411#define PCIX_CMD_RD_CNT_SHIFT 18 412#define PCIX_CMD_RD_CNT_MASK 0x000C0000 413#define PCIX_CMD_MAX_SPLIT_SHIFT 20 414#define PCIX_CMD_MAX_SPLIT_MASK 0x00700000 415 416/* PCI-X Status Register (0x44) */ 417 418 419/* Generic bit fields shared by most MODE and STATUS registers */ 420 421#define M_MODE_RESET _DD_MAKEMASK1(0) 422#define M_MODE_ENABLE _DD_MAKEMASK1(1) 423#define M_MODE_ATTNENABLE _DD_MAKEMASK1(2) 424 425#define M_STAT_ERROR _DD_MAKEMASK1(1) 426 427/* Generic bit fields shared by STATS_CTRL registers */ 428 429#define M_STATS_ENABLE _DD_MAKEMASK1(0) 430#define M_STATS_FASTUPDATE _DD_MAKEMASK1(1) 431#define M_STATS_CLEAR _DD_MAKEMASK1(2) 432#define M_STATS_FLUSH _DD_MAKEMASK1(3) 433#define M_STATS_ZERO _DD_MAKEMASK1(4) 434 435/* Private PCI Configuration registers (p 335) */ 436 437/* MHC: Miscellaneous Host Control Register (0x68) */ 438 439#define M_MHC_CLEARINTA _DD_MAKEMASK1(0) 440#define M_MHC_MASKPCIINT _DD_MAKEMASK1(1) 441#define M_MHC_ENBYTESWAP _DD_MAKEMASK1(2) 442#define M_MHC_ENWORDSWAP _DD_MAKEMASK1(3) 443#define M_MHC_ENPCISTATERW _DD_MAKEMASK1(4) 444#define M_MHC_ENCLKCTRLRW _DD_MAKEMASK1(5) 445#define M_MHC_ENREGWORDSWAP _DD_MAKEMASK1(6) 446#define M_MHC_ENINDIRECT _DD_MAKEMASK1(7) 447#define S_MHC_ASICREV 16 448#define M_MHC_ASICREV _DD_MAKEMASK(16,S_MHC_ASICREV) 449#define G_MHC_ASICREV(x) _DD_GETVALUE(x,S_MHC_ASICREV,M_MHC_ASICREV) 450 451/* DMAC: DMA Read/Write Control Register (0x6c) */ 452 453#define S_DMAC_MINDMA 0 454#define M_DMAC_MINDMA _DD_MAKEMASK(8,S_DMAC_MINDMA) 455#define V_DMAC_MINDMA(x) _DD_MAKEVALUE(x,S_DMAC_MINDMA) 456#define G_DMAC_MINDMA(x) _DD_GETVALUE(x,S_DMAC_MINDMA,M_DMAC_MINDMA) 457 458#define S_DMAC_RDBDY 8 /* 570{0,1} only */ 459#define M_DMAC_RDBDY _DD_MAKEMASK(3,S_DMAC_RDBDY) 460#define V_DMAC_RDBDY(x) _DD_MAKEVALUE(x,S_DMAC_RDBDY) 461#define G_DMAC_RDBDY(x) _DD_GETVALUE(x,S_DMAC_RDBDY,M_DMAC_RDBDY) 462 463#define S_DMAC_WRBDY 11 /* 570{0,1} only */ 464#define M_DMAC_WRBDY _DD_MAKEMASK(3,S_DMAC_WRBDY) 465#define V_DMAC_WRBDY(x) _DD_MAKEVALUE(x,S_DMAC_WRBDY) 466#define G_DMAC_WRBDY(x) _DD_GETVALUE(x,S_DMAC_WRBDY,M_DMAC_WRBDY) 467 468#define S_DMAC_ONEDMA 14 469#define M_DMAC_ONEDMA _DD_MAKEMASK(2,S_DMAC_ONEDMA) 470#define V_DMAC_ONEDMA(x) _DD_MAKEVALUE(x,S_DMAC_ONEDMA) 471#define G_DMAC_ONEDMA(x) _DD_GETVALUE(x,S_DMAC_ONEDMA,M_DMAC_WRBDY) 472 473#define S_DMAC_RDWMK 16 474#define M_DMAC_RDWMK _DD_MAKEMASK(3,S_DMAC_RDWMK) 475#define V_DMAC_RDWMK(x) _DD_MAKEVALUE(x,S_DMAC_RDWMK) 476#define G_DMAC_RDWMK(x) _DD_GETVALUE(x,S_DMAC_RDWMK,M_DMAC_RDWMK) 477 478#define S_DMAC_WRWMK 19 479#define M_DMAC_WRWMK _DD_MAKEMASK(3,S_DMAC_WRWMK) 480#define V_DMAC_WRWMK(x) _DD_MAKEVALUE(x,S_DMAC_WRWMK) 481#define G_DMAC_WRWMK(x) _DD_GETVALUE(x,S_DMAC_WRWMK,M_DMAC_WRWMK) 482 483#define M_DMAC_MEMRDMULT _DD_MAKEMASK1(22) /* 570{0,1} only */ 484#define M_DMAC_BEALL _DD_MAKEMASK1(23) /* 570{0,1} only */ 485#define M_DMAC_ENBUGFIX _DD_MAKEMASK1(23) /* 570{3,4} only */ 486 487#define S_DMAC_RDCMD 24 /* 570{0,1} only */ 488#define M_DMAC_RDCMD _DD_MAKEMASK(4,S_DMAC_RDCMD) 489#define V_DMAC_RDCMD(x) _DD_MAKEVALUE(x,S_DMAC_RDCMD) 490#define G_DMAC_RDCMD(x) _DD_GETVALUE(x,S_DMAC_RDCMD,M_DMAC_RDCMD) 491#define K_PCI_MEMRD 0x6 492 493#define S_DMAC_WRCMD 28 494#define M_DMAC_WRCMD _DD_MAKEMASK(4,S_DMAC_WRCMD) 495#define V_DMAC_WRCMD(x) _DD_MAKEVALUE(x,S_DMAC_WRCMD) 496#define G_DMAC_WRCMD(x) _DD_GETVALUE(x,S_DMAC_WRCMD,M_DMAC_WRCMD) 497#define K_PCI_MEMWR 0x7 498 499/* PCIS: PCI State Register (0x70) */ 500 501#define M_PCIS_RESET _DD_MAKEMASK1(0) 502#define M_PCIS_INT _DD_MAKEMASK1(1) 503#define M_PCIS_MODE _DD_MAKEMASK1(2) 504#define M_PCIS_33MHZ _DD_MAKEMASK1(3) 505#define M_PCIS_32BIT _DD_MAKEMASK1(4) 506#define M_PCIS_ROMEN _DD_MAKEMASK1(5) 507#define M_PCIS_ROMRETRY _DD_MAKEMASK1(6) 508#define M_PCIS_FLATVIEW _DD_MAKEMASK1(8) 509 510#define S_PCIS_MAXRETRY 9 /* 570{0,1} only */ 511#define M_PCIS_MAXRETRY _DD_MAKEMASK(3,S_PCIS_MAXRETRY) 512#define V_PCIS_MAXRETRY(x) _DD_MAKEVALUE(x,S_PCIS_MAXRETRY) 513#define G_PCIS_MAXRETRY(x) _DD_GETVALUE(x,S_PCIS_MAXRETRY,M_PCIS_MAXRETRY) 514 515#define M_PCIS_RETRYSAME _DD_MAKEMASK1(13) /* not 570{0,1} */ 516#define M_PCIS_CARDBUSMODE _DD_MAKEMASK1(14) /* 5705 only */ 517#define M_PCIS_FORCERETRY _DD_MAKEMASK1(15) /* 5705 only */ 518 519/* PCI Clock Control Register (0x74) */ 520 521/* Register Base Address Register (0x78) */ 522 523/* Memory Window Base Address Register (0x7c) */ 524 525 526/* High Priority Mailboxes (p 323) */ 527 528 529/* Ethernet MAC Control registers (p 358) */ 530 531/* MACM: Ethernet MAC Mode Register (0x400) */ 532 533#define M_MACM_GLBRESET _DD_MAKEMASK1(0) 534#define M_MACM_HALFDUPLEX _DD_MAKEMASK1(1) 535 536#define S_MACM_PORTMODE 2 537#define M_MACM_PORTMODE _DD_MAKEMASK(2,S_MACM_PORTMODE) 538#define V_MACM_PORTMODE(x) _DD_MAKEVALUE(x,S_MACM_PORTMODE) 539#define G_MACM_PORTMODE(x) _DD_GETVALUE(x,S_MACM_PORTMODE,M_MACM_PORTMODE) 540#define K_MACM_PORTMODE_NONE 0x0 541#define K_MACM_PORTMODE_MII 0x1 542#define K_MACM_PORTMODE_GMII 0x2 543#define K_MACM_PORTMODE_TBI 0x3 544 545#define M_MACM_LOOPBACK _DD_MAKEMASK1(4) 546#define M_MACM_TAGGEDMAC _DD_MAKEMASK1(7) 547#define M_MACM_TXBURST _DD_MAKEMASK1(8) 548#define M_MACM_MAXDEFER _DD_MAKEMASK1(9) 549#define M_MACM_LINKPOLARITY _DD_MAKEMASK1(10) 550#define M_MACM_RXSTATSENB _DD_MAKEMASK1(11) 551#define M_MACM_RXSTATSCLR _DD_MAKEMASK1(12) 552#define M_MACM_RXSTATSFLUSH _DD_MAKEMASK1(13) 553#define M_MACM_TXSTATSENB _DD_MAKEMASK1(14) 554#define M_MACM_TXSTATSCLR _DD_MAKEMASK1(15) 555#define M_MACM_TXSTATSFLUSH _DD_MAKEMASK1(16) 556#define M_MACM_SENDCFGS _DD_MAKEMASK1(17) 557#define M_MACM_MAGICPKT _DD_MAKEMASK1(18) 558#define M_MACM_ACPI _DD_MAKEMASK1(19) 559#define M_MACM_MIPENB _DD_MAKEMASK1(20) 560#define M_MACM_TDEENB _DD_MAKEMASK1(21) 561#define M_MACM_RDEENB _DD_MAKEMASK1(22) 562#define M_MACM_FHDEENB _DD_MAKEMASK1(23) 563 564/* MACSTAT: Ethernet MAC Status Register (0x404) */ 565/* MACEVNT: Ethernet MAC Event Enable Register (0x408) */ 566 567/* Status Register only */ 568#define M_MACSTAT_PCSSYNC _DD_MAKEMASK1(0) 569#define M_MACSTAT_SIGDET _DD_MAKEMASK1(1) 570#define M_MACSTAT_RCVCFG _DD_MAKEMASK1(2) 571#define M_MACSTAT_CFGCHNG _DD_MAKEMASK1(3) 572#define M_MACSTAT_SYNCCHNG _DD_MAKEMASK1(4) 573/* Status and Enable Registers */ 574#define M_EVT_PORTERR _DD_MAKEMASK1(10) 575#define M_EVT_LINKCHNG _DD_MAKEMASK1(12) 576#define M_EVT_MICOMPLETE _DD_MAKEMASK1(22) 577#define M_EVT_MIINT _DD_MAKEMASK1(23) 578#define M_EVT_APERR _DD_MAKEMASK1(24) 579#define M_EVT_ODIERR _DD_MAKEMASK1(25) 580#define M_EVT_RXSTATOVRUN _DD_MAKEMASK1(26) 581#define M_EVT_TXSTATOVRUN _DD_MAKEMASK1(27) 582 583 584/* LEDCTRL: LED Control Register (0x40c) */ 585#define M_LEDCTRL_OVERRIDE _DD_MAKEMASK1(0) 586#define M_LEDCTRL_1000MBPS _DD_MAKEMASK1(1) 587#define M_LEDCTRL_100MBPS _DD_MAKEMASK1(2) 588 589 590/* MICOMM: MI Communication Register (0x44c) */ 591 592#define S_MICOMM_DATA 0 593#define M_MICOMM_DATA _DD_MAKEMASK(16,S_MICOMM_DATA) 594#define V_MICOMM_DATA(x) _DD_MAKEVALUE(x,S_MICOMM_DATA) 595#define G_MICOMM_DATA(x) _DD_GETVALUE(x,S_MICOMM_DATA,M_MICOMM_DATA) 596 597#define S_MICOMM_REG 16 598#define M_MICOMM_REG _DD_MAKEMASK(5,S_MICOMM_REG) 599#define V_MICOMM_REG(x) _DD_MAKEVALUE(x,S_MICOMM_REG) 600#define G_MICOMM_REG(x) _DD_GETVALUE(x,S_MICOMM_REG,M_MICOMM_REG) 601 602#define S_MICOMM_PHY 21 603#define M_MICOMM_PHY _DD_MAKEMASK(5,S_MICOMM_PHY) 604#define V_MICOMM_PHY(x) _DD_MAKEVALUE(x,S_MICOMM_PHY) 605#define G_MICOMM_PHY(x) _DD_GETVALUE(x,S_MICOMM_PHY,M_MICOMM_PHY) 606 607#define S_MICOMM_CMD 26 608#define M_MICOMM_CMD _DD_MAKEMASK(2,S_MICOMM_CMD) 609#define V_MICOMM_CMD(x) _DD_MAKEVALUE(x,S_MICOMM_CMD) 610#define G_MICOMM_CMD(x) _DD_GETVALUE(x,S_MICOMM_CMD,M_MICOMM_CMD) 611#define K_MICOMM_CMD_WR 0x1 612#define K_MICOMM_CMD_RD 0x2 613#define V_MICOMM_CMD_WR V_MICOMM_CMD(K_MICOMM_CMD_WR) 614#define V_MICOMM_CMD_RD V_MICOMM_CMD(K_MICOMM_CMD_RD) 615 616#define M_MICOMM_RDFAIL _DD_MAKEMASK1(28) 617#define M_MICOMM_BUSY _DD_MAKEMASK1(29) 618 619/* MISTAT: MI Status Register (0x450) */ 620 621#define M_MISTAT_LINKED _DD_MAKEMASK1(0) 622#define M_MISTAT_10MBPS _DD_MAKEMASK1(1) 623 624/* MIMODE: MI Mode Register (0x454) */ 625 626#define M_MIMODE_SHORTPREAMBLE _DD_MAKEMASK1(1) 627#define M_MIMODE_POLLING _DD_MAKEMASK1(4) 628 629#define S_MIMODE_CLKCNT 16 630#define M_MIMODE_CLKCNT _DD_MAKEMASK(5,S_MIMODE_CLKCNT) 631#define V_MIMODE_CLKCNT(x) _DD_MAKEVALUE(x,S_MIMODE_CLKCNT) 632#define G_MIMODE_CLKCNT(x) _DD_GETVALUE(x,S_MIMODE_CLKCNT,M_MIMODE_CLKCNT) 633 634/* TXLEN: Transmit MAC Lengths Register (0x464) */ 635 636#define S_TXLEN_SLOT 0 637#define M_TXLEN_SLOT _DD_MAKEMASK(8,S_TXLEN_SLOT) 638#define V_TXLEN_SLOT(x) _DD_MAKEVALUE(x,S_TXLEN_SLOT) 639#define G_TXLEN_SLOT(x) _DD_GETVALUE(x,S_TXLEN_SLOT,M_TXLEN_SLOT) 640 641#define S_TXLEN_IPG 8 642#define M_TXLEN_IPG _DD_MAKEMASK(4,S_TXLEN_IPG) 643#define V_TXLEN_IPG(x) _DD_MAKEVALUE(x,S_TXLEN_IPG) 644#define G_TXLEN_IPG(x) _DD_GETVALUE(x,S_TXLEN_IPG,M_TXLEN_IPG) 645 646#define S_TXLEN_IPGCRS 12 647#define M_TXLEN_IPGCRS _DD_MAKEMASK(2,S_TXLEN_IPGCRS) 648#define V_TXLEN_IPGCRS(x) _DD_MAKEVALUE(x,S_TXLEN_IPGCRS) 649#define G_TXLEN_IPGCRS(x) _DD_GETVALUE(x,S_TXLEN_IPGCRS,M_TXLEN_IPGCRS) 650 651/* RULESCFG: Receive Rules Configuration Register (0x500) */ 652 653#define S_RULESCFG_DEFAULT 3 654#define M_RULESCFG_DEFAULT _DD_MAKEMASK(5,S_RULESCFG_DEFAULT) 655#define V_RULESCFG_DEFAULT(x) _DD_MAKEVALUE(x,S_RULESCFG_DEFAULT) 656#define G_RULESCFG_DEFAULT(x) _DD_GETVALUE(x,S_RULESCFG_DEFAULT,M_RULESCFG_DEFAULT) 657 658 659/* Send Data Initiator Control Registers (p 383) */ 660/* Send BD Ring Selector Control Registers (p 387) */ 661/* Send BD Initiator Control Registers (p 389) */ 662 663 664/* Receive List Placement Control Registers (p 392) */ 665 666/* LISTCFG: Receive List Placement Configuration Register (0x2010) */ 667 668#define S_LISTCFG_GROUP 0 669#define M_LISTCFG_GROUP _DD_MAKEMASK(3,S_LISTCFG_GROUP) 670#define V_LISTCFG_GROUP(x) _DD_MAKEVALUE(x,S_LISTCFG_GROUP) 671#define G_LISTCFG_GROUP(x) _DD_GETVALUE(x,S_LISTCFG_GROUP,M_LISTCFG_GROUP) 672 673#define S_LISTCFG_ACTIVE 3 674#define M_LISTCFG_ACTIVE _DD_MAKEMASK(5,S_LISTCFG_ACTIVE) 675#define V_LISTCFG_ACTIVE(x) _DD_MAKEVALUE(x,S_LISTCFG_ACTIVE) 676#define G_LISTCFG_ACTIVE(x) _DD_GETVALUE(x,S_LISTCFG_ACTIVE,M_LISTCFG_ACTIVE) 677 678#define S_LISTCFG_BAD 8 679#define M_LISTCFG_BAD _DD_MAKEMASK(5,S_LISTCFG_BAD) 680#define V_LISTCFG_BAD(x) _DD_MAKEVALUE(x,S_LISTCFG_BAD) 681#define G_LISTCFG_BAD(x) _DD_GETVALUE(x,S_LISTCFG_BAD,M_LISTCFG_BAD) 682 683#define S_LISTCFG_DEFAULT 13 684#define M_LISTCFG_DEFAULT _DD_MAKEMASK(2,S_LISTCFG_DEFAULT) 685#define V_LISTCFG_DEFAULT(x) _DD_MAKEVALUE(x,S_LISTCFG_DEFAULT) 686#define G_LISTCFG_DEFAULT(x) _DD_GETVALUE(x,S_LISTCFG_DEFAULT,M_LISTCFG_DEFAULT) 687 688 689/* Receive Data and Receive BD Initiator Control Registers (p 399) */ 690 691/* RCVINITMODE: Receive Data and Receive BD Initiator Mode Register (0x2400) */ 692 693#define M_RCVINITMODE_JUMBO _DD_MAKEMASK1(2) 694#define M_RCVINITMODE_FRMSIZE _DD_MAKEMASK1(3) 695#define M_RCVINITMODE_RTNSIZE _DD_MAKEMASK1(4) 696 697 698/* Receive Initiator Control Registers (p 404) */ 699/* Receive BD Completion Control Registers (p 406) */ 700/* Receive List Selector Control Registers (p 408) */ 701/* Mbuf Cluster Free Registers (p 409) */ 702 703 704/* Host Coalescing Control registers (p 410) */ 705 706/* HCM: Host Coalescing Mode Register (0x3C00) */ 707 708#define M_HCM_RESET _DD_MAKEMASK1(0) 709#define M_HCM_ENABLE _DD_MAKEMASK1(1) 710#define M_HCM_ATTN _DD_MAKEMASK1(2) 711#define M_HCM_COAL_NOW _DD_MAKEMASK1(3) 712 713#define S_HCM_MSIBITS 4 714#define M_HCM_MSIBITS _DD_MAKEMASK(3,S_HCM_MSIBITS) 715#define V_HCM_MSIBITS(x) _DD_MAKEVALUE(x,S_HCM_MSIBITS) 716#define G_HCM_MSIBITS _DD_GETVALUE(x,S_HCM_MSIBITS,M_HCM_MSIBITS) 717 718#define S_HCM_SBSIZE 7 719#define M_HCM_SBSIZE _DD_MAKEMASK(2,S_HCM_SBSIZE) 720#define V_HCM_SBSIZE(x) _DD_MAKEVALUE(x,S_HCM_SBSIZE) 721#define G_HCM_SBSIZE _DD_GETVALUE(x,S_HCM_SBSIZE,M_HCM_SBSIZE) 722#define K_HCM_SBSIZE_80 0x0 723#define K_HCM_SBSIZE_64 0x1 724#define K_HCM_SBSIZE_32 0x2 725/* ... more ... */ 726 727 728/* Memory Arbiter Registers (p 420) */ 729 730/* MAM: Memory Arbiter Mode Register (0x4000) */ 731 732#define M_MAM_RESET _DD_MAKEMASK1(0) 733#define M_MAM_ENABLE _DD_MAKEMASK1(1) 734 735/* Memory Arbiter Status Register (0x4004) */ 736 737/* Memory Arbiter Trap Low and Trap High Registers (0x4008, 0x400C) */ 738 739 740/* Buffer Manager Control Registers (p 424) */ 741 742/* BMODE: Buffer Manager Control Register (0x4400) */ 743 744#define M_BMODE_RESET _DD_MAKEMASK1(0) 745#define M_BMODE_ENABLE _DD_MAKEMASK1(1) 746#define M_BMODE_ATTN _DD_MAKEMASK1(2) 747#define M_BMODE_TEST _DD_MAKEMASK1(3) 748#define M_BMODE_MBUFLOWATTN _DD_MAKEMASK1(4) 749 750 751/* Read DMA Control Registers (p 428) */ 752/* Write DMA Control Registers (p 431) */ 753 754/* Bit fields shared by DMA_MODE and DMA_STATUS registers */ 755 756#define M_ATTN_TGTABORT _DD_MAKEMASK1(2) 757#define M_ATTN_MSTRABORT _DD_MAKEMASK1(3) 758#define M_ATTN_PERR _DD_MAKEMASK1(4) 759#define M_ATTN_ADDROVFL _DD_MAKEMASK1(5) 760#define M_ATTN_FIFOOVFL _DD_MAKEMASK1(6) 761#define M_ATTN_FIFOUNFL _DD_MAKEMASK1(7) 762#define M_ATTN_FIFOREAD _DD_MAKEMASK1(8) 763#define M_ATTN_LENERR _DD_MAKEMASK1(9) 764#define M_ATTN_ALL (M_ATTN_TGTABORT | M_ATTN_MSTRABORT | \ 765 M_ATTN_PERR | M_ATTN_ADDROVFL | \ 766 M_ATTN_FIFOOVFL | M_ATTN_FIFOUNFL | \ 767 M_ATTN_FIFOREAD | M_ATTN_LENERR) 768 769/* Read DMA Mode Register (0x4800) */ 770/* Write DMA Mode Register (0x4C00) */ 771 772/* Read DMA Status Register (0x4804) */ 773/* Write DMA Status Register (0x4C04) */ 774 775 776/* RX RISC Registers (p 433) */ 777/* TX RISC Registers (p 437) */ 778/* Low Priority Mailboxes (p 441) */ 779/* Flow Through Queues (p 445) */ 780 781 782/* Message Signaled Interrupt Registers (p 447) */ 783 784/* MSIMODE: MSI Mode Register (0x6000) */ 785 786#define M_MSIMODE_RESET _DD_MAKEMASK1(0) 787#define M_MSIMODE_ENABLE _DD_MAKEMASK1(1) 788#define M_MSIMODE_TGTABORT _DD_MAKEMASK1(2) 789#define M_MSIMODE_MSTRABORT _DD_MAKEMASK1(3) 790#define M_MSIMODE_PARITYERR _DD_MAKEMASK1(4) 791#define M_MSIMODE_FIFOUNRUN _DD_MAKEMASK1(5) 792#define M_MSIMODE_FIFOOVRUN _DD_MAKEMASK1(6) 793 794#define S_MSIMODE_PRIORITY 30 795#define M_MSIMODE_PRIORITY _DD_MAKEMASK(2,S_MSIMODE_PRIORITY) 796#define V_MSIMODE_PRIORITY(x) _DD_MAKEVALUE(x,S_MSIMODE_PRIORITY) 797#define G_MSIMODE_PRIORITY(x) _DD_GETVALUE(x,S_MSIMODE_PRIORITY,M_MSIMODE_PRIORITY) 798 799/* MSISTAT: MSI Status Register (0x6004) */ 800 801#define M_MSISTAT_TGTABORT _DD_MAKEMASK1(2) 802#define M_MSISTAT_MSTRABORT _DD_MAKEMASK1(3) 803#define M_MSISTAT_PARITYERR _DD_MAKEMASK1(4) 804#define M_MSISTAT_FIFOUNRUN _DD_MAKEMASK1(5) 805#define M_MSISTAT_FIFOOVRUN _DD_MAKEMASK1(6) 806 807/* MSIDATA: MSI FIFO Access Register (0x6008) */ 808 809#define S_MSIFIFO_DATA 0 810#define M_MSIFIFO_DATA _DD_MAKEMASK(3,S_MSIFIFO_DATA) 811#define V_MSIFIFO_DATA(x) _DD_MAKEVALUE(x,S_MSIFIFO_DATA) 812#define G_MSIFIFO_DATA(x) _DD_GETVALUE(x,S_MSIFIFO_DATA,M_MSIFIFO_DATA) 813 814#define M_MSIFIFO_OVFL _DD_MAKEMASK1(3) 815 816 817/* DMA Completion Registers (p 449) */ 818 819 820/* General Control registers (p 450) */ 821 822/* MCTL: Miscellaneous Host Control Register (0x6800) */ 823 824#define M_MCTL_UPDATE _DD_MAKEMASK1(0) 825#define M_MCTL_BSWAPCTRL _DD_MAKEMASK1(1) 826#define M_MCTL_WSWAPCTRL _DD_MAKEMASK1(2) 827#define M_MCTL_BSWAPDATA _DD_MAKEMASK1(4) 828#define M_MCTL_WSWAPDATA _DD_MAKEMASK1(5) 829#define M_MCTL_NOCRACK _DD_MAKEMASK1(9) 830#define M_MCTL_NOCRC _DD_MAKEMASK1(10) 831#define M_MCTL_ACCEPTBAD _DD_MAKEMASK1(11) 832#define M_MCTL_NOTXINT _DD_MAKEMASK1(13) 833#define M_MCTL_NORTRNINT _DD_MAKEMASK1(14) 834#define M_MCTL_PCI32 _DD_MAKEMASK1(15) 835#define M_MCTL_HOSTUP _DD_MAKEMASK1(16) 836#define M_MCTL_HOSTBDS _DD_MAKEMASK1(17) 837#define M_MCTL_NOTXPHSUM _DD_MAKEMASK1(20) 838#define M_MCTL_NORXPHSUM _DD_MAKEMASK1(23) 839#define M_MCTL_TXINT _DD_MAKEMASK1(24) 840#define M_MCTL_RXINT _DD_MAKEMASK1(25) 841#define M_MCTL_MACINT _DD_MAKEMASK1(26) 842#define M_MCTL_DMAINT _DD_MAKEMASK1(27) 843#define M_MCTL_FLOWINT _DD_MAKEMASK1(28) 844#define M_MCTL_4XRINGS _DD_MAKEMASK1(29) 845#define M_MCTL_MCASTEN _DD_MAKEMASK1(30) 846 847/* MCFG: Miscellaneous Configuration Register (0x6804) */ 848 849#define M_MCFG_CORERESET _DD_MAKEMASK1(0) 850#define S_MCFG_PRESCALER 1 851#define M_MCFG_PRESCALER _DD_MAKEMASK(7,S_MCFG_PRESCALER) 852#define V_MCFG_PRESCALER(x) _DD_MAKEVALUE(x,S_MCFG_PRESCALER) 853#define G_MCFG_PRESCALER(x) _DD_GETVALUE(x,S_MCFG_PRESCALER,M_MCFG_PRESCALER) 854 855/* MLCTL: Miscellaneous Local Control Register (0x6808) */ 856 857#define M_MLCTL_INTSTATE _DD_MAKEMASK1(0) 858#define M_MLCTL_INTCLR _DD_MAKEMASK1(1) 859#define M_MLCTL_INTSET _DD_MAKEMASK1(2) 860#define M_MLCTL_INTATTN _DD_MAKEMASK1(3) 861/* ... */ 862#define M_MLCTL_EPAUTOACCESS _DD_MAKEMASK1(24) 863 864/* EPADDR: Serial EEPROM Address Register (0x6838) */ 865 866#define S_EPADDR_ADDR 0 867#define M_EPADDR_ADDR (_DD_MAKEMASK(16,S_EPADDR_ADDR) & ~3) 868#define V_EPADDR_ADDR(x) _DD_MAKEVALUE(x,S_EPADDR_ADDR) 869#define G_EPADDR_ADDR(x) _DD_GETVALUE(x,S_EPADDR_ADDR,M_EPADDR_ADDR) 870 871#define S_EPADDR_HPERIOD 16 872#define M_EPADDR_HPERIOD _DD_MAKEMASK(9,S_EPADDR_HPERIOD) 873#define V_EPADDR_HPERIOD(x) _DD_MAKEVALUE(x,S_EPADDR_HPERIOD) 874#define G_EPADDR_HPERIOD(x) _DD_GETVALUE(x,S_EPADDR_HPERIOD,M_EPADDR_HPERIOD) 875 876#define M_EPADDR_START _DD_MAKEMASK1(25) 877 878#define S_EPADDR_DEVID 26 879#define M_EPADDR_DEVID _DD_MAKEMASK(3,S_EPADDR_DEVID) 880#define V_EPADDR_DEVID(x) _DD_MAKEVALUE(x,S_EPADDR_DEVID) 881#define G_EPADDR_DEVID(x) _DD_GETVALUE(x,S_EPADDR_DEVID,M_EPADDR_DEVID) 882 883#define M_EPADDR_RESET _DD_MAKEMASK1(29) 884#define M_EPADDR_COMPLETE _DD_MAKEMASK1(30) 885#define M_EPADDR_RW _DD_MAKEMASK1(31) 886 887/* EPDATA: Serial EEPROM Data Register (0x683C) */ 888 889/* EPCTL: Serial EEPROM Control Register (0x6840) */ 890 891#define M_EPCTL_CLOCKTS0 _DD_MAKEMASK1(0) 892#define M_EPCTL_CLOCKO _DD_MAKEMASK1(1) 893#define M_EPCTL_CLOCKI _DD_MAKEMASK1(2) 894#define M_EPCTL_DATATSO _DD_MAKEMASK1(3) 895#define M_EPCTL_DATAO _DD_MAKEMASK1(4) 896#define M_EPCTL_DATAI _DD_MAKEMASK1(5) 897 898/* MDCTL: MDI Control Register (0x6844) */ 899 900#define M_MDCTL_DATA _DD_MAKEMASK1(0) 901#define M_MDCTL_ENABLE _DD_MAKEMASK1(1) 902#define M_MDCTL_SELECT _DD_MAKEMASK1(2) 903#define M_MDCTL_CLOCK _DD_MAKEMASK1(3) 904 905 906/* Ring Control Blocks (p 97) */ 907 908#define RCB_HOST_ADDR_HIGH 0x0 909#define RCB_HOST_ADDR_LOW 0x4 910#define RCB_CTRL 0x8 911#define RCB_NIC_ADDR 0xC 912 913#define RCB_SIZE 0x10 914 915#define RCB_FLAG_USE_EXT_RCV_BD _DD_MAKEMASK1(0) 916#define RCB_FLAG_RING_DISABLED _DD_MAKEMASK1(1) 917 918#define S_RCB_MAXLEN 16 919#define M_RCB_MAXLEN _DD_MAKEMASK(16,S_RCB_MAXLEN) 920#define V_RCB_MAXLEN(x) _DD_MAKEVALUE(x,S_RCB_MAXLEN) 921#define G_RCB_MAXLEN(x) _DD_GETVALUE(x,S_RCB_MAXLEN,M_RCB_MAXLEN) 922 923 924/* On-chip Memory Map (Tables 70 and 71, pp 178-179) This is the map 925 for the 5700 with no external SRAM, the 5701, 5702 and 5703. The 926 5705 does not fully implement some ranges and maps the buffer pool 927 differently. */ 928 929/* Locations 0x0000 - 0x00FF are Page Zero */ 930 931/* Locations 0x0100 - 0x01FF are Send Producer Ring RCBs */ 932 933#define A_SND_RCBS 0x0100 934#define L_SND_RCBS (16*RCB_SIZE) 935#define A_SND_RCB(n) (A_SND_RCBS + ((n)-1)*RCB_SIZE) 936 937/* Locations 0x0200 - 0x02FF are Receive Return Ring RCBs */ 938 939#define A_RTN_RCBS 0x0200 940#define L_RTN_RCBS (16*RCB_SIZE) 941#define A_RTN_RCB(n) (A_RTN_RCBS + ((n)-1)*RCB_SIZE) 942 943/* Locations 0x0300 - 0x0AFF are Statistics Block */ 944 945#define A_MAC_STATS 0x0300 946#define L_MAC_STATS (0x0B00-A_MAC_STATS) 947 948/* Locations 0x0B00 - 0x0B4F are Status Block */ 949 950#define A_MAC_STATUS 0x0B00 951#define L_MAC_STATUS (0x0B50-A_MAC_STATUS) 952 953/* Locations 0x0B50 - 0x0FFF are Software General Communication */ 954 955#define A_PXE_MAILBOX 0x0B50 956#define T3_MAGIC_NUMBER 0x4B657654 957 958/* Locations 0x1000 - 0x1FFF are unmapped */ 959 960/* Locations 0x2000 - 0x3FFF are DMA Descriptors */ 961 962#define A_DMA_DESCS 0x2000 963#define L_DMA_DESCS (0x4000-A_DMA_DESCS) 964 965/* Locations 0x4000 - 0x5FFF are Send Rings 1-4 */ 966 967#define A_SND_RINGS 0x4000 968#define L_SND_RINGS (0x6000-A_SND_RINGS) 969 970/* Locations 0x6000 - 0x6FFF are Standard Receive Rings */ 971 972#define A_STD_RCV_RINGS 0x6000 973#define L_STD_RCV_RINGS (0x7000-A_STD_RCV_RINGS) 974 975/* Locations 0x7000 - 0x7FFF are Jumbo Receive Rings */ 976 977#define A_JUMBO_RCV_RINGS 0x7000 978#define L_JUMBO_RCV_RINGS (0x8000-A_JUMBO_RCV_RINGS) 979 980/* Locations 0x08000 - 0x0FFFF are Buffer Pool 1 */ 981/* Locations 0x10000 - 0x17FFF are Buffer Pool 2 */ 982/* Locations 0x18000 - 0x1FFFF are Buffer Pool 3 */ 983 984#define A_BUFFER_POOL 0x08000 985#define L_BUFFER_POOL (0x20000-A_BUFFER_POOL) 986 987/* Locations 0x08000 - 0x09FFF are TXMBUF (5705) */ 988/* Locations 0x10000 - 0x1DFFF are RXMBUF (5705) */ 989 990#define A_TXMBUF 0x08000 991#define L_TXMBUF (0x0A000-A_TXMBUF) 992#define A_RXMBUF 0x10000 993#define L_RXMBUF (0x1E000-A_RXMBUF) 994 995 996/* Indices of (8-byte) counters in the Statistics Block. */ 997 998#define ifHCInOctets 32 999#define etherStatsFragments 34 1000#define ifHCInUcastPkts 35 1001#define ifHCInMulticastPkts 36 1002#define ifHCInBroadcastPkts 37 1003#define dot3StatsFCSErrors 38 1004#define dot3StatsAlignmentErrors 39 1005#define xonPauseFramesReceived 40 1006#define xoffPauseFramesReceived 41 1007#define macControlFramesReceived 42 1008#define xoffSateEntered 43 1009#define dot3StatsFrameTooLongs 44 1010#define etherStatsJabbers 45 1011#define etherStatsUndersizePkts 46 1012#define inRangeLengthError 47 1013#define outRangeLengthError 48 1014#define etherStatsPkts64Octets 49 1015#define etherStatsPkts65to127Octets 50 1016#define etherStatsPkts128to255Octets 51 1017#define etherStatsPkts256to511Octets 52 1018#define etherStatsPkts512to1023Octets 53 1019#define etherStatsPkts1024to1522Octets 54 1020#define etherStatsPkts1523to2047Octets 55 1021#define etherStatsPkts2048to4095Octets 56 1022#define etherStatsPkts4096to8191Octets 57 1023#define etherStatsPkts8192to9022Octets 58 1024 1025#define ifHCOutOctets 96 1026#define etherStatsCollisions 98 1027#define outXonSent 99 1028#define outXoffSent 100 1029#define flowControlDone 101 1030#define dot3StatsInternalMacTransmitErrors 102 1031#define dot3StatsSingleCollisionFrames 103 1032#define dot3StatsMultipleCollisionFrames 104 1033#define dot3StatsDeferredTransmissions 105 1034#define dot3StatsExcessiveCollisions 107 1035#define dot3StatsLateCollisions 108 1036#define dot3Collided2Times 109 1037#define dot3Collided3Times 110 1038#define dot3Collided4Times 111 1039#define dot3Collided5Times 112 1040#define dot3Collided6Times 113 1041#define dot3Collided7Times 114 1042#define dot3Collided8Times 115 1043#define dot3Collided9Times 116 1044#define dot3Collided10Times 117 1045#define dot3Collided11Times 118 1046#define dot3Collided12Times 119 1047#define dot3Collided13Times 120 1048#define dot3Collided14Times 121 1049#define dot3Collided15Times 122 1050#define ifHCOutUcastPkts 123 1051#define ifHCOutMulticastPkts 124 1052#define ifHCOutBroadcastPkts 125 1053#define dot3StatsCarrierSenseErrors 126 1054#define ifOutDiscards 127 1055#define ifOutErrors 128 1056 1057#define COSifHCInPkts1 160 1058#define COSifHCInPkts2 161 1059#define COSifHCInPkts3 162 1060#define COSifHCInPkts4 163 1061#define COSifHCInPkts5 164 1062#define COSifHCInPkts6 165 1063#define COSifHCInPkts7 166 1064#define COSifHCInPkts8 167 1065#define COSifHCInPkts9 168 1066#define COSifHCInPkts10 169 1067#define COSifHCInPkts11 170 1068#define COSifHCInPkts12 171 1069#define COSifHCInPkts13 172 1070#define COSifHCInPkts14 173 1071#define COSifHCInPkts15 174 1072#define COSifHCInPkts16 175 1073#define COSFramesDroppedDueToFilters 176 1074#define nicDmaWriteQueueFull 177 1075#define nicDmaWriteHighPriQueueFull 178 1076#define nicNoMoreRxBDs 179 1077#define ifInDiscards 180 1078#define ifInErrors 181 1079#define nicRecvThresholdHit 182 1080 1081#define COSifHCOutPkts1 192 1082#define COSifHCOutPkts2 193 1083#define COSifHCOutPkts3 194 1084#define COSifHCOutPkts4 195 1085#define COSifHCOutPkts5 196 1086#define COSifHCOutPkts6 197 1087#define COSifHCOutPkts7 198 1088#define COSifHCOutPkts8 199 1089#define COSifHCOutPkts9 200 1090#define COSifHCOutPkts10 201 1091#define COSifHCOutPkts11 202 1092#define COSifHCOutPkts12 203 1093#define COSifHCOutPkts13 204 1094#define COSifHCOutPkts14 205 1095#define COSifHCOutPkts15 206 1096#define COSifHCOutPkts16 207 1097#define nicDmaReadQueueFull 208 1098#define nicDmaReadHighPriQueueFull 209 1099#define nicSendDataCompQueueFull 210 1100#define nicRingSetSendProdIndex 211 1101#define nicRingStatusUpdate 212 1102#define nicInterrupts 213 1103#define nicAvoidedInterrupts 214 1104#define nicSendThresholdHit 215 1105 1106#endif /* _BCM_5700_H_ */ 1107