1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * L2 Cache initialization File: sb1250_l2cache.S 5 * 6 * This module contains code to initialize the L2 cache. 7 * 8 * Note: all the routines in this module rely on registers only, 9 * since DRAM may not be active yet. 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50#include "sbmips.h" 51#include "mipsmacros.h" 52#include "sb1250_regs.h" 53#include "sb1250_l2c.h" 54#include "sb1250_mc.h" 55#include "sb1250_scd.h" 56#include "sb1250_wid.h" 57 58/* 59 * This lets us override the WID by poking values into our PromICE 60 */ 61#ifdef _MAGICWID_ 62#undef A_SCD_SYSTEM_REVISION 63#define A_SCD_SYSTEM_REVISION 0x1FC00508 64#endif 65 66 .text 67 .set mips64 68 69 70/* ********************************************************************* 71 * Macros 72 ********************************************************************* */ 73 74/*#define PHYS_TO_XKPHYS(x) (0x9000000000000000|(x))*/ 75#define CACHE_LINE_SIZE 32 76#define HAZARD ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop 77 78#define IF_BIN(binreg,binmask,label) \ 79 .set noat ; \ 80 andi AT,binreg,binmask ; \ 81 bne AT,zero,label ; \ 82 .set at 83 84/* In the WID register, 0=top/left, 1=bottom/left, 2=top/right, 3=bottom/right */ 85 86#define DISAB_TOP 0x800 87#define DISAB_BOT 0x400 88#define DISAB_RGT 0x200 89#define DISAB_LFT 0x100 90 91/* ********************************************************************* 92 * SB1250_L2CACHE_DISABTABLE 93 * 94 * This table maps the WID l2 diagnostic bits onto the disable 95 * mask for the L2 disable register. 96 * 97 * There are 8 entries in the table, with the index as followS: 98 * 99 * H WW 100 * 101 * H = 0 if only 1/4 of the cache is valid 102 * H = 1 if 1/2 of the cache is valid 103 * WW is the way number (or half number) that is valid 104 ********************************************************************* */ 105 106/* 107 * This is how the quadrant numbers are actually organized: 108 * 109 * 1 3 110 * 0 2 111 */ 112 113sb1250_l2cache_disabtable: 114 115 .word DISAB_LFT /* Good=0(right) Disable: left */ 116 .word DISAB_LFT /* Good=1(right) Disable: left */ 117 .word DISAB_RGT /* Good=2(left) Disable: right */ 118 .word DISAB_RGT /* Good=3(left) Disable: right */ 119 120 .word DISAB_RGT|DISAB_TOP /* Good=0(bot/left), Disable: top,right */ 121 .word DISAB_RGT|DISAB_BOT /* Good=1(top/left), Disable: bottom,right */ 122 .word DISAB_LFT|DISAB_TOP /* Good=2(bot/right), Disable: top,left */ 123 .word DISAB_LFT|DISAB_BOT /* Good=3(top/right), Disable: bottom,left */ 124 125 126// Old table for historical value, when we 127// thought the quadrant numbers were: 128// 129// 0 2 130// 1 3 131// 132// .word DISAB_RGT|DISAB_BOT /* Good=0(top/left), Disable: right,bottom */ 133// .word DISAB_RGT|DISAB_TOP /* Good=1(bot/left), Disable: right,top */ 134// .word DISAB_LFT|DISAB_BOT /* Good=2(top/right), Disable: left,bottom */ 135// .word DISAB_LFT|DISAB_TOP /* Good=3(bot/right), Disable: left,top */ 136 137 138/* ********************************************************************* 139 * SB1250_L2CACHE_INIT() 140 * 141 * Initialize the L2 Cache tags to be "invalid" 142 * 143 * Input parameters: 144 * nothing 145 * 146 * Return value: 147 * nothing 148 * 149 * Registers used: 150 * t0,t1,t2 151 ********************************************************************* */ 152 153 154LEAF(sb1250_l2cache_init) 155 156 # Do nothing (return immediately) if L2 has been disabled via JTAG. 157 158 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG) 159 ld t0, 0(t0) 160 and t0, t0, M_SYS_L2C_RESET 161 beq zero, t0, 1f 162 jr ra 1631: 164 165 # Save the old status register, and set the KX bit. 166 167 mfc0 t2,C0_SR 168 or t1,t2,M_SR_KX 169 mtc0 t1,C0_SR 170 HAZARD 171 172 # Start the index at the base of the cache management 173 # area, but leave the address bit for "Valid" zero. 174 # Note that the management tags are at 00_D000_0000, 175 # which cannot be expressed with the PHYS_TO_K1 macro, 176 # so well need to use a 64-bit address to get to it. 177 178 dli t0,PHYS_TO_XKSEG_UNCACHED(A_L2C_MGMT_TAG_BASE) 179 180 # Loop through each entry and each way 181 182#ifdef _FASTINIT_ 183 li t1,16 184#else 185 li t1,L2C_ENTRIES_PER_WAY*L2C_NUM_WAYS 186#endif 187 188 189 # Write a zero to the cache management register at each 190 # address. 191 192 .align 4 1931: sd zero,0(t0) 194 sd zero,CACHE_LINE_SIZE(t0) 195 sd zero,2*CACHE_LINE_SIZE(t0) 196 sd zero,3*CACHE_LINE_SIZE(t0) 197 daddu t0,(4*CACHE_LINE_SIZE) # size of a cache line 198 subu t1,4 199 bne t1,0,1b 200 201 # 202 # Restore old KX bit setting 203 # 204 205 mtc0 t2,C0_SR 206 HAZARD 207 208 209 /* 210 * Test to see if we're running on a pre-production part with 211 * a defective L1 cache. We store information in the SCD 212 * SYSTEM_REVISION register that identifies what is 213 * going on. 214 */ 215 216 /* 217 * First, check the part number 218 */ 219 220 li t0,PHYS_TO_K1(A_SCD_SYSTEM_REVISION) 221 ld t1,0(t0) /* get SYSTEM_REVISION */ 222 223 dsrl t1,t1,S_SYS_PART 224 andi t1,t1,(M_SYS_PART >> S_SYS_PART) 225 226 beq t1,0x1250,sb1250_l2cache_check_rev /* Go if real 1250 */ 227 beq t1,0x1150,sb1250_l2cache_check_rev /* or 1250 in uni-cpu mode */ 228 b sb1250_l2cache_init_good /* otherwise not a 1250, no WID check */ 229 230 /* 231 * Now, check the revision. Anything earlier than step A3 232 * does not need this check. Pass 3 does not need this check also. 233 * 234 * Exception: Step A6 parts return 0x04 in their revision field. 235 * These parts can can be verified as A6 by having a nonzero WID. 236 */ 237 238sb1250_l2cache_check_rev: 239 ld t1,0(t0) /* get the SYSTEM_REVISION again */ 240 dsrl t1,t1,S_SYS_REVISION 241 andi t1,t1,(M_SYS_REVISION >> S_SYS_REVISION) 242 beq t1,0x04,sb1250_l2cache_check_wid 243 blt t1,0x05,sb1250_l2cache_init_good 244 bge t1,0x20,sb1250_l2cache_init_good 245 246 /* 247 * Okay, we really need to check the WID now. If the WID is 248 * not programmed at all, assume the part is good. 249 * (yes, this includes the wafer/lot bits) 250 */ 251 252sb1250_l2cache_check_wid: 253 ld t1,0(t0) /* Get the WID bits back */ 254 dsrl t1,t1,S_SYS_WID /* wafer ID to bits 0..31 */ 255 li t2,(M_SYS_WID >> S_SYS_WID) 256 and t1,t1,t2 257 258 WID_UNCONVOLUTE(t1,t2,t3,t4) 259 260 beq t1,zero,sb1250_l2cache_init_good 261 262 /* 263 * Get the bin number from the WID. This tells us many things. 264 * For the L1 cache we need to know which ways to use, 265 * and this is determined by what we put in the tag registers. 266 */ 267 268 andi t0,t1,M_WID_BIN /* bin # into T0 */ 269 li t2,1 /* make a bitmask */ 270 sll t0,t2,t0 /* put '1' in correct place */ 271 272 /* 273 * t0 now contains a single bit set corresponding to the bin number 274 * that this chip belongs to. 275 * for example, if it is in bin 4, then the value is 1<<4 276 */ 277 278 /* 279 * Check for the case of a fully operational cache. 280 */ 281 282 IF_BIN(t0,M_WID_BIN_F2,sb1250_l2cache_init_good) 283 284 /* 285 * Get the WID register again and isolate the L2 cache bits. Combine 286 * this with the "1/2" attribute in the bin bitmask to form the 287 * offset of our table. 288 */ 289 290 li t1,PHYS_TO_K1(A_SCD_SYSTEM_REVISION) 291 ld t1,0(t1) 292 dsrl t1,t1,S_SYS_WID /* get WID bits */ 293 294 WID_UNCONVOLUTE(t1,t2,t3,t4) 295 296 dsrl t1,t1,S_WID_L2QTR 297 andi t1,t1,(M_WID_L2QTR >> S_WID_L2QTR) 298 299 IF_BIN(t0,M_WID_BIN_H2,1f) 300 ori t1,t1,0x04 /* t1 = index into table */ 3011: 302 303 sll t1,2 /* make 32-bit offset */ 304 305 move t2,ra 306 LOADREL(t0,sb1250_l2cache_disabtable) 307 or t0,K1BASE 308 move ra,t2 /* get address of table */ 309 310 add t0,t0,t1 /* t0 = address of element in table */ 311 lw t0,0(t0) /* t0 = address for WAY_DISABLE */ 312 li t1,PHYS_TO_K1(A_L2_CACHE_DISABLE) /* Quadrant disable */ 313 or t1,t1,t0 /* OR in the address bits */ 314 315 sd t0,0(t1) /* do the memory reference */ 316 317 318sb1250_l2cache_init_good: 319 j ra # return to caller 320 321END(sb1250_l2cache_init) 322 323 324/* ********************************************************************* 325 * SB1250_L2CACHE_DISABLE() 326 * 327 * Convert the entire L2 Cache into static memory, for use by 328 * the bootstrap loader. Actually, it only removes three of the 329 * ways, since you must leave at least one way active at all 330 * times. 331 * 332 * Input parameters: 333 * nothing 334 * 335 * Return value: 336 * nothing 337 * 338 * Registers used: 339 * t0,t1 340 ********************************************************************* */ 341 342 343LEAF(sb1250_l2cache_disable) 344 345 # Do nothing (return immediately) if L2 has been disabled via JTAG. 346 347 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG) 348 ld t0, 0(t0) 349 and t0, t0, M_SYS_L2C_RESET 350 beq zero, t0, 1f 351 jr ra 3521: 353 354 # Save the old status register, and set the KX bit. 355 # Configure the L2 cache as SRAM (all ways disabled except one) 356 # Do a memory reference at the "way_disable" address 357 # to switch it off. 358 # Warning: do NOT try to configure all of the ways off - you 359 # must leave at least one way active! This code leaves 360 # way #3 active and gives ways 0..2 to the program. 361 362 li t0,PHYS_TO_K1(A_L2_MAKEDISABLE(0x07)) 363 ld t0,(t0) 364 365 # Use the result of the load to stall the pipe here. 366 # Ref sec 5.4.2 367 # XXX is this necessary for global enable/disable operations? 368 369 addu t0,t0,t0 370 371 # Re-write all the tags 372 373 b sb1250_l2cache_init 374 375END(sb1250_l2cache_disable) 376 377 378/* ********************************************************************* 379 * SB1250_L2CACHE_ENABLE() 380 * 381 * Convert the L2 Cache memory into the actual L2 cache, enabling 382 * the cache for future memory accesses. 383 * 384 * Input parameters: 385 * nothing 386 * 387 * Return value: 388 * nothing 389 * 390 * Registers used: 391 * t0,t1 392 ********************************************************************* */ 393 394LEAF(sb1250_l2cache_enable) 395 396 # Do nothing (return immediately) if L2 has been disabled via JTAG. 397 398 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG) 399 ld t0, 0(t0) 400 and t0, t0, M_SYS_L2C_RESET 401 beq zero, t0, 1f 402 jr ra 4031: 404 405 # Save the old status register, and set the KX bit. 406 # Configure the L2 cache as Cache (all ways enabled) 407 # Do a memory reference at the "way_disable" address 408 # to switch it on. 409 410 li t0,PHYS_TO_K1(A_L2_MAKEDISABLE(0x0)) 411 ld t0,(t0) 412 413 # Use the result of the load to stall the pipe here. 414 # Ref sec 5.4.2 415 # XXX is this necessary for global enable/disable operations? 416 417 addu t0,t0,t0 418 419 # Re-write all the tags 420 421 b sb1250_l2cache_init 422 423END(sb1250_l2cache_enable) 424 425 426/* ********************************************************************* 427 * SB1250_L2CACHE_FLUSH() 428 * 429 * Flush the entire L2 cache. All dirty lines are written back 430 * out to memory. 431 * 432 * Input parameters: 433 * nothing 434 * 435 * Return value: 436 * v0 - number of lines flushed 437 * 438 * Registers used: 439 * t0,t1,t2,t3,t4,t5,t6,t7,a0,s1,s2,s3,s4 440 ********************************************************************* */ 441 442LEAF(sb1250_l2cache_flush) 443 444 # Do nothing (return immediately) if L2 has been disabled via JTAG. 445 446 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG) 447 ld t0, 0(t0) 448 and t0, t0, M_SYS_L2C_RESET 449 beq zero, t0, 1f 450 jr ra 4511: 452 453 # Save the old status register, and set the KX bit. 454 455 mfc0 a0,C0_SR 456 or t1,a0,M_SR_KX 457 mtc0 t1,C0_SR 458 HAZARD 459 460 # 461 # Set the BERR bits in both memory controllers. We're 462 # going to do cacheable reads where there is no memory. 463 # 464 # 465 # Note that on an 1125, we can still do this on MC 0 even 466 # though there is only one memory controller. The register 467 # is there, it just ignores the bits we're trying to write. 468 # 469 470 li t0,PHYS_TO_K1(A_MC_REGISTER(0,R_MC_CONFIG)) 471 ld t6,0(t0) 472 dli t1,(M_MC_BERR_DISABLE | M_MC_ECC_DISABLE) 473 or t1,t1,t6 474 sd t1,0(t0) 475 476 li t0,PHYS_TO_K1(A_MC_REGISTER(1,R_MC_CONFIG)) 477 ld t7,0(t0) 478 dli t1,(M_MC_BERR_DISABLE | M_MC_ECC_DISABLE) 479 or t1,t1,t7 480 sd t1,0(t0) 481 482 # Start the index at the base of the cache management area. 483 # Note that the management tags are at 00_D000_0000, 484 # which cannot be expressed with the PHYS_TO_K1 macro, 485 # so well need to use a 64-bit address to get to it. 486 487 # Set up the common values which may be massaged by WID info 488 489 li s1,PHYS_TO_K1(A_L2_READ_ADDRESS) 490 li s2,L2C_NUM_WAYS 491 492 dli s3,PHYS_TO_XKSEG_UNCACHED(A_L2C_MGMT_TAG_BASE) 493 move v0,zero 494 495 /* 496 * Test to see if we're running on a pre-production part with 497 * a defective L1 cache. We store information in the SCD 498 * SYSTEM_REVISION register that identifies what is 499 * going on. 500 */ 501 502 /* 503 * First, check the part number 504 */ 505 506 li t0,PHYS_TO_K1(A_SCD_SYSTEM_REVISION) 507 ld t1,0(t0) /* get SYSTEM_REVISION */ 508 509 dsrl t1,t1,S_SYS_PART 510 andi t1,t1,(M_SYS_PART >> S_SYS_PART) 511 512 beq t1,0x1250,1f /* Go if real 1250 */ 513 beq t1,0x1150,1f /* or 1250 in uni-cpu mode */ 514 b l2f_full /* otherwise not a 1250, no WID check */ 515 516 /* 517 * Now, check the revision. Anything earlier than step A3 518 * does not need this check. 519 * 520 * Exception: Step A6 parts return 0x04 in their revision field. 521 * These parts can can be verified as A6 by having a nonzero WID. 522 */ 523 5241: ld t1,0(t0) /* get the SYSTEM_REVISION again */ 525 dsrl t1,t1,S_SYS_REVISION 526 andi t1,t1,(M_SYS_REVISION >> S_SYS_REVISION) 527 beq t1,0x04,1f 528 blt t1,0x05,l2f_full 529 530 /* 531 * Okay, we really need to check the WID now. If the WID is 532 * not programmed at all, assume the part is good. 533 * (yes, this includes the wafer/lot bits) 534 */ 535 5361: ld t1,0(t0) /* Get the WID bits back */ 537 dsrl t1,t1,S_SYS_WID /* wafer ID to bits 0..31 */ 538 li t2,(M_SYS_WID >> S_SYS_WID) 539 and t1,t1,t2 540 541 WID_UNCONVOLUTE(t1,t2,t3,t4) 542 543 beq t1,zero,l2f_full 544 545 /* 546 * Get the bin number from the WID. This tells us many things. 547 * For the L1 cache we need to know which ways to use, 548 * and this is determined by what we put in the tag registers. 549 */ 550 551 andi t0,t1,M_WID_BIN /* bin # into T0 */ 552 li t2,1 /* make a bitmask */ 553 sll t0,t2,t0 /* put '1' in correct place */ 554 555 /* 556 * t0 now contains a single bit set corresponding to the bin number 557 * that this chip belongs to. 558 * for example, if it is in bin 4, then the value is 1<<4 559 */ 560 561 /* 562 * Check for the case of a fully operational cache. 563 */ 564 565 IF_BIN(t0,M_WID_BIN_F2,l2f_full) 566 567 /* 568 * Get the WID register again and isolate the L2 cache bits. Combine 569 * this with the "1/2" attribute in the bin bitmask to form the 570 * offset of our table. 571 */ 572 573 li t1,PHYS_TO_K1(A_SCD_SYSTEM_REVISION) 574 ld t1,0(t1) 575 dsrl t1,t1,S_SYS_WID /* get WID bits */ 576 577 WID_UNCONVOLUTE(t1,t2,t3,t4) 578 579 dsrl t1,t1,S_WID_L2QTR 580 andi t1,t1,(M_WID_L2QTR >> S_WID_L2QTR) 581 582 IF_BIN(t0,M_WID_BIN_H2,l2f_half) 583 584l2f_quarter: li s4,L2C_ENTRIES_PER_WAY/4 585 dsll t1,S_L2C_MGMT_QUADRANT 586 daddu s3,t1 587 b 1f 588 589l2f_half: li s4,L2C_ENTRIES_PER_WAY/2 590 dsrl t1,1 591 xori t1,1 592 dsll t1,S_L2C_MGMT_HALF 593 daddu s3,t1 594 b 1f 595 596l2f_full: li s4,L2C_ENTRIES_PER_WAY 597 598 # Loop through each entry and each way 599 6001: move t1,s4 601 move t0,s3 602 603 # Do a read at the cache management address to set the 604 # A_L2_READ_TAG register. 605 6062: ld t3,0(t0) # this sets the register. 607 daddu t3,t3,0 # Do an ALU op to ensure ordering 608 ld t4,0(s1) # Get the tag 609 li t5,M_L2C_TAG_DIRTY 610 and t5,t4,t5 # Test the dirty bit 611 beq t5,zero,3f # don't flush this line 612 613 # 614 # The way that we're looking at now will be the victim, so all we 615 # need to do is a cacheable read at any address that does *not* 616 # match this tag. To do this, we're going to OR in some bits 617 # into the physical address to put it way outside the memory area. 618 # Then do a cacheable read. The current way will be replaced 619 # with the garbage data. We'll pick PA 30_0000_0000 in the middle 620 # of the 520GB memory expansion area for this purpose. 621 # 622 623 add v0,1 # count this line (debug) 624 625 dli t5,(M_L2C_TAG_TAG|M_L2C_TAG_INDEX) 626 and t4,t4,t5 # Have a physical address 627 dli t5,PHYS_TO_XKSEG_CACHED(0x3000000000) 628 or t4,t4,t5 629 ld t4,0(t4) # Do a read. 630 daddu t4,1 # Use it in an ALU op. 631 632 6333: daddu t0,CACHE_LINE_SIZE # size of a cache line 634 subu t1,1 635 bne t1,0,2b 636 637 daddu s3,V_L2C_MGMT_WAY(1) 638 subu s2,1 639 bne s2,0,1b 640 641 642 # 643 # Now, reinit the entire cache. Of course, we could just 644 # reinit the lines we flushed, but this routine is mucking 645 # the entire cache anyway, so it doesn't matter. 646 # 647 648 649 dli t0,PHYS_TO_XKSEG_UNCACHED(A_L2C_MGMT_TAG_BASE) 650 li t1,L2C_ENTRIES_PER_WAY*L2C_NUM_WAYS 651 652 # Write a zero to the cache management register at each 653 # address. 654 6551: sd zero,0(t0) 656 sd zero,CACHE_LINE_SIZE(t0) 657 sd zero,2*CACHE_LINE_SIZE(t0) 658 sd zero,3*CACHE_LINE_SIZE(t0) 659 daddu t0,(4*CACHE_LINE_SIZE) # size of a cache line 660 subu t1,4 661 bne t1,0,1b 662 663 # 664 # Restore the old MC register values 665 # 666 667 668 li t0,PHYS_TO_K1(A_MC_REGISTER(0,R_MC_CONFIG)) 669 sd t6,0(t0) 670 671 li t0,PHYS_TO_K1(A_MC_REGISTER(1,R_MC_CONFIG)) 672 sd t7,0(t0) 673 674 # 675 # Restore old KX bit setting 676 # 677 678 mtc0 a0,C0_SR 679 HAZARD 680 681 j ra # return to caller 682 683END(sb1250_l2cache_flush) 684 685 686 687 688/* ********************************************************************* 689 * End 690 ********************************************************************* */ 691