1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MIPS64 CPU definitions File: sbmips.h 5 * 6 * This module contains constants and macros specific to the 7 * SB1 MIPS64 core. 8 * 9 * Author: Mitch Lichtenberg (mitch@sibyte.com) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48#ifndef _SB_MIPS_H 49#define _SB_MIPS_H 50 51/* ********************************************************************* 52 * Configure language 53 ********************************************************************* */ 54 55#if defined(__ASSEMBLER__) 56#define _ATYPE_ 57#define _ATYPE32_ 58#define _ATYPE64_ 59#else 60#define _ATYPE_ (__SIZE_TYPE__) 61#define _ATYPE32_ (int) 62#define _ATYPE64_ (long long) 63#endif 64 65 66/* ********************************************************************* 67 * Bitfield macros 68 ********************************************************************* */ 69 70/* 71 * Make a mask for 1 bit at position 'n' 72 */ 73 74#define _MM_MAKEMASK1(n) (1 << (n)) 75 76/* 77 * Make a mask for 'v' bits at position 'n' 78 */ 79 80#define _MM_MAKEMASK(v,n) (((1<<(v))-1) << (n)) 81 82/* 83 * Make a value at 'v' at bit position 'n' 84 */ 85 86#define _MM_MAKEVALUE(v,n) ((v) << (n)) 87 88/* 89 * Retrieve a value from 'v' at bit position 'n' with 'm' mask bits 90 */ 91 92#define _MM_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 93 94 95 96/* ********************************************************************* 97 * 32-bit MIPS Address Spaces 98 ********************************************************************* */ 99 100#ifdef __ASSEMBLER__ 101#define _ACAST32_ 102#define _ACAST64_ 103#else 104#define _ACAST32_ _ATYPE_ _ATYPE32_ /* widen if necessary */ 105#define _ACAST64_ _ATYPE64_ /* do _not_ narrow */ 106#endif 107 108/* 32-bit address map */ 109#define UBASE 0x00000000 /* user+ mapped */ 110#define USIZE 0x80000000 111#define K0BASE (_ACAST32_ 0x80000000) /* kernel unmapped cached */ 112#define K0SIZE 0x20000000 113#define K1BASE (_ACAST32_ 0xa0000000) /* kernel unmapped uncached */ 114#define K1SIZE 0x20000000 115#define KSBASE (_ACAST32_ 0xc0000000) /* supervisor+ mapped */ 116#define KSSIZE 0x20000000 117#define K3BASE (_ACAST32_ 0xe0000000) /* kernel mapped */ 118#define K3SIZE 0x20000000 119 120/* 64-bit address map additions to the above (sign-extended) ranges */ 121#define XUBASE (_ACAST64_ 0x0000000080000000) /* user+ mapped */ 122#define XUSIZE (_ACAST64_ 0x00000FFF80000000) 123#define XSSEGBASE (_ACAST64_ 0x4000000000000000) /* supervisor+ mapped */ 124#define XSSEGSIZE (_ACAST64_ 0x0000100000000000) 125#define XKPHYSBASE (_ACAST64_ 0x8000000000000000) /* kernel unmapped */ 126#define XKPHYSSIZE (_ACAST64_ 0x0000100000000000) 127#define XKSEGBASE (_ACAST64_ 0xC000000000000000) /* kernel mapped */ 128#define XKSEGSIZE (_ACAST64_ 0x00000FFF80000000) 129 130#define GEN_VECT (_ACAST32_ 0x80000080) 131#define UTLB_VECT (_ACAST32_ 0x80000000) 132 133/* ********************************************************************* 134 * Address space coercion macros 135 ********************************************************************* */ 136 137#define PHYS_TO_K0(pa) (K0BASE | (pa)) 138#define PHYS_TO_K1(pa) (K1BASE | (pa)) 139#define K0_TO_PHYS(va) ((va) & (K0SIZE-1)) 140#define K1_TO_PHYS(va) ((va) & (K1SIZE-1)) 141#define K0_TO_K1(va) ((va) | K1SIZE) 142#define K1_TO_K0(va) ((va) & ~K1SIZE) 143 144#define PHYS_TO_XK1(p) (_ACAST64_ (0xffffffffa0000000 | (p))) 145#define XK1_TO_PHYS(p) ((p) & (K1SIZE-1)) 146#define PHYS_TO_XKPHYS(cca,p) (_SB_MAKEMASK1(63) | (_SB_MAKE64(cca) << 59) | (p)) 147#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 148#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) 149#define XKPHYS_TO_PHYS(p) ((p) & _SB_MAKEMASK(0,59)) 150 151 152#if !defined(__ASSEMBLER__) 153#define mips_wbflush() __asm__ __volatile__ ("sync" : : : "memory") 154#define ISK0SEG(va) ((va) >= K0BASE && (va) <= (K0BASE + K0SIZE - 1)) 155#define ISK1SEG(va) ((va) >= K1BASE && (va) <= (K1BASE + K1SIZE - 1)) 156#endif 157 158/* ********************************************************************* 159 * Register aliases 160 ********************************************************************* */ 161 162#if defined(__ASSEMBLER__) 163#define zero $0 164#define AT $1 /* assembler temporaries */ 165#define v0 $2 /* value holders */ 166#define v1 $3 167#define a0 $4 /* arguments */ 168#define a1 $5 169#define a2 $6 170#define a3 $7 171#define t0 $8 /* temporaries */ 172#define t1 $9 173#define t2 $10 174#define t3 $11 175#define t4 $12 176#define t5 $13 177#define t6 $14 178#define t7 $15 179#define ta0 $12 180#define ta1 $13 181#define ta2 $14 182#define ta3 $15 183#define s0 $16 /* saved registers */ 184#define s1 $17 185#define s2 $18 186#define s3 $19 187#define s4 $20 188#define s5 $21 189#define s6 $22 190#define s7 $23 191#define t8 $24 /* temporaries */ 192#define t9 $25 193#define k0 $26 /* kernel registers */ 194#define k1 $27 195#define gp $28 /* global pointer */ 196#define sp $29 /* stack pointer */ 197#define s8 $30 /* saved register */ 198#define fp $30 /* frame pointer */ 199#define ra $31 /* return address */ 200#endif 201 202/* ********************************************************************* 203 * CP0 Registers 204 ********************************************************************* */ 205 206#if defined(__ASSEMBLER__) 207#define C0_INX $0 /* CP0: TLB Index */ 208#define C0_RAND $1 /* CP0: TLB Random */ 209#define C0_TLBLO0 $2 /* CP0: TLB EntryLo0 */ 210#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ 211#define C0_TLBLO1 $3 /* CP0: TLB EntryLo1 */ 212#define C0_CTEXT $4 /* CP0: Context */ 213#define C0_PGMASK $5 /* CP0: TLB PageMask */ 214#define C0_WIRED $6 /* CP0: TLB Wired */ 215#define C0_BADVADDR $8 /* CP0: Bad Virtual Address */ 216#define C0_COUNT $9 /* CP0: Count */ 217#define C0_TLBHI $10 /* CP0: TLB EntryHi */ 218#define C0_COMPARE $11 /* CP0: Compare */ 219#define C0_SR $12 /* CP0: Processor Status */ 220#define C0_STATUS C0_SR /* CP0: Processor Status */ 221#define C0_CAUSE $13 /* CP0: Exception Cause */ 222#define C0_EPC $14 /* CP0: Exception PC */ 223#define C0_PRID $15 /* CP0: Processor Revision Indentifier */ 224#define C0_CONFIG $16 /* CP0: Config */ 225#define C0_LLADDR $17 /* CP0: LLAddr */ 226#define C0_WATCHLO $18 /* CP0: WatchpointLo */ 227#define C0_WATCHHI $19 /* CP0: WatchpointHi */ 228#define C0_XCTEXT $20 /* CP0: XContext */ 229#define C0_DIAGNOSTIC $22 /* CP0: Diagnostic */ 230#define C0_ECC $26 /* CP0: ECC */ 231#define C0_CACHEERR $27 /* CP0: CacheErr */ 232#define C0_TAGLO $28 /* CP0: TagLo */ 233#define C0_TAGHI $29 /* CP0: TagHi */ 234#define C0_ERREPC $30 /* CP0: ErrorEPC */ 235#else 236#define C0_INX 0 /* CP0: TLB Index */ 237#define C0_RAND 1 /* CP0: TLB Random */ 238#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */ 239#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ 240#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */ 241#define C0_CTEXT 4 /* CP0: Context */ 242#define C0_PGMASK 5 /* CP0: TLB PageMask */ 243#define C0_WIRED 6 /* CP0: TLB Wired */ 244#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */ 245#define C0_COUNT 9 /* CP0: Count */ 246#define C0_TLBHI 10 /* CP0: TLB EntryHi */ 247#define C0_COMPARE 11 /* CP0: Compare */ 248#define C0_SR 12 /* CP0: Processor Status */ 249#define C0_STATUS C0_SR /* CP0: Processor Status */ 250#define C0_CAUSE 13 /* CP0: Exception Cause */ 251#define C0_EPC 14 /* CP0: Exception PC */ 252#define C0_PRID 15 /* CP0: Processor Revision Indentifier */ 253#define C0_CONFIG 16 /* CP0: Config */ 254#define C0_LLADDR 17 /* CP0: LLAddr */ 255#define C0_WATCHLO 18 /* CP0: WatchpointLo */ 256#define C0_WATCHHI 19 /* CP0: WatchpointHi */ 257#define C0_XCTEXT 20 /* CP0: XContext */ 258#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */ 259#define C0_ECC 26 /* CP0: ECC */ 260#define C0_CACHEERR 27 /* CP0: CacheErr */ 261#define C0_TAGLO 28 /* CP0: TagLo */ 262#define C0_TAGHI 29 /* CP0: TagHi */ 263#define C0_ERREPC 30 /* CP0: ErrorEPC */ 264#endif 265 266/* ********************************************************************* 267 * CP1 (floating point) control registers 268 ********************************************************************* */ 269 270#define FPA_IRR 0 /* CP1: Implementation/Revision */ 271#define FPA_CSR 31 /* CP1: Control/Status */ 272 273/* ********************************************************************* 274 * Macros for generating assembly language routines 275 ********************************************************************* */ 276 277#if defined(__ASSEMBLER__) 278 279/* global leaf function (does not call other functions) */ 280#define LEAF(name) \ 281 .globl name; \ 282 .ent name; \ 283name: 284 285/* global alternate entry to (local or global) leaf function */ 286#define XLEAF(name) \ 287 .globl name; \ 288 .aent name; \ 289name: 290 291/* end of a global function */ 292#define END(name) \ 293 .size name,.-name; \ 294 .end name 295 296/* local leaf function (does not call other functions) */ 297#define SLEAF(name) \ 298 .ent name; \ 299name: 300 301/* local alternate entry to (local or global) leaf function */ 302#define SXLEAF(name) \ 303 .aent name; \ 304name: 305 306/* end of a local function */ 307#define SEND(name) \ 308 END(name) 309 310/* define & export a symbol */ 311#define EXPORT(name) \ 312 .globl name; \ 313name: 314 315/* import a symbol */ 316#define IMPORT(name, size) \ 317 .extern name,size 318 319/* define a zero-fill common block (BSS if not overridden) with a global name */ 320#define COMM(name,size) \ 321 .comm name,size 322 323/* define a zero-fill common block (BSS if not overridden) with a local name */ 324#define LCOMM(name,size) \ 325 .lcomm name,size 326 327#endif 328 329 330/* Floating-Point Control register bits */ 331#define CSR_C 0x00800000 332#define CSR_EXC 0x0003f000 333#define CSR_EE 0x00020000 334#define CSR_EV 0x00010000 335#define CSR_EZ 0x00008000 336#define CSR_EO 0x00004000 337#define CSR_EU 0x00002000 338#define CSR_EI 0x00001000 339#define CSR_TV 0x00000800 340#define CSR_TZ 0x00000400 341#define CSR_TO 0x00000200 342#define CSR_TU 0x00000100 343#define CSR_TI 0x00000080 344#define CSR_SV 0x00000040 345#define CSR_SZ 0x00000020 346#define CSR_SO 0x00000010 347#define CSR_SU 0x00000008 348#define CSR_SI 0x00000004 349#define CSR_RM 0x00000003 350 351/* Status Register */ 352#define M_SR_CUMASK _MM_MAKEMASK(4,28) /* coprocessor usable bits */ 353#define M_SR_CU3 _MM_MAKEMASK1(31) /* coprocessor 3 usable */ 354#define M_SR_CU2 _MM_MAKEMASK1(30) /* coprocessor 2 usable */ 355#define M_SR_CU1 _MM_MAKEMASK1(29) /* coprocessor 1 usable */ 356#define M_SR_CU0 _MM_MAKEMASK1(28) /* coprocessor 0 usable */ 357 358#define M_SR_RP _MM_MAKEMASK1(27) /* reduced power mode */ 359#define M_SR_FR _MM_MAKEMASK1(26) /* fpu regs any data */ 360#define M_SR_RE _MM_MAKEMASK1(25) /* reverse endian */ 361#define M_SR_MX _MM_MAKEMASK1(24) /* MDMX */ 362#define M_SR_PX _MM_MAKEMASK1(23) /* 64-bit ops in user mode */ 363#define M_SR_BEV _MM_MAKEMASK1(22) /* boot exception vectors */ 364#define M_SR_TS _MM_MAKEMASK1(21) /* TLB is shut down */ 365#define M_SR_SR _MM_MAKEMASK1(20) /* soft reset */ 366#define M_SR_NMI _MM_MAKEMASK1(19) /* nonmaskable interrupt */ 367 368#define M_SR_IMASK _MM_MAKEMASK(8,8) /* all interrupt mask bits */ 369 370#define M_SR_IBIT8 _MM_MAKEMASK1(15) /* individual bits */ 371#define M_SR_IBIT7 _MM_MAKEMASK1(14) 372#define M_SR_IBIT6 _MM_MAKEMASK1(13) 373#define M_SR_IBIT5 _MM_MAKEMASK1(12) 374#define M_SR_IBIT4 _MM_MAKEMASK1(11) 375#define M_SR_IBIT3 _MM_MAKEMASK1(10) 376#define M_SR_IBIT2 _MM_MAKEMASK1(9) 377#define M_SR_IBIT1 _MM_MAKEMASK1(8) 378 379#define M_SR_IMASK8 0 /* masks for nested int levels */ 380#define M_SR_IMASK7 _MM_MAKEMASK(1,15) 381#define M_SR_IMASK6 _MM_MAKEMASK(2,14) 382#define M_SR_IMASK5 _MM_MAKEMASK(3,13) 383#define M_SR_IMASK4 _MM_MAKEMASK(4,12) 384#define M_SR_IMASK3 _MM_MAKEMASK(5,11) 385#define M_SR_IMASK2 _MM_MAKEMASK(6,10) 386#define M_SR_IMASK1 _MM_MAKEMASK(7,9) 387#define M_SR_IMASK0 _MM_MAKEMASK(8,8) 388 389#define M_SR_KX _MM_MAKEMASK1(7) /* 64-bit access for kernel */ 390#define M_SR_SX _MM_MAKEMASK1(6) /* .. for supervisor */ 391#define M_SR_UX _MM_MAKEMASK1(5) /* .. for user */ 392 393#define S_SR_KSU 3 /* base operating mode mode */ 394#define M_SR_KSU _MM_MAKEMASK(2,S_SR_KSU) 395#define V_SR_KSU(x) _MM_MAKEVALUE(x,S_SR_KSU) 396#define G_SR_KSU(x) _MM_GETVALUE(x,S_SR_KSU,M_SR_KSU) 397#define K_SR_KSU_KERNEL 0 398#define K_SR_KSU_SUPR 1 399#define K_SR_KSU_USER 2 400 401#define M_SR_UM _MM_MAKEMASK1(4) 402#define M_SR_ERL _MM_MAKEMASK1(2) 403#define M_SR_EXL _MM_MAKEMASK1(1) 404#define M_SR_IE _MM_MAKEMASK1(0) 405 406/* 407 * Cause Register 408 */ 409#define M_CAUSE_BD _MM_MAKEMASK1(31) /* exception in BD slot */ 410 411#define S_CAUSE_CE 28 /* coprocessor error */ 412#define M_CAUSE_CE _MM_MAKEMASK(2,S_CAUSE_CE) 413#define V_CAUSE_CE(x) _MM_MAKEVALUE(x,S_CAUSE_CE) 414#define G_CAUSE_CE(x) _MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE) 415 416#define M_CAUSE_IV _MM_MAKEMASK1(23) /* special interrupt */ 417#define M_CAUSE_WP _MM_MAKEMASK1(22) /* watch interrupt deferred */ 418 419#define S_CAUSE_IPMASK 8 420#define M_CAUSE_IPMASK _MM_MAKEMASK(8,S_CAUSE_IPMASK) 421#define M_CAUSE_IP8 _MM_MAKEMASK1(15) /* hardware interrupts */ 422#define M_CAUSE_IP7 _MM_MAKEMASK1(14) 423#define M_CAUSE_IP6 _MM_MAKEMASK1(13) 424#define M_CAUSE_IP5 _MM_MAKEMASK1(12) 425#define M_CAUSE_IP4 _MM_MAKEMASK1(11) 426#define M_CAUSE_IP3 _MM_MAKEMASK1(10) 427#define M_CAUSE_SW2 _MM_MAKEMASK1(9) /* software interrupts */ 428#define M_CAUSE_SW1 _MM_MAKEMASK1(8) 429 430#define S_CAUSE_EXC 2 431#define M_CAUSE_EXC _MM_MAKEMASK(5,S_CAUSE_EXC) 432#define V_CAUSE_EXC(x) _MM_MAKEVALUE(x,S_CAUSE_EXC) 433#define G_CAUSE_EXC(x) _MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC) 434 435/* Exception Code */ 436#define K_CAUSE_EXC_INT 0 /* External interrupt */ 437#define K_CAUSE_EXC_MOD 1 /* TLB modification */ 438#define K_CAUSE_EXC_TLBL 2 /* TLB miss (Load or Ifetch) */ 439#define K_CAUSE_EXC_TLBS 3 /* TLB miss (Save) */ 440#define K_CAUSE_EXC_ADEL 4 /* Address error (Load or Ifetch) */ 441#define K_CAUSE_EXC_ADES 5 /* Address error (Save) */ 442#define K_CAUSE_EXC_IBE 6 /* Bus error (Ifetch) */ 443#define K_CAUSE_EXC_DBE 7 /* Bus error (data load or store) */ 444#define K_CAUSE_EXC_SYS 8 /* System call */ 445#define K_CAUSE_EXC_BP 9 /* Break point */ 446#define K_CAUSE_EXC_RI 10 /* Reserved instruction */ 447#define K_CAUSE_EXC_CPU 11 /* Coprocessor unusable */ 448#define K_CAUSE_EXC_OVF 12 /* Arithmetic overflow */ 449#define K_CAUSE_EXC_TRAP 13 /* Trap exception */ 450#define K_CAUSE_EXC_VCEI 14 /* Virtual Coherency Exception (I) */ 451#define K_CAUSE_EXC_FPE 15 /* Floating Point Exception */ 452#define K_CAUSE_EXC_CP2 16 /* Cp2 Exception */ 453#define K_CAUSE_EXC_WATCH 23 /* Watchpoint exception */ 454#define K_CAUSE_EXC_VCED 31 /* Virtual Coherency Exception (D) */ 455 456#define K_NTLBENTRIES 64 457 458#define HI_HALF(x) ((x) >> 16) 459#define LO_HALF(x) ((x) & 0xffff) 460 461/* FPU stuff */ 462 463#if defined(__ASSEMBLER__) 464#define C1_CSR $31 465#define C1_FRID $0 466#else 467#define C1_CSR 31 468#define C1_FRID 0 469#endif 470 471#define S_FCSR_CAUSE 12 472#define M_FCSR_CAUSE _MM_MAKEMASK(5,S_FCSR_CAUSE) 473#define V_FCSR_CAUSE(x) _MM_MAKEVALUE(x,S_FCSR_CAUSE) 474#define G_FCSR_CAUSE(x) _MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE) 475 476#define S_FCSR_ENABLES 7 477#define M_FCSR_ENABLES _MM_MAKEMASK(5,S_FCSR_ENABLES) 478#define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES) 479#define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES) 480 481#define S_FCSR_FLAGS 2 482#define M_FCSR_FLAGS _MM_MAKEMASK(5,S_FCSR_FLAGS) 483#define V_FCSR_FLAGS(x) _MM_MAKEVALUE(x,S_FCSR_FLAGS) 484#define G_FCSR_FLAGS(x) _MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS) 485 486 487/* 488 * MIPS64 Config Register (select 0) 489 */ 490#define M_CFG_CFG1 _MM_MAKEMASK1(31) /* config1 select1 is impl */ 491#define M_CFG_BE _MM_MAKEMASK1(15) /* big-endian mode */ 492 493#define S_CFG_AT 13 /* Architecture Type */ 494#define M_CFG_AT _MM_MAKEMASK(2,S_CFG_AT) 495#define V_CFG_AT(x) _MM_MAKEVALUE(x,S_CFG_AT) 496#define G_CFG_AT(x) _MM_GETVALUE(x,S_CFG_AT,M_CFG_AT) 497#define K_CFG_AT_MIPS32 0 498#define K_CFG_AT_MIPS64_32 1 499#define K_CFG_AT_MIPS64 2 500 501#define S_CFG_AR 10 /* Architecture Revision */ 502#define M_CFG_AR _MM_MAKEMASK(3,S_CFG_AR) 503#define V_CFG_AR(x) _MM_MAKEVALUE(x,S_CFG_AR) 504#define G_CFG_AR(x) _MM_GETVALUE(x,S_CFG_AR,M_CFG_AR) 505#define K_CFG_AR_REV1 0 506 507#define S_CFG_MMU 7 /* MMU Type */ 508#define M_CFG_MMU _MM_MAKEMASK(3,S_CFG_MMU) 509#define V_CFG_MMU(x) _MM_MAKEVALUE(x,S_CFG_MMU) 510#define G_CFG_MMU(x) _MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU) 511#define K_CFG_MMU_NONE 0 512#define K_CFG_MMU_TLB 1 513#define K_CFG_MMU_BAT 2 514#define K_CFG_MMU_FIXED 3 515 516#define S_CFG_K0COH 0 /* K0seg coherency */ 517#define M_CFG_K0COH _MM_MAKEMASK(3,S_CFG_K0COH) 518#define V_CFG_K0COH(x) _MM_MAKEVALUE(x,S_CFG_K0COH) 519#define G_CFG_K0COH(x) _MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH) 520#define K_CFG_K0COH_UNCACHED 2 521#define K_CFG_K0COH_CACHEABLE 3 522#define K_CFG_K0COH_COHERENT 5 523 524/* 525 * MIPS64 Config Register (select 1) 526 */ 527 528#define M_CFG_CFG2 _MM_MAKEMASK1(31) /* config2 select2 is impl */ 529 530#define S_CFG_MMUSIZE 25 531#define M_CFG_MMUSIZE _MM_MAKEMASK(6,S_CFG_MMUSIZE) 532 533#define S_CFG_IS 22 534#define M_CFG_IS _MM_MAKEMASK(3,S_CFG_IS) 535#define V_CFG_IS(x) _MM_MAKEVALUE(x,S_CFG_IS) 536#define G_CFG_IS(x) _MM_GETVALUE(x,S_CFG_IS,M_CFG_IS) 537 538#define S_CFG_IL 19 539#define M_CFG_IL _MM_MAKEMASK(S_CFG_IL,3) 540#define V_CFG_IL(x) _MM_MAKEVALUE(x,S_CFG_IL) 541#define G_CFG_IL(x) _MM_GETVALUE(x,S_CFG_IL,M_CFG_IL) 542 543#define S_CFG_IA 16 544#define M_CFG_IA _MM_MAKEMASK(3,S_CFG_IA) 545#define V_CFG_IA(x) _MM_MAKEVALUE(x,S_CFG_IA) 546#define G_CFG_IA(x) _MM_GETVALUE(x,S_CFG_IA,M_CFG_IA) 547 548#define S_CFG_DS 13 549#define M_CFG_DS _MM_MAKEMASK(3,S_CFG_DS) 550#define V_CFG_DS(x) _MM_MAKEVALUE(x,S_CFG_DS) 551#define G_CFG_DS(x) _MM_GETVALUE(x,S_CFG_DS,M_CFG_DS) 552 553#define S_CFG_DL 10 554#define M_CFG_DL _MM_MAKEMASK(3,S_CFG_DL) 555#define V_CFG_DL(x) _MM_MAKEVALUE(x,S_CFG_DL) 556#define G_CFG_DL(x) _MM_GETVALUE(x,S_CFG_DL,M_CFG_DL) 557 558#define S_CFG_DA 7 559#define M_CFG_DA _MM_MAKEMASK(3,S_CFG_DA) 560#define V_CFG_DA(x) _MM_MAKEVALUE(x,S_CFG_DA) 561#define G_CFG_DA(x) _MM_GETVALUE(x,S_CFG_DA,M_CFG_DA) 562 563#define M_CFG_PC _MM_MAKEMASK1(4) /* perf ctrs present */ 564#define M_CFG_WR _MM_MAKEMASK1(3) /* watch regs present */ 565#define M_CFG_CA _MM_MAKEMASK1(2) /* MIPS16 present */ 566#define M_CFG_EP _MM_MAKEMASK1(1) /* EJTAG present */ 567#define M_CFG_FP _MM_MAKEMASK1(0) /* FPU present */ 568 569 570 571/* 572 * Primary Cache TagLo 573 */ 574 575#define S_TAGLO_PTAG 8 576#define M_TAGLO_PTAG _MM_MAKEMASK(56,S_TAGLO_PTAG) 577 578#define S_TAGLO_PSTATE 6 579#define M_TAGLO_PSTATE _MM_MAKEMASK(2,S_TAGLO_PSTATE) 580#define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE) 581#define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE) 582#define K_TAGLO_PSTATE_INVAL 0 583#define K_TAGLO_PSTATE_SHARED 1 584#define K_TAGLO_PSTATE_CLEAN_EXCL 2 585#define K_TAGLO_PSTATE_DIRTY_EXCL 3 586 587#define M_TAGLO_LOCK _MM_MAKEMASK1(5) 588#define M_TAGLO_PARITY _MM_MAKEMASK1(0) 589 590 591/* 592 * CP0 CacheErr register 593 */ 594#define M_CERR_DATA _MM_MAKEMASK1(31) /* err in D space */ 595#define M_CERR_SCACHE _MM_MAKEMASK1(30) /* err in l2, not l1 */ 596#define M_CERR_DERR _MM_MAKEMASK1(29) /* data error */ 597#define M_CERR_TERR _MM_MAKEMASK1(28) /* tag error */ 598#define M_CERR_EXTRQ _MM_MAKEMASK1(27) /* external req caused err */ 599#define M_CERR_BPAR _MM_MAKEMASK1(26) /* bus parity err */ 600#define M_CERR_ADATA _MM_MAKEMASK1(25) /* additional data */ 601#define M_CERR_IDX _MM_MAKEMASK(22,0) 602 603 604 605/* 606 * Primary Cache operations 607 */ 608#define Index_Invalidate_I 0x0 /* 0 0 */ 609#define Index_Writeback_Inv_D 0x1 /* 0 1 */ 610#define Index_Invalidate_SI 0x2 /* 0 2 */ 611#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ 612#define Index_Load_Tag_I 0x4 /* 1 0 */ 613#define Index_Load_Tag_D 0x5 /* 1 1 */ 614#define Index_Load_Tag_SI 0x6 /* 1 2 */ 615#define Index_Load_Tag_SD 0x7 /* 1 3 */ 616#define Index_Store_Tag_I 0x8 /* 2 0 */ 617#define Index_Store_Tag_D 0x9 /* 2 1 */ 618#define Index_Store_Tag_SI 0xA /* 2 2 */ 619#define Index_Store_Tag_SD 0xB /* 2 3 */ 620#define Create_Dirty_Exc_D 0xD /* 3 1 */ 621#define Create_Dirty_Exc_SD 0xF /* 3 3 */ 622#define Hit_Invalidate_I 0x10 /* 4 0 */ 623#define Hit_Invalidate_D 0x11 /* 4 1 */ 624#define Hit_Invalidate_SI 0x12 /* 4 2 */ 625#define Hit_Invalidate_SD 0x13 /* 4 3 */ 626#define Fill_I 0x14 /* 5 0 */ 627#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ 628#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ 629#define Hit_Writeback_I 0x18 /* 6 0 */ 630#define Hit_Writeback_D 0x19 /* 6 1 */ 631#define Hit_Writeback_SD 0x1B /* 6 3 */ 632#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ 633#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ 634 635/* Watchpoint Register */ 636#define M_WATCH_PA 0xfffffff8 637#define M_WATCH_R 0x00000002 638#define M_WATCH_W 0x00000001 639 640 641/* TLB entries */ 642#define M_TLBHI_ASID _MM_MAKEMASK(0,8) 643#define M_TLBHI_VPN2 _MM_MAKEMASK(27,13) 644 645#define M_TLBLO_G _MM_MAKEMASK1(0) 646#define M_TLBLO_V _MM_MAKEMASK1(1) 647#define M_TLBLO_D _MM_MAKEMASK1(2) 648 649#define S_TLBLO_CALG 3 650#define M_TLBLO_CALG _MM_MAKEMASK(3,S_TLBLO_CALG) 651#define V_TLBLO_CALG(x) _MM_MAKEVALUE(x,S_TLBLO_CALG) 652#define G_TLBLO_CALG(x) _MM_GETVALUE(x,S_TLBLO_CALG,M_TLBLO_CALG) 653 654#define K_CALG_COH_EXCL1_NOL2 0 655#define K_CALG_COH_SHRL1_NOL2 1 656#define K_CALG_UNCACHED 2 657#define K_CALG_NONCOHERENT 3 658#define K_CALG_COH_EXCL 4 659#define K_CALG_COH_SHAREABLE 5 660#define K_CALG_NOTUSED 6 661#define K_CALG_UNCACHED_ACCEL 7 662 663#define S_TLBLO_PFNMASK 6 664#define M_TLBLO_PFNMASK _MM_MAKEMASK(24,S_TLBLO_PFNMASK) 665#define V_TLBLO_PFNMASK(x) _MM_MAKEVALUE(x,S_TLBLO_PFNMASK) 666#define G_TLBLO_PFNMASK(x) _MM_GETVALUE(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK) 667 668 669 670#endif /* _SB_MIPS_H */ 671 672 673