/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/msm/ |
H A D | mdp_hw_init.c | 75 outpdw(MDP_BASE + 0x40800, 0x0); 76 outpdw(MDP_BASE + 0x40804, 0x151515); 77 outpdw(MDP_BASE + 0x40808, 0x1d1d1d); 78 outpdw(MDP_BASE + 0x4080c, 0x232323); 79 outpdw(MDP_BASE + 0x40810, 0x272727); 80 outpdw(MDP_BASE + 0x40814, 0x2b2b2b); 81 outpdw(MDP_BASE + 0x40818, 0x2f2f2f); 82 outpdw(MDP_BASE + 0x4081c, 0x333333); 83 outpdw(MDP_BASE + 0x40820, 0x363636); 84 outpdw(MDP_BASE [all...] |
H A D | mdp_ppp_v20.c | 185 MDP_OUTP(MDP_BASE + table[i].reg, table[i].val); 190 MDP_OUTP(MDP_BASE + 0x5fffc, 0x0); 191 MDP_OUTP(MDP_BASE + 0x50200, 0x7fc00000); 192 MDP_OUTP(MDP_BASE + 0x5fffc, 0x0); 193 MDP_OUTP(MDP_BASE + 0x50204, 0x7fc00000); 194 MDP_OUTP(MDP_BASE + 0x5fffc, 0x0); 195 MDP_OUTP(MDP_BASE + 0x50208, 0x7fc00000); 196 MDP_OUTP(MDP_BASE + 0x5fffc, 0x0); 197 MDP_OUTP(MDP_BASE + 0x5020c, 0x7fc00000); 198 MDP_OUTP(MDP_BASE [all...] |
H A D | mdp_cursor.c | 55 MDP_OUTP(MDP_BASE + 0x9004c, (img->dy << 16) | img->dx); 75 MDP_OUTP(MDP_BASE + 0x90044, (img->height << 16) | img->width); 76 MDP_OUTP(MDP_BASE + 0x90048, mfd->cursor_buf_phys); 80 MDP_OUTP(MDP_BASE + 0x90060, 82 (inp32(MDP_BASE + 0x90060) & 0x1)); 84 MDP_OUTP(MDP_BASE + 0x90064, (alpha << 24)); 85 MDP_OUTP(MDP_BASE + 0x90068, (0xffffff & img->bg_color)); 86 MDP_OUTP(MDP_BASE + 0x9006C, (0xffffff & img->bg_color)); 88 MDP_OUTP(MDP_BASE + 0x90064, 90 MDP_OUTP(MDP_BASE [all...] |
H A D | mdp_dma_lcdc.c | 165 MDP_OUTP(MDP_BASE + dma_base + 0x8, (uint32) buf); 167 MDP_OUTP(MDP_BASE + dma_base + 0x4, ((fbi->var.yres) << 16) | 170 MDP_OUTP(MDP_BASE + dma_base + 0xc, fbi->fix.line_length); 172 MDP_OUTP(MDP_BASE + dma_base + 0x10, 0); 174 MDP_OUTP(MDP_BASE + dma_base, dma2_cfg_reg); 249 MDP_OUTP(MDP_BASE + timer_base + 0x4, hsync_ctrl); 250 MDP_OUTP(MDP_BASE + timer_base + 0x8, vsync_period); 251 MDP_OUTP(MDP_BASE + timer_base + 0xc, vsync_pulse_width * hsync_period); 253 MDP_OUTP(MDP_BASE + timer_base + 0x10, display_hctl); 254 MDP_OUTP(MDP_BASE [all...] |
H A D | mdp_dma_tv.c | 69 MDP_OUTP(MDP_BASE + 0xC0008, (uint32) buf >> 3); 73 MDP_OUTP(MDP_BASE + 0xC0004, 0x4c60674); /* flicker filter enabled */ 74 MDP_OUTP(MDP_BASE + 0xC0010, 0x20); /* sobel treshold */ 76 MDP_OUTP(MDP_BASE + 0xC0018, 0xeb0010); /* Y Max, Y min */ 77 MDP_OUTP(MDP_BASE + 0xC001C, 0xf00010); /* Cb Max, Cb min */ 78 MDP_OUTP(MDP_BASE + 0xC0020, 0xf00010); /* Cb Max, Cb min */ 80 MDP_OUTP(MDP_BASE + 0xC000C, 0x67686970); /* add a few chars for CC */ 81 MDP_OUTP(MDP_BASE + 0xC0000, 0x1); /* MDP tv out enable */ 101 MDP_OUTP(MDP_BASE + 0xC0000, 0x0); 128 MDP_OUTP(MDP_BASE [all...] |
H A D | mdp4_overlay_lcdc.c | 218 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x4, hsync_ctrl); 219 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x8, vsync_period); 220 MDP_OUTP(MDP_BASE + LCDC_BASE + 0xc, vsync_pulse_width * hsync_period); 221 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x10, display_hctl); 222 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x14, display_v_start); 223 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x18, display_v_end); 224 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x28, lcdc_border_clr); 225 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x2c, lcdc_underflow_clr); 226 MDP_OUTP(MDP_BASE + LCDC_BASE + 0x30, lcdc_hsync_skew); 227 MDP_OUTP(MDP_BASE [all...] |
H A D | mdp_dma_s.c | 85 MDP_OUTP(MDP_BASE + 0xa0004, (iBuf->dma_h << 16 | iBuf->dma_w)); 86 MDP_OUTP(MDP_BASE + 0xa0008, src); /* ibuf address */ 87 MDP_OUTP(MDP_BASE + 0xa000c, iBuf->ibuf_width * outBpp);/* ystride */ 98 MDP_OUTP(MDP_BASE + 0xa0010, (iBuf->dma_y << 16) | iBuf->dma_x); 99 MDP_OUTP(MDP_BASE + 0x00090, 1); 100 MDP_OUTP(MDP_BASE + 0x00094, 109 MDP_OUTP(MDP_BASE + 0xa0000, dma_s_cfg_reg);
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H A D | mdp.c | 146 MDP_OUTP(MDP_BASE + 0x94800 + 148 MDP_OUTP(MDP_BASE + 0x93800 + 194 MDP_OUTP(MDP_BASE + 0x90070, (mdp_lut_i << 10) | 0x17); 230 MDP_OUTP(MDP_BASE + 0x95004, hist->frame_cnt); 231 MDP_OUTP(MDP_BASE + 0x95000, 1); 233 MDP_OUTP(MDP_BASE + 0x94004, hist->frame_cnt); 234 MDP_OUTP(MDP_BASE + 0x94000, 1); 350 outpdw(MDP_BASE + 0x30, 0x1000); 378 MDP_OUTP(MDP_BASE + 0x90070, 383 outpdw(MDP_BASE [all...] |
H A D | mdp4_overlay.c | 81 MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg); 89 MDP_OUTP(MDP_BASE + 0x90004, 91 MDP_OUTP(MDP_BASE + 0x90008, pipe->srcp0_addr); 92 MDP_OUTP(MDP_BASE + 0x9000c, pipe->srcp0_ystride); 95 MDP_OUTP(MDP_BASE + 0x90010, (pipe->dst_y << 16 | pipe->dst_x)); 178 rgb_base = MDP_BASE + MDP4_RGB_BASE; 217 vg_base = MDP_BASE + MDP4_VIDEO_BASE; 617 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */ 619 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */ 637 data = inpdw(MDP_BASE [all...] |
H A D | mdp_dma.c | 153 MDP_OUTP(MDP_BASE + 0x90004, (iBuf->dma_h << 16 | iBuf->dma_w)); 154 MDP_OUTP(MDP_BASE + 0x90008, src); 155 MDP_OUTP(MDP_BASE + 0x9000c, ystride); 174 MDP_OUTP(MDP_BASE + 0x90010, (iBuf->dma_y << 16) | iBuf->dma_x); 175 MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param); 176 MDP_OUTP(MDP_BASE + 0x00094, 187 MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg); 204 MDP_OUTP(MDP_BASE + 0x210, start_y); 205 MDP_OUTP(MDP_BASE + 0x20c, 1); /* enable prim vsync */ 207 MDP_OUTP(MDP_BASE [all...] |
H A D | staging-devices.c | 65 #define MDP_BASE 0xA3F00000 macro 70 #define MDP_BASE 0xAA200000 macro 87 .start = MDP_BASE, 88 .end = MDP_BASE + 0x000F0000 - 1,
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H A D | mdp_vsync.c | 119 MDP_OUTP(MDP_BASE + MDP_SYNC_STATUS_0, vsync_load_cnt); 153 MDP_OUTP(MDP_BASE + MDP_SYNC_CFG_0, cfg); 222 MDP_OUTP(MDP_BASE + MDP_PRIM_VSYNC_INIT_VAL, 229 MDP_OUTP(MDP_BASE + MDP_PRIM_VSYNC_OUT_CTRL, 234 MDP_OUTP(MDP_BASE + 0x200,
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H A D | mdp4_util.c | 43 outpdw(MDP_BASE + 0x001c, bits); /* MDP_SW_RESET */ 45 while (inpdw(MDP_BASE + 0x001c) & bits) /* self clear when complete */ 62 outpdw(MDP_BASE + 0x10004, bits); /* MDP_OVERLAY0_CFG */ 64 outpdw(MDP_BASE + 0x18004, bits); /* MDP_OVERLAY1_CFG */ 66 MSM_FB_INFO("mdp4_overlay_cfg: 0x%x\n", (int)inpdw(MDP_BASE + 0x10004)); 73 bits = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */ 96 outpdw(MDP_BASE + 0x0038, bits); /* MDP_DISP_INTF_SEL */ 98 MSM_FB_INFO("mdp4_display_intf_sel: 0x%x\n", (int)inpdw(MDP_BASE + 0x0038)); 103 return inpdw(MDP_BASE + 0x0018) & 0x3ff; /* MDP_DISPLAY_STATUS */ 111 outpdw(MDP_BASE [all...] |
H A D | mdp4_overlay_mddi.c | 97 MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param); 98 MDP_OUTP(MDP_BASE + 0x00094,
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H A D | mdp_ppp_v31.c | 735 MDP_OUTP(MDP_BASE + 0x50020, 739 MDP_OUTP(MDP_BASE + 0x10230, ppp_scale_config); 803 outpdw(MDP_BASE + 0x70010, bg_alpha);
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H A D | mdp_ppp_dq.c | 262 outpdw(MDP_BASE + 0x30, 0x1000);
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H A D | mdp.h | 104 #define MDP_BASE msm_mdp_base macro 223 #define MDP_CMD_DEBUG_ACCESS_BASE (MDP_BASE+0x10000)
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