1/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Code Aurora nor 11 * the names of its contributors may be used to endorse or promote 12 * products derived from this software without specific prior written 13 * permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef MDP_H 30#define MDP_H 31 32#include <linux/kernel.h> 33#include <linux/sched.h> 34#include <linux/time.h> 35#include <linux/init.h> 36#include <linux/interrupt.h> 37#include <linux/fb.h> 38#include <linux/hrtimer.h> 39#include "msm_mdp.h" 40 41#include <mach/hardware.h> 42#include <linux/io.h> 43 44#include <asm/system.h> 45#include <asm/mach-types.h> 46 47#include "msm_fb_panel.h" 48 49#ifdef CONFIG_MDP_PPP_ASYNC_OP 50#include "mdp_ppp_dq.h" 51#endif 52 53#ifdef BIT 54#undef BIT 55#endif 56 57#define BIT(x) (1<<(x)) 58 59#define MDPOP_NOP 0 60#define MDPOP_LR BIT(0) /* left to right flip */ 61#define MDPOP_UD BIT(1) /* up and down flip */ 62#define MDPOP_ROT90 BIT(2) /* rotate image to 90 degree */ 63#define MDPOP_ROT180 (MDPOP_UD|MDPOP_LR) 64#define MDPOP_ROT270 (MDPOP_ROT90|MDPOP_UD|MDPOP_LR) 65#define MDPOP_ASCALE BIT(7) 66#define MDPOP_ALPHAB BIT(8) /* enable alpha blending */ 67#define MDPOP_TRANSP BIT(9) /* enable transparency */ 68#define MDPOP_DITHER BIT(10) /* enable dither */ 69#define MDPOP_SHARPENING BIT(11) /* enable sharpening */ 70#define MDPOP_BLUR BIT(12) /* enable blur */ 71#define MDPOP_FG_PM_ALPHA BIT(13) 72 73struct mdp_table_entry { 74 uint32_t reg; 75 uint32_t val; 76}; 77 78extern struct mdp_ccs mdp_ccs_yuv2rgb ; 79extern struct mdp_ccs mdp_ccs_rgb2yuv ; 80 81/* 82 * MDP Image Structure 83 */ 84typedef struct mdpImg_ { 85 uint32 imgType; /* Image type */ 86 uint32 *bmy_addr; /* bitmap or y addr */ 87 uint32 *cbcr_addr; /* cbcr addr */ 88 uint32 width; /* image width */ 89 uint32 mdpOp; /* image opertion (rotation,flip up/down, alpha/tp) */ 90 uint32 tpVal; /* transparency color */ 91 uint32 alpha; /* alpha percentage 0%(0x0) ~ 100%(0x100) */ 92 int sp_value; /* sharpening strength */ 93} MDPIMG; 94 95#ifdef CONFIG_MDP_PPP_ASYNC_OP 96#define MDP_OUTP(addr, data) mdp_ppp_outdw((uint32_t)(addr), \ 97 (uint32_t)(data)) 98#else 99#define MDP_OUTP(addr, data) outpdw((addr), (data)) 100#endif 101 102#define MDP_KTIME2USEC(kt) (kt.tv.sec*1000000 + kt.tv.nsec/1000) 103 104#define MDP_BASE msm_mdp_base 105 106typedef enum { 107 MDP_BC_SCALE_POINT2_POINT4, 108 MDP_BC_SCALE_POINT4_POINT6, 109 MDP_BC_SCALE_POINT6_POINT8, 110 MDP_BC_SCALE_POINT8_1, 111 MDP_BC_SCALE_UP, 112 MDP_PR_SCALE_POINT2_POINT4, 113 MDP_PR_SCALE_POINT4_POINT6, 114 MDP_PR_SCALE_POINT6_POINT8, 115 MDP_PR_SCALE_POINT8_1, 116 MDP_PR_SCALE_UP, 117 MDP_SCALE_BLUR, 118 MDP_INIT_SCALE 119} MDP_SCALE_MODE; 120 121typedef enum { 122 MDP_BLOCK_POWER_OFF, 123 MDP_BLOCK_POWER_ON 124} MDP_BLOCK_POWER_STATE; 125 126typedef enum { 127 MDP_MASTER_BLOCK, 128 MDP_CMD_BLOCK, 129 MDP_PPP_BLOCK, 130 MDP_DMA2_BLOCK, 131 MDP_DMA3_BLOCK, 132 MDP_DMA_S_BLOCK, 133 MDP_DMA_E_BLOCK, 134 MDP_OVERLAY0_BLOCK, 135 MDP_OVERLAY1_BLOCK, 136 MDP_MAX_BLOCK 137} MDP_BLOCK_TYPE; 138 139/* Let's keep Q Factor power of 2 for optimization */ 140#define MDP_SCALE_Q_FACTOR 512 141 142#ifdef CONFIG_FB_MSM_MDP31 143#define MDP_MAX_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*8) 144#define MDP_MIN_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/8) 145#define MDP_MAX_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*8) 146#define MDP_MIN_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/8) 147#else 148#define MDP_MAX_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*4) 149#define MDP_MIN_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/4) 150#define MDP_MAX_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*4) 151#define MDP_MIN_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/4) 152#endif 153 154/* SHIM Q Factor */ 155#define PHI_Q_FACTOR 29 156#define PQF_PLUS_5 (PHI_Q_FACTOR + 5) /* due to 32 phases */ 157#define PQF_PLUS_4 (PHI_Q_FACTOR + 4) 158#define PQF_PLUS_2 (PHI_Q_FACTOR + 2) /* to get 4.0 */ 159#define PQF_MINUS_2 (PHI_Q_FACTOR - 2) /* to get 0.25 */ 160#define PQF_PLUS_5_PLUS_2 (PQF_PLUS_5 + 2) 161#define PQF_PLUS_5_MINUS_2 (PQF_PLUS_5 - 2) 162 163#define MDP_CONVTP(tpVal) (((tpVal&0xF800)<<8)|((tpVal&0x7E0)<<5)|((tpVal&0x1F)<<3)) 164 165#define MDPOP_ROTATION (MDPOP_ROT90|MDPOP_LR|MDPOP_UD) 166#define MDP_CHKBIT(val, bit) ((bit) == ((val) & (bit))) 167 168/* overlay interface API defines */ 169typedef enum { 170 MORE_IBUF, 171 FINAL_IBUF, 172 COMPLETE_IBUF 173} MDP_IBUF_STATE; 174 175struct mdp_dirty_region { 176 __u32 xoffset; /* source origin in the x-axis */ 177 __u32 yoffset; /* source origin in the y-axis */ 178 __u32 width; /* number of pixels in the x-axis */ 179 __u32 height; /* number of pixels in the y-axis */ 180}; 181 182/* 183 * MDP extended data types 184 */ 185typedef struct mdp_roi_s { 186 uint32 x; 187 uint32 y; 188 uint32 width; 189 uint32 height; 190 int32 lcd_x; 191 int32 lcd_y; 192 uint32 dst_width; 193 uint32 dst_height; 194} MDP_ROI; 195 196typedef struct mdp_ibuf_s { 197 uint8 *buf; 198 uint32 bpp; 199 uint32 ibuf_type; 200 uint32 ibuf_width; 201 uint32 ibuf_height; 202 203 MDP_ROI roi; 204 MDPIMG mdpImg; 205 206 int32 dma_x; 207 int32 dma_y; 208 uint32 dma_w; 209 uint32 dma_h; 210 211 uint32 vsync_enable; 212 uint32 visible_swapped; 213} MDPIBUF; 214 215struct mdp_dma_data { 216 boolean busy; 217 boolean waiting; 218 struct mutex ov_mutex; 219 struct semaphore mutex; 220 struct completion comp; 221}; 222 223#define MDP_CMD_DEBUG_ACCESS_BASE (MDP_BASE+0x10000) 224 225#define MDP_DMA2_TERM 0x1 226#define MDP_DMA3_TERM 0x2 227#define MDP_PPP_TERM 0x4 228#define MDP_DMA_S_TERM 0x8 229#ifdef CONFIG_FB_MSM_MDP40 230#define MDP_DMA_E_TERM 0x10 231#define MDP_OVERLAY0_TERM 0x20 232#define MDP_OVERLAY1_TERM 0x40 233#endif 234 235#define ACTIVE_START_X_EN BIT(31) 236#define ACTIVE_START_Y_EN BIT(31) 237#define ACTIVE_HIGH 0 238#define ACTIVE_LOW 1 239#define MDP_DMA_S_DONE BIT(2) 240#define LCDC_FRAME_START BIT(15) 241#define LCDC_UNDERFLOW BIT(16) 242 243#ifdef CONFIG_FB_MSM_MDP22 244#define MDP_DMA_P_DONE BIT(2) 245#else 246#define MDP_DMA_P_DONE BIT(14) 247#endif 248 249#define MDP_PPP_DONE BIT(0) 250#define TV_OUT_DMA3_DONE BIT(6) 251#define TV_ENC_UNDERRUN BIT(7) 252#define TV_OUT_DMA3_START BIT(13) 253#define MDP_HIST_DONE BIT(20) 254 255#ifdef CONFIG_FB_MSM_MDP22 256#define MDP_ANY_INTR_MASK (MDP_PPP_DONE| \ 257 MDP_DMA_P_DONE| \ 258 TV_ENC_UNDERRUN) 259#else 260#define MDP_ANY_INTR_MASK (MDP_PPP_DONE| \ 261 MDP_DMA_P_DONE| \ 262 MDP_DMA_S_DONE| \ 263 LCDC_UNDERFLOW| \ 264 MDP_HIST_DONE| \ 265 TV_ENC_UNDERRUN) 266#endif 267 268#define MDP_TOP_LUMA 16 269#define MDP_TOP_CHROMA 0 270#define MDP_BOTTOM_LUMA 19 271#define MDP_BOTTOM_CHROMA 3 272#define MDP_LEFT_LUMA 22 273#define MDP_LEFT_CHROMA 6 274#define MDP_RIGHT_LUMA 25 275#define MDP_RIGHT_CHROMA 9 276 277#define CLR_G 0x0 278#define CLR_B 0x1 279#define CLR_R 0x2 280#define CLR_ALPHA 0x3 281 282#define CLR_Y CLR_G 283#define CLR_CB CLR_B 284#define CLR_CR CLR_R 285 286/* from lsb to msb */ 287#define MDP_GET_PACK_PATTERN(a,x,y,z,bit) (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z)) 288 289/* 290 * 0x0000 0x0004 0x0008 MDP sync config 291 */ 292#ifdef CONFIG_FB_MSM_MDP22 293#define MDP_SYNCFG_HGT_LOC 22 294#define MDP_SYNCFG_VSYNC_EXT_EN BIT(21) 295#define MDP_SYNCFG_VSYNC_INT_EN BIT(20) 296#else 297#define MDP_SYNCFG_HGT_LOC 21 298#define MDP_SYNCFG_VSYNC_EXT_EN BIT(20) 299#define MDP_SYNCFG_VSYNC_INT_EN BIT(19) 300#define MDP_HW_VSYNC 301#endif 302 303/* 304 * 0x0018 MDP VSYNC THREASH 305 */ 306#define MDP_PRIM_BELOW_LOC 0 307#define MDP_PRIM_ABOVE_LOC 8 308 309/* 310 * MDP_PRIMARY_VSYNC_OUT_CTRL 311 * 0x0080,84,88 internal vsync pulse config 312 */ 313#define VSYNC_PULSE_EN BIT(31) 314#define VSYNC_PULSE_INV BIT(30) 315 316/* 317 * 0x008c MDP VSYNC CONTROL 318 */ 319#define DISP0_VSYNC_MAP_VSYNC0 0 320#define DISP0_VSYNC_MAP_VSYNC1 BIT(0) 321#define DISP0_VSYNC_MAP_VSYNC2 BIT(0)|BIT(1) 322 323#define DISP1_VSYNC_MAP_VSYNC0 0 324#define DISP1_VSYNC_MAP_VSYNC1 BIT(2) 325#define DISP1_VSYNC_MAP_VSYNC2 BIT(2)|BIT(3) 326 327#define PRIMARY_LCD_SYNC_EN BIT(4) 328#define PRIMARY_LCD_SYNC_DISABLE 0 329 330#define SECONDARY_LCD_SYNC_EN BIT(5) 331#define SECONDARY_LCD_SYNC_DISABLE 0 332 333#define EXTERNAL_LCD_SYNC_EN BIT(6) 334#define EXTERNAL_LCD_SYNC_DISABLE 0 335 336/* 337 * 0x101f0 MDP VSYNC Threshold 338 */ 339#define VSYNC_THRESHOLD_ABOVE_LOC 0 340#define VSYNC_THRESHOLD_BELOW_LOC 16 341#define VSYNC_ANTI_TEAR_EN BIT(31) 342 343/* 344 * 0x10004 command config 345 */ 346#define MDP_CMD_DBGBUS_EN BIT(0) 347 348/* 349 * 0x10124 or 0x101d4PPP source config 350 */ 351#define PPP_SRC_C0G_8BITS (BIT(1)|BIT(0)) 352#define PPP_SRC_C1B_8BITS (BIT(3)|BIT(2)) 353#define PPP_SRC_C2R_8BITS (BIT(5)|BIT(4)) 354#define PPP_SRC_C3A_8BITS (BIT(7)|BIT(6)) 355 356#define PPP_SRC_C0G_6BITS BIT(1) 357#define PPP_SRC_C1B_6BITS BIT(3) 358#define PPP_SRC_C2R_6BITS BIT(5) 359 360#define PPP_SRC_C0G_5BITS BIT(0) 361#define PPP_SRC_C1B_5BITS BIT(2) 362#define PPP_SRC_C2R_5BITS BIT(4) 363 364#define PPP_SRC_C3_ALPHA_EN BIT(8) 365 366#define PPP_SRC_BPP_INTERLVD_1BYTES 0 367#define PPP_SRC_BPP_INTERLVD_2BYTES BIT(9) 368#define PPP_SRC_BPP_INTERLVD_3BYTES BIT(10) 369#define PPP_SRC_BPP_INTERLVD_4BYTES (BIT(10)|BIT(9)) 370 371#define PPP_SRC_BPP_ROI_ODD_X BIT(11) 372#define PPP_SRC_BPP_ROI_ODD_Y BIT(12) 373#define PPP_SRC_INTERLVD_2COMPONENTS BIT(13) 374#define PPP_SRC_INTERLVD_3COMPONENTS BIT(14) 375#define PPP_SRC_INTERLVD_4COMPONENTS (BIT(14)|BIT(13)) 376 377/* 378 * RGB666 unpack format 379 * TIGHT means R6+G6+B6 together 380 * LOOSE means R6+2 +G6+2+ B6+2 (with MSB) 381 * or 2+R6 +2+G6 +2+B6 (with LSB) 382 */ 383#define PPP_SRC_UNPACK_TIGHT BIT(17) 384#define PPP_SRC_UNPACK_LOOSE 0 385#define PPP_SRC_UNPACK_ALIGN_LSB 0 386#define PPP_SRC_UNPACK_ALIGN_MSB BIT(18) 387 388#define PPP_SRC_FETCH_PLANES_INTERLVD 0 389#define PPP_SRC_FETCH_PLANES_PSEUDOPLNR BIT(20) 390 391#define PPP_SRC_WMV9_MODE BIT(21) /* window media version 9 */ 392 393/* 394 * 0x10138 PPP operation config 395 */ 396#define PPP_OP_SCALE_X_ON BIT(0) 397#define PPP_OP_SCALE_Y_ON BIT(1) 398 399#define PPP_OP_CONVERT_RGB2YCBCR 0 400#define PPP_OP_CONVERT_YCBCR2RGB BIT(2) 401#define PPP_OP_CONVERT_ON BIT(3) 402 403#define PPP_OP_CONVERT_MATRIX_PRIMARY 0 404#define PPP_OP_CONVERT_MATRIX_SECONDARY BIT(4) 405 406#define PPP_OP_LUT_C0_ON BIT(5) 407#define PPP_OP_LUT_C1_ON BIT(6) 408#define PPP_OP_LUT_C2_ON BIT(7) 409 410/* rotate or blend enable */ 411#define PPP_OP_ROT_ON BIT(8) 412 413#define PPP_OP_ROT_90 BIT(9) 414#define PPP_OP_FLIP_LR BIT(10) 415#define PPP_OP_FLIP_UD BIT(11) 416 417#define PPP_OP_BLEND_ON BIT(12) 418 419#define PPP_OP_BLEND_SRCPIXEL_ALPHA 0 420#define PPP_OP_BLEND_DSTPIXEL_ALPHA BIT(13) 421#define PPP_OP_BLEND_CONSTANT_ALPHA BIT(14) 422#define PPP_OP_BLEND_SRCPIXEL_TRANSP (BIT(13)|BIT(14)) 423 424#define PPP_OP_BLEND_ALPHA_BLEND_NORMAL 0 425#define PPP_OP_BLEND_ALPHA_BLEND_REVERSE BIT(15) 426 427#define PPP_OP_DITHER_EN BIT(16) 428 429#define PPP_OP_COLOR_SPACE_RGB 0 430#define PPP_OP_COLOR_SPACE_YCBCR BIT(17) 431 432#define PPP_OP_SRC_CHROMA_RGB 0 433#define PPP_OP_SRC_CHROMA_H2V1 BIT(18) 434#define PPP_OP_SRC_CHROMA_H1V2 BIT(19) 435#define PPP_OP_SRC_CHROMA_420 (BIT(18)|BIT(19)) 436#define PPP_OP_SRC_CHROMA_COSITE 0 437#define PPP_OP_SRC_CHROMA_OFFSITE BIT(20) 438 439#define PPP_OP_DST_CHROMA_RGB 0 440#define PPP_OP_DST_CHROMA_H2V1 BIT(21) 441#define PPP_OP_DST_CHROMA_H1V2 BIT(22) 442#define PPP_OP_DST_CHROMA_420 (BIT(21)|BIT(22)) 443#define PPP_OP_DST_CHROMA_COSITE 0 444#define PPP_OP_DST_CHROMA_OFFSITE BIT(23) 445 446#define PPP_BLEND_CALPHA_TRNASP BIT(24) 447 448#define PPP_OP_BG_CHROMA_RGB 0 449#define PPP_OP_BG_CHROMA_H2V1 BIT(25) 450#define PPP_OP_BG_CHROMA_H1V2 BIT(26) 451#define PPP_OP_BG_CHROMA_420 BIT(25)|BIT(26) 452#define PPP_OP_BG_CHROMA_SITE_COSITE 0 453#define PPP_OP_BG_CHROMA_SITE_OFFSITE BIT(27) 454#define PPP_OP_DEINT_EN BIT(29) 455 456#define PPP_BLEND_BG_USE_ALPHA_SEL (1 << 0) 457#define PPP_BLEND_BG_ALPHA_REVERSE (1 << 3) 458#define PPP_BLEND_BG_SRCPIXEL_ALPHA (0 << 1) 459#define PPP_BLEND_BG_DSTPIXEL_ALPHA (1 << 1) 460#define PPP_BLEND_BG_CONSTANT_ALPHA (2 << 1) 461#define PPP_BLEND_BG_CONST_ALPHA_VAL(x) ((x) << 24) 462 463#define PPP_OP_DST_RGB 0 464#define PPP_OP_DST_YCBCR BIT(30) 465/* 466 * 0x10150 PPP destination config 467 */ 468#define PPP_DST_C0G_8BIT (BIT(0)|BIT(1)) 469#define PPP_DST_C1B_8BIT (BIT(3)|BIT(2)) 470#define PPP_DST_C2R_8BIT (BIT(5)|BIT(4)) 471#define PPP_DST_C3A_8BIT (BIT(7)|BIT(6)) 472 473#define PPP_DST_C0G_6BIT BIT(1) 474#define PPP_DST_C1B_6BIT BIT(3) 475#define PPP_DST_C2R_6BIT BIT(5) 476 477#define PPP_DST_C0G_5BIT BIT(0) 478#define PPP_DST_C1B_5BIT BIT(2) 479#define PPP_DST_C2R_5BIT BIT(4) 480 481#define PPP_DST_C3A_8BIT (BIT(7)|BIT(6)) 482#define PPP_DST_C3ALPHA_EN BIT(8) 483 484#define PPP_DST_PACKET_CNT_INTERLVD_2ELEM BIT(9) 485#define PPP_DST_PACKET_CNT_INTERLVD_3ELEM BIT(10) 486#define PPP_DST_PACKET_CNT_INTERLVD_4ELEM (BIT(10)|BIT(9)) 487#define PPP_DST_PACKET_CNT_INTERLVD_6ELEM (BIT(11)|BIT(9)) 488 489#define PPP_DST_PACK_LOOSE 0 490#define PPP_DST_PACK_TIGHT BIT(13) 491#define PPP_DST_PACK_ALIGN_LSB 0 492#define PPP_DST_PACK_ALIGN_MSB BIT(14) 493 494#define PPP_DST_OUT_SEL_AXI 0 495#define PPP_DST_OUT_SEL_MDDI BIT(15) 496 497#define PPP_DST_BPP_2BYTES BIT(16) 498#define PPP_DST_BPP_3BYTES BIT(17) 499#define PPP_DST_BPP_4BYTES (BIT(17)|BIT(16)) 500 501#define PPP_DST_PLANE_INTERLVD 0 502#define PPP_DST_PLANE_PLANAR BIT(18) 503#define PPP_DST_PLANE_PSEUDOPLN BIT(19) 504 505#define PPP_DST_TO_TV BIT(20) 506 507#define PPP_DST_MDDI_PRIMARY 0 508#define PPP_DST_MDDI_SECONDARY BIT(21) 509#define PPP_DST_MDDI_EXTERNAL BIT(22) 510 511/* 512 * 0x10180 DMA config 513 */ 514#define DMA_DSTC0G_8BITS (BIT(1)|BIT(0)) 515#define DMA_DSTC1B_8BITS (BIT(3)|BIT(2)) 516#define DMA_DSTC2R_8BITS (BIT(5)|BIT(4)) 517 518#define DMA_DSTC0G_6BITS BIT(1) 519#define DMA_DSTC1B_6BITS BIT(3) 520#define DMA_DSTC2R_6BITS BIT(5) 521 522#define DMA_DSTC0G_5BITS BIT(0) 523#define DMA_DSTC1B_5BITS BIT(2) 524#define DMA_DSTC2R_5BITS BIT(4) 525 526#define DMA_PACK_TIGHT BIT(6) 527#define DMA_PACK_LOOSE 0 528#define DMA_PACK_ALIGN_LSB 0 529/* 530 * use DMA_PACK_ALIGN_MSB if the upper 6 bits from 8 bits output 531 * from LCDC block maps into 6 pins out to the panel 532 */ 533#define DMA_PACK_ALIGN_MSB BIT(7) 534#define DMA_PACK_PATTERN_RGB \ 535 (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8) 536#define DMA_PACK_PATTERN_BGR \ 537 (MDP_GET_PACK_PATTERN(0, CLR_B, CLR_G, CLR_R, 2)<<8) 538#define DMA_OUT_SEL_AHB 0 539#define DMA_OUT_SEL_LCDC BIT(20) 540#define DMA_IBUF_FORMAT_RGB888 0 541#define DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888 BIT(26) 542 543#ifdef CONFIG_FB_MSM_MDP22 544#define DMA_OUT_SEL_MDDI BIT(14) 545#define DMA_AHBM_LCD_SEL_PRIMARY 0 546#define DMA_AHBM_LCD_SEL_SECONDARY BIT(15) 547#define DMA_IBUF_C3ALPHA_EN BIT(16) 548#define DMA_DITHER_EN BIT(17) 549#define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0 550#define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY BIT(18) 551#define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL BIT(19) 552#define DMA_IBUF_FORMAT_RGB565 BIT(20) 553#define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 0 554#define DMA_IBUF_NONCONTIGUOUS BIT(21) 555#else 556#define DMA_OUT_SEL_MDDI BIT(19) 557#define DMA_AHBM_LCD_SEL_PRIMARY 0 558#define DMA_AHBM_LCD_SEL_SECONDARY 0 559#define DMA_IBUF_C3ALPHA_EN 0 560#define DMA_DITHER_EN BIT(24) 561#define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0 562#define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY 0 563#define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL 0 564#define DMA_IBUF_FORMAT_RGB565 BIT(25) 565#define DMA_IBUF_NONCONTIGUOUS 0 566#endif 567 568/* 569 * MDDI Register 570 */ 571#define MDDI_VDO_PACKET_DESC 0x5666 572 573#ifdef CONFIG_FB_MSM_MDP40 574#define MDP_INTR_ENABLE (msm_mdp_base + 0x0050) 575#define MDP_INTR_STATUS (msm_mdp_base + 0x0054) 576#define MDP_INTR_CLEAR (msm_mdp_base + 0x0058) 577#define MDP_EBI2_LCD0 (msm_mdp_base + 0x0060) 578#define MDP_EBI2_LCD1 (msm_mdp_base + 0x0064) 579#define MDP_EBI2_PORTMAP_MODE (msm_mdp_base + 0x0070) 580 581#define MDP_DMA_P_HIST_INTR_STATUS (msm_mdp_base + 0x95014) 582#define MDP_DMA_P_HIST_INTR_CLEAR (msm_mdp_base + 0x95018) 583#define MDP_DMA_P_HIST_INTR_ENABLE (msm_mdp_base + 0x9501C) 584#else 585#define MDP_INTR_ENABLE (msm_mdp_base + 0x0020) 586#define MDP_INTR_STATUS (msm_mdp_base + 0x0024) 587#define MDP_INTR_CLEAR (msm_mdp_base + 0x0028) 588#define MDP_EBI2_LCD0 (msm_mdp_base + 0x003c) 589#define MDP_EBI2_LCD1 (msm_mdp_base + 0x0040) 590#define MDP_EBI2_PORTMAP_MODE (msm_mdp_base + 0x005c) 591#endif 592 593#define MDP_FULL_BYPASS_WORD43 (msm_mdp_base + 0x101ac) 594 595#define MDP_CSC_PFMVn(n) (msm_mdp_base + 0x40400 + 4 * (n)) 596#define MDP_CSC_PRMVn(n) (msm_mdp_base + 0x40440 + 4 * (n)) 597#define MDP_CSC_PRE_BV1n(n) (msm_mdp_base + 0x40500 + 4 * (n)) 598#define MDP_CSC_PRE_BV2n(n) (msm_mdp_base + 0x40540 + 4 * (n)) 599#define MDP_CSC_POST_BV1n(n) (msm_mdp_base + 0x40580 + 4 * (n)) 600#define MDP_CSC_POST_BV2n(n) (msm_mdp_base + 0x405c0 + 4 * (n)) 601 602#ifdef CONFIG_FB_MSM_MDP31 603#define MDP_CSC_PRE_LV1n(n) (msm_mdp_base + 0x40600 + 4 * (n)) 604#define MDP_CSC_PRE_LV2n(n) (msm_mdp_base + 0x40640 + 4 * (n)) 605#define MDP_CSC_POST_LV1n(n) (msm_mdp_base + 0x40680 + 4 * (n)) 606#define MDP_CSC_POST_LV2n(n) (msm_mdp_base + 0x406c0 + 4 * (n)) 607#define MDP_PPP_SCALE_COEFF_LSBn(n) (msm_mdp_base + 0x50400 + 8 * (n)) 608#define MDP_PPP_SCALE_COEFF_MSBn(n) (msm_mdp_base + 0x50404 + 8 * (n)) 609 610#define SCALE_D0_SET 0 611#define SCALE_D1_SET BIT(0) 612#define SCALE_D2_SET BIT(1) 613#define SCALE_U1_SET (BIT(0)|BIT(1)) 614 615#else 616#define MDP_CSC_PRE_LV1n(n) (msm_mdp_base + 0x40580 + 4 * (n)) 617#endif 618 619#define MDP_CURSOR_WIDTH 64 620#define MDP_CURSOR_HEIGHT 64 621#define MDP_CURSOR_SIZE (MDP_CURSOR_WIDTH*MDP_CURSOR_WIDTH*4) 622 623#define MDP_DMA_P_LUT_C0_EN BIT(0) 624#define MDP_DMA_P_LUT_C1_EN BIT(1) 625#define MDP_DMA_P_LUT_C2_EN BIT(2) 626#define MDP_DMA_P_LUT_POST BIT(4) 627 628void mdp_hw_init(void); 629int mdp_ppp_pipe_wait(void); 630void mdp_pipe_kickoff(uint32 term, struct msm_fb_data_type *mfd); 631void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state, 632 boolean isr); 633void mdp_set_dma_pan_info(struct fb_info *info, struct mdp_dirty_region *dirty, 634 boolean sync); 635void mdp_dma_pan_update(struct fb_info *info); 636void mdp_refresh_screen(unsigned long data); 637int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req, 638 struct file **pp_src, struct file **pp_dest); 639void mdp_lcd_update_workqueue_handler(struct work_struct *work); 640void mdp_vsync_resync_workqueue_handler(struct work_struct *work); 641void mdp_dma2_update(struct msm_fb_data_type *mfd); 642void mdp_config_vsync(struct msm_fb_data_type *); 643uint32 mdp_get_lcd_line_counter(struct msm_fb_data_type *mfd); 644enum hrtimer_restart mdp_dma2_vsync_hrtimer_handler(struct hrtimer *ht); 645void mdp_set_scale(MDPIBUF *iBuf, 646 uint32 dst_roi_width, 647 uint32 dst_roi_height, 648 boolean inputRGB, boolean outputRGB, uint32 *pppop_reg_ptr); 649void mdp_init_scale_table(void); 650void mdp_adjust_start_addr(uint8 **src0, 651 uint8 **src1, 652 int v_slice, 653 int h_slice, 654 int x, 655 int y, 656 uint32 width, 657 uint32 height, int bpp, MDPIBUF *iBuf, int layer); 658void mdp_set_blend_attr(MDPIBUF *iBuf, 659 uint32 *alpha, 660 uint32 *tpVal, 661 uint32 perPixelAlpha, uint32 *pppop_reg_ptr); 662 663int mdp_dma3_on(struct platform_device *pdev); 664int mdp_dma3_off(struct platform_device *pdev); 665void mdp_dma3_update(struct msm_fb_data_type *mfd); 666 667int mdp_lcdc_on(struct platform_device *pdev); 668int mdp_lcdc_off(struct platform_device *pdev); 669void mdp_lcdc_update(struct msm_fb_data_type *mfd); 670int mdp_hw_cursor_update(struct fb_info *info, struct fb_cursor *cursor); 671void mdp_enable_irq(uint32 term); 672void mdp_disable_irq(uint32 term); 673void mdp_disable_irq_nolock(uint32 term); 674uint32_t mdp_get_bytes_per_pixel(uint32_t format); 675 676#ifdef MDP_HW_VSYNC 677void mdp_hw_vsync_clk_enable(struct msm_fb_data_type *mfd); 678void mdp_hw_vsync_clk_disable(struct msm_fb_data_type *mfd); 679#endif 680 681void mdp_dma_s_update(struct msm_fb_data_type *mfd); 682 683/* Added to support flipping */ 684void mdp_set_offset_info(struct fb_info *info, uint32 address, uint32 interval); 685 686int get_gem_img(struct mdp_img *img, unsigned long *start, 687 unsigned long *len); 688int get_img(struct mdp_img *img, struct fb_info *info, 689 unsigned long *start, unsigned long *len, 690 struct file **pp_file); 691 692 693/*int get_img(struct msmfb_data *img, struct fb_info *info, 694 unsigned long *start, unsigned long *len, struct file **pp_file);*/ 695#endif /* MDP_H */ 696