Searched refs:DDR (Results 1 - 7 of 7) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/ |
H A D | sleep24xx.S | 62 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 76 /* The DPLL has to be on before we take the DDR out of self refresh */ 82 movs r0, r0 @ see if DDR or SDR
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H A D | sram242x.S | 86 /* set up for return, DDR should be good */ 137 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] 138 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 177 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL 180 /* With DDR, we need to take care of the DLL for the frequency change */ 233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
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H A D | sram243x.S | 86 /* set up for return, DDR should be good */ 137 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] 138 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 177 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL 180 /* With DDR, we need to take care of the DLL for the frequency change */ 233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/xtensa/include/asm/ |
H A D | regs.h | 46 #define DDR 104 macro
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/include/asm/mach-loongson/ |
H A D | loongson.h | 309 * d: DDR, PCI, LIO 324 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) 326 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/kernel/ |
H A D | head.S | 365 get_ddr_phys_offset r3, r11 @ get DDR base address 370 get_ddr_phys_offset r3, r11 @ get DDR base address
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/netgear-R7000-V1.0.7.12_1.2.5/src/shared/ |
H A D | aisdram.S | 230 /* Scan for a Denali DDR controller (a0) */ 1108 * AI version of DDR / memory controller initialization 1317 /* Standard package, assume 1024-column, 32-bit, 8-bank DDR */ 1321 /* Low cost package, assume 1024-column, 16-bit, 8-bank DDR */ 1417 sll t1, t1, 3 # Shift to bit6:4 for DDR MRS register
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