1/* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */ 2/* 3 * linux/arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (c) 2003 ARM Limited 7 * All Rights Reserved 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Kernel startup code for all 32-bit CPUs 14 */ 15#include <linux/linkage.h> 16#include <linux/init.h> 17 18#include <asm/assembler.h> 19#include <asm/domain.h> 20#include <asm/ptrace.h> 21#include <asm/asm-offsets.h> 22#include <asm/memory.h> 23#include <asm/thread_info.h> 24#include <asm/system.h> 25 26#if (CONFIG_DRAM_BASE & 0x001fffff) 27#error "CONFIG_DRAM_BASE must be at an even 2MiB boundary!" 28#endif 29 30#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 31#define KERNEL_RAM_PADDR (CONFIG_DRAM_BASE + TEXT_OFFSET) 32 33 34/* 35 * swapper_pg_dir is the virtual address of the initial page table. 36 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 37 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 38 * the least significant 16 bits to be 0x8000, but we could probably 39 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 40 */ 41#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 42#error KERNEL_RAM_VADDR must start at 0xXXXX8000 43#endif 44 45 .globl swapper_pg_dir 46 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 47 .macro get_ddr_phys_offset_pa, rd, rs 48 ldr \rd, =ddr_phys_offset_va 49 ldr \rs, =PAGE_OFFSET 50 sub \rd, \rd, \rs 51 ldr \rs, =CONFIG_DRAM_BASE 52 add \rd, \rd, \rs 53 .endm 54 55 .macro get_ddr_pgtbl, rd, rs 56 mov \rd, \rs 57 ldr \rd, [\rd, #0x0] 58 ldr \rs, =TEXT_OFFSET 59 add \rd, \rd, \rs 60 sub \rd, \rd, #0x4000 61 .endm 62 63 .macro get_ddr_phys_offset, rd, rs 64 mov \rd, \rs 65 ldr \rd, [\rd, #0x0] 66 .endm 67 68 .macro pgtbl, rd 69 ldr \rd, =(KERNEL_RAM_PADDR - 0x4000) 70 .endm 71 72#ifdef CONFIG_XIP_KERNEL 73#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 74#define KERNEL_END _edata_loc 75#else 76#define KERNEL_START KERNEL_RAM_VADDR 77#define KERNEL_END _end 78#endif 79 80/* 81 * Kernel startup entry point. 82 * --------------------------- 83 * 84 * This is normally called from the decompressor code. The requirements 85 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 86 * r1 = machine nr, r2 = atags pointer. 87 * 88 * This code is mostly position independent, so if you link the kernel at 89 * 0xc0008000, you call this at __pa(0xc0008000). 90 * 91 * See linux/arch/arm/tools/mach-types for the complete list of machine 92 * numbers for r1. 93 * 94 * We're trying to keep crap to a minimum; DO NOT add any machine specific 95 * crap here - that's what the boot loader (or in extreme, well justified 96 * circumstances, zImage) is for. 97 */ 98 __HEAD 99ENTRY(stext) 100 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 101 @ and irqs disabled 102 103 ldr r3, =0x18000000 @ SI_ENUM_BASE 104 ldr r4, =0 @ CC_CHIPID 105 ldr r4, [r3, r4] 106 /* Compare Chip ID */ 107 ldr r3, =0x0000ffff @ CID_ID_MASK 108 and r5, r4, r3 109 ldr r3, =53010 @ BCM4707_CHIP_ID 110 cmp r5, r3 111 bne no_acp 112 /* Compare Chip Rev */ 113 ldr r3, =0x000f0000 @ CID_REV_MASK 114 and r4, r4, r3 115 cmp r4, #0 @ The revision number of NS-Ax is 0. 116 bne bx_acp 117ax_acp: 118 /* A0 and A1 don't support ACP */ 119 ldr r3, =0x1800702c @ CCB_SRAB_CMDSTAT 120 ldr r4, =0x02400001 @ SPI page 0x02, SPI offset 0x40 121 str r4, [r3] 122 ldr r3, =0x1800703c @ CCB_SRAB_RDL 123 ldr r4, [r3] 124 ldr r3, =0xff @ 8-bits CHIP_REVID mask 125 and r4, r4, r3 126 cmp r4, #1 @ REVID: A0 = 0, A1 = 1 127 ble no_acp 128 129 /* A2 and later are able to support ACP */ 130 ldr r3, =tgt_phys 131 ldr r4, =0xc0000000 @ Clear the upper two bits 132 bic r3, r3, r4 133 ldr r4, =0x80000000 @ NS-Ax ACP starting address 134 orr r3, r3, r4 135 mov pc, r3 @ PC=0x80008000 for NS-Ax ACP 136 b tgt_phys 137bx_acp: 138 ldr r3, =tgt_phys 139 ldr r4, =0xc0000000 @ Clear the upper two bits 140 bic r3, r3, r4 141 ldr r4, =0x40000000 @ NS-Bx ACP starting address 142 orr r3, r3, r4 143 mov pc, r3 @ PC=0x40008000 for NS-Bx ACP 144 b tgt_phys 145no_acp: 146 mov r3, pc @ PC=0x8000 147tgt_phys: 148 ldr r0, =0xf0000000 149 and r3, r3, r0 150 get_ddr_phys_offset_pa r6, r7 151 str r3, [r6] @ r3=0x80000000 for NS-Ax ACP 152 @ r3=0x40000000 for NS-Bx ACP 153 @ r3=0x0 for Non ACP 154 mov r0, #0 @ restore r0 to 0x0 155 156#ifdef CONFIG_ARCH_HAS_HEAD_FIXUP 157 bl __mach_head_fixup 158#endif 159 mrc p15, 0, r9, c0, c0 @ get processor id 160 bl __lookup_processor_type @ r5=procinfo r9=cpuid 161 movs r10, r5 @ invalid processor (r5=0)? 162 beq __error_p @ yes, error 'p' 163 bl __lookup_machine_type @ r5=machinfo 164 movs r8, r5 @ invalid machine (r5=0)? 165 beq __error_a @ yes, error 'a' 166 bl __vet_atags 167 bl __create_page_tables 168 169 /* 170 * The following calls CPU specific code in a position independent 171 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 172 * xxx_proc_info structure selected by __lookup_machine_type 173 * above. On return, the CPU will be ready for the MMU to be 174 * turned on, and r0 will hold the CPU control register value. 175 */ 176 ldr r13, __switch_data @ address to jump to after 177 @ mmu has been enabled 178 adr lr, BSYM(__enable_mmu) @ return (PIC) address 179 ARM( add pc, r10, #PROCINFO_INITFUNC ) 180 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 181 THUMB( mov pc, r12 ) 182ENDPROC(stext) 183 184#if defined(CONFIG_SMP) 185ENTRY(secondary_startup) 186 /* 187 * Common entry point for secondary CPUs. 188 * 189 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 190 * the processor type - there is no need to check the machine type 191 * as it has already been validated by the primary processor. 192 */ 193 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 194 mrc p15, 0, r9, c0, c0 @ get processor id 195 bl __lookup_processor_type 196 movs r10, r5 @ invalid processor? 197 moveq r0, #'p' @ yes, error 'p' 198 beq __error 199 200 /* 201 * Use the page tables supplied from __cpu_up. 202 */ 203 adr r4, __secondary_data 204 ldmia r4, {r5, r7, r12} @ address to jump to after 205 sub r4, r4, r5 @ mmu has been enabled 206 ldr r4, [r7, r4] @ get secondary_data.pgdir 207 adr lr, BSYM(__enable_mmu) @ return address 208 mov r13, r12 @ __secondary_switched address 209 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 210 @ (return control reg) 211 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 212 THUMB( mov pc, r12 ) 213ENDPROC(secondary_startup) 214 215 /* 216 * r6 = &secondary_data 217 */ 218ENTRY(__secondary_switched) 219 ldr sp, [r7, #4] @ get secondary_data.stack 220 mov fp, #0 221 b secondary_start_kernel 222ENDPROC(__secondary_switched) 223 224 .type __secondary_data, %object 225__secondary_data: 226 .long . 227 .long secondary_data 228 .long __secondary_switched 229#endif /* defined(CONFIG_SMP) */ 230 231 232 233/* 234 * Setup common bits before finally enabling the MMU. Essentially 235 * this is just loading the page table pointer and domain access 236 * registers. 237 */ 238__enable_mmu: 239#ifdef CONFIG_ALIGNMENT_TRAP 240 orr r0, r0, #CR_A 241#else 242 bic r0, r0, #CR_A 243#endif 244#ifdef CONFIG_CPU_DCACHE_DISABLE 245 bic r0, r0, #CR_C 246#endif 247#ifdef CONFIG_CPU_BPREDICT_DISABLE 248 bic r0, r0, #CR_Z 249#endif 250#ifdef CONFIG_CPU_ICACHE_DISABLE 251 bic r0, r0, #CR_I 252#endif 253 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 254 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 255 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 256 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 257 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 258 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 259 b __turn_mmu_on 260ENDPROC(__enable_mmu) 261 262/* 263 * Enable the MMU. This completely changes the structure of the visible 264 * memory space. You will not be able to trace execution through this. 265 * If you have an enquiry about this, *please* check the linux-arm-kernel 266 * mailing list archives BEFORE sending another post to the list. 267 * 268 * r0 = cp#15 control register 269 * r13 = *virtual* address to jump to upon completion 270 * 271 * other registers depend on the function called upon completion 272 */ 273 .align 5 274__turn_mmu_on: 275 mov r0, r0 276 mcr p15, 0, r0, c1, c0, 0 @ write control reg 277 mrc p15, 0, r3, c0, c0, 0 @ read id reg 278 mov r3, r3 279 mov r3, r13 280 mov pc, r3 281ENDPROC(__turn_mmu_on) 282 283 284/* 285 * Setup the initial page tables. We only setup the barest 286 * amount which are required to get the kernel running, which 287 * generally means mapping in the kernel code. 288 * 289 * r8 = machinfo 290 * r9 = cpuid 291 * r10 = procinfo 292 * 293 * Returns: 294 * r0, r3, r6, r7 corrupted 295 * r4 = physical page table address 296 */ 297__create_page_tables: 298 get_ddr_phys_offset_pa r0, r4 299 get_ddr_pgtbl r4, r0 @ page table address 300 301 /* 302 * Clear the 16K level 1 swapper page table 303 */ 304 mov r0, r4 305 mov r3, #0 306 add r6, r0, #0x4000 3071: str r3, [r0], #4 308 str r3, [r0], #4 309 str r3, [r0], #4 310 str r3, [r0], #4 311 teq r0, r6 312 bne 1b 313 314 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 315 316 /* 317 * Create identity mapping for first MB of kernel to 318 * cater for the MMU enable. This identity mapping 319 * will be removed by paging_init(). We use our current program 320 * counter to determine corresponding section base address. 321 */ 322 mov r6, pc 323 mov r6, r6, lsr #20 @ start of kernel section 324 orr r3, r7, r6, lsl #20 @ flags + kernel base 325 str r3, [r4, r6, lsl #2] @ identity mapping 326 327 /* 328 * Now setup the pagetables for our kernel direct 329 * mapped region. 330 */ 331 add r0, r4, #(KERNEL_START & 0xff000000) >> 18 332 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! 333 ldr r6, =(KERNEL_END - 1) 334 add r0, r0, #4 335 add r6, r4, r6, lsr #18 3361: cmp r0, r6 337 add r3, r3, #1 << 20 338 strls r3, [r0], #4 339 bls 1b 340 341#ifdef CONFIG_XIP_KERNEL 342 /* 343 * Map some ram to cover our .data and .bss areas. 344 */ 345 orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000) 346 .if (KERNEL_RAM_PADDR & 0x00f00000) 347 orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000) 348 .endif 349 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 350 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! 351 ldr r6, =(_end - 1) 352 add r0, r0, #4 353 add r6, r4, r6, lsr #18 3541: cmp r0, r6 355 add r3, r3, #1 << 20 356 strls r3, [r0], #4 357 bls 1b 358#endif 359 360 /* 361 * Then map first 1MB of ram in case it contains our boot params. 362 */ 363 add r0, r4, #PAGE_OFFSET >> 18 364 get_ddr_phys_offset_pa r11, r3 365 get_ddr_phys_offset r3, r11 @ get DDR base address 366 and r3, r3, #0xff000000 367 orr r6, r7, r3 368 369 get_ddr_phys_offset_pa r11, r3 370 get_ddr_phys_offset r3, r11 @ get DDR base address 371 and r3, r3, #0x00f00000 372 cmp r3, #0 373 orrgt r6, r6, r3 374 str r6, [r0] 375 376#ifdef CONFIG_DEBUG_LL 377 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 378 /* 379 * Map in IO space for serial debugging. 380 * This allows debug messages to be output 381 * via a serial console before paging_init. 382 */ 383 ldr r3, [r8, #MACHINFO_PGOFFIO] 384 add r0, r4, r3 385 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 386 cmp r3, #0x0800 @ limit to 512MB 387 movhi r3, #0x0800 388 add r6, r0, r3 389 ldr r3, [r8, #MACHINFO_PHYSIO] 390 orr r3, r3, r7 3911: str r3, [r0], #4 392 add r3, r3, #1 << 20 393 teq r0, r6 394 bne 1b 395#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 396 /* 397 * If we're using the NetWinder or CATS, we also need to map 398 * in the 16550-type serial port for the debug messages 399 */ 400 add r0, r4, #0xff000000 >> 18 401 orr r3, r7, #0x7c000000 402 str r3, [r0] 403#endif 404#ifdef CONFIG_ARCH_RPC 405 /* 406 * Map in screen at 0x02000000 & SCREEN2_BASE 407 * Similar reasons here - for debug. This is 408 * only for Acorn RiscPC architectures. 409 */ 410 add r0, r4, #0x02000000 >> 18 411 orr r3, r7, #0x02000000 412 str r3, [r0] 413 add r0, r4, #0xd8000000 >> 18 414 str r3, [r0] 415#endif 416#endif 417 mov pc, lr 418ENDPROC(__create_page_tables) 419 .ltorg 420 421#include "head-common.S" 422