Searched refs:wb_info (Results 1 - 11 of 11) sorted by relevance
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
H A D | dcn30_hwseq.h | 40 struct dc_writeback_info *wb_info, 44 struct dc_writeback_info *wb_info, 53 struct dc_writeback_info *wb_info);
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H A D | dcn30_hwseq.c | 404 struct dc_writeback_info *wb_info, 410 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 411 ASSERT(wb_info->wb_enabled); 412 ASSERT(wb_info->mpcc_inst >= 0); 413 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); 414 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 415 mcif_buf_params = &wb_info->mcif_buf_params; 419 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); 421 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info 402 dcn30_set_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument 425 dcn30_update_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument 442 dcn30_mmhubbub_warmup( struct dc *dc, unsigned int num_dwb, struct dc_writeback_info *wb_info) argument 500 dcn30_enable_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument 553 struct dc_writeback_info wb_info; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.c | 278 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; local 280 if (wb_info->wb_enabled && wb_info->writeback_source_plane && 281 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { 284 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? 285 wb_info->dwb_params.cnv_params.crop_height : 286 wb_info->dwb_params.cnv_params.src_height; 287 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? 288 wb_info->dwb_params.cnv_params.crop_width : 289 wb_info [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_stream.c | 393 struct dc_writeback_info *wb_info) 404 if (wb_info == NULL) { 409 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 416 wb_info->dwb_params.out_transfer_func = &stream->out_transfer_func; 418 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 426 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 427 stream->writeback_info[i] = *wb_info; 434 stream->writeback_info[stream->num_wb_info++] = *wb_info; 439 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 451 struct dwbc *dwb = dc->res_pool->dwbc[wb_info 391 dc_stream_add_writeback(struct dc *dc, struct dc_stream_state *stream, struct dc_writeback_info *wb_info) argument 550 dc_stream_warmup_writeback(struct dc *dc, int num_dwb, struct dc_writeback_info *wb_info) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_translation_helper.c | 1069 const struct dc_writeback_info *wb_info = &in->writeback_info[i]; local 1071 if (wb_info->wb_enabled) { 1072 out->WritebackEnable[location] = wb_info->wb_enabled; 1073 out->ActiveWritebacksPerSurface[location] = wb_info->dwb_params.cnv_params.src_width; 1074 out->WritebackDestinationWidth[location] = wb_info->dwb_params.dest_width; 1075 out->WritebackDestinationHeight[location] = wb_info->dwb_params.dest_height; 1077 out->WritebackSourceWidth[location] = wb_info->dwb_params.cnv_params.crop_en ? 1078 wb_info->dwb_params.cnv_params.crop_width : 1079 wb_info->dwb_params.cnv_params.src_width; 1081 out->WritebackSourceHeight[location] = wb_info [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.c | 999 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; local 1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1013 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 1014 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 1017 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 1018 if (wb_info 2495 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/ |
H A D | hw_sequencer.h | 310 struct dc_writeback_info *wb_info, 313 struct dc_writeback_info *wb_info, 320 struct dc_writeback_info *wb_info);
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
H A D | dcn20_hwseq.h | 116 struct dc_writeback_info *wb_info,
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H A D | dcn20_hwseq.c | 2400 struct dc_writeback_info *wb_info, 2407 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2408 ASSERT(wb_info->wb_enabled); 2409 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2410 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2414 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2416 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2417 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2421 dwb->funcs->enable(dwb, &wb_info 2398 dcn20_enable_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_stream.h | 404 struct dc_writeback_info *wb_info); 420 struct dc_writeback_info *wb_info);
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 9054 struct dc_writeback_info *wb_info; local 9059 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); 9060 if (!wb_info) { 9061 DRM_ERROR("Failed to allocate wb_info\n"); 9068 kfree(wb_info); 9075 kfree(wb_info); 9086 /* fill in wb_info */ 9087 wb_info->wb_enabled = true; 9089 wb_info [all...] |
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