/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CallLowering.cpp | 202 MVT NewVT = TLI->getRegisterTypeForCallingConv( local 211 if (NewVT.getSizeInBits() * NumParts != CurVT.getSizeInBits()) 226 if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i], 236 LLT NewLLT = getLLTForMVT(NewVT); 253 if (Handler.assignArg(i + Part, NewVT, NewVT, CCValAssign::Full, 268 LLT SmallTy = LLT::scalar(NewVT.getSizeInBits()); 286 if (Handler.assignArg(i + PartIdx, NewVT, NewVT, CCValAssig [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.h | 121 EVT NewVT) const override {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 218 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); local 231 NewVT, 2*OldElts), 238 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 242 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 375 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); local 395 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size());
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H A D | LegalizeVectorTypes.cpp | 288 EVT NewVT = N->getValueType(0).getVectorElementType(); local 290 NewVT, Op); 310 EVT NewVT = N->getValueType(0).getVectorElementType(); local 313 NewVT, Op, N->getOperand(1)); 1823 EVT NewVT = Inputs[0].getValueType(); local 1824 unsigned NewElts = NewVT.getVectorNumElements(); 1881 EVT EltVT = NewVT.getVectorElementType(); 1908 Output = DAG.getBuildVector(NewVT, dl, SVOps); 1911 Output = DAG.getUNDEF(NewVT); 1916 DAG.getUNDEF(NewVT) 4462 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); local 4479 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NewNumElts); local 4935 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); local 5128 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); local [all...] |
H A D | DAGCombiner.cpp | 4192 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 4193 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 4194 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 4195 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 4196 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 4197 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 4248 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 4249 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 4250 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 4251 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N 4324 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 4367 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); local 15696 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); local 18668 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), local 20546 EVT NewVT; local [all...] |
H A D | TargetLowering.cpp | 221 EVT NewVT = VT; local 226 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; 227 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && 228 isSafeMemOpType(NewVT.getSimpleVT())) 230 else if (NewVT == MVT::i64 && 234 NewVT = MVT::f64; 241 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); 242 if (NewVT == MVT::i8) 244 } while (!isSafeMemOpType(NewVT [all...] |
H A D | LegalizeDAG.cpp | 3115 EVT NewVT = 3118 assert(NewVT.bitsEq(VT)); 3121 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); 3122 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); 3126 NewVT.getVectorNumElements()/VT.getVectorNumElements(); 3142 VT = NewVT;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 982 MVT NewVT = MVT::getVectorVT(EltTy, EC); local 983 if (!TLI->isTypeLegal(NewVT)) 984 NewVT = EltTy; 985 IntermediateVT = NewVT; 987 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits().getFixedSize(); 993 MVT DestVT = TLI->getRegisterType(NewVT); 995 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1470 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); local 1471 if (!isTypeLegal(NewVT)) 1472 NewVT [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 319 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]); local 320 if (EVT(NewVT) != SplitEVTs[i]) { 329 LLT NewLLT(NewVT); 331 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx); 334 if (NewVT.isVector()) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 322 EVT NewVT) const override;
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H A D | HexagonISelLowering.cpp | 3436 ISD::LoadExtType ExtTy, EVT NewVT) const { 3438 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 499 EVT NewVT) const override;
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H A D | AArch64ISelLowering.cpp | 2759 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); local 2763 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); 2964 EVT NewVT = getExtensionTo64Bits(OrigTy); 2966 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); 9499 EVT NewVT) const { 9501 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) 11375 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2); local 11379 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 714 EVT NewVT) const { 716 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) 719 unsigned NewSize = NewVT.getStoreSizeInBits(); 2901 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); 2904 = DAG.getLoad(NewVT, SL, LN->getChain(), 2953 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); 2959 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
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H A D | R600ISelLowering.cpp | 1826 EVT NewVT = MVT::v4i32; local 1829 NewVT = VT; 1832 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements));
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H A D | SIISelLowering.cpp | 4741 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); local 4742 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); 4743 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); 4745 EVT SelectVT = NewVT; 4746 if (NewVT.bitsLT(MVT::i32)) { 4755 if (NewVT != SelectVT) 4756 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); 6051 EVT NewVT = NumVDataDwords > 1 ? local 6055 ResultTypes[0] = NewVT; 9896 EVT NewVT local [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 890 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; local 891 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT),
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 1486 EVT NewVT) const { 1489 if (NewVT.isVector() && !Load->hasOneUse())
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 1249 EVT NewVT) const override;
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H A D | X86ISelLowering.cpp | 5099 EVT NewVT) const { 9235 MVT NewVT = V0_LO.getSimpleValueType(); 9237 SDValue LO = DAG.getUNDEF(NewVT); 9238 SDValue HI = DAG.getUNDEF(NewVT); 9243 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI); 9245 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI); 9249 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO); 9252 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI); 12965 MVT NewVT = V.getSimpleValueType(); 12966 if (!NewVT [all...] |
/freebsd-13-stable/contrib/llvm-project/clang/lib/AST/ |
H A D | Decl.cpp | 2515 auto *NewVT = VarTemplate->getInstantiatedFromMemberTemplate(); local 2516 if (!NewVT) 2518 VarTemplate = NewVT;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCalls.cpp | 3416 VectorType *NewVT = cast<VectorType>(II->getType()); local 3419 CV0 = ConstantExpr::getIntegerCast(CV0, NewVT, /*isSigned=*/!Zext); 3420 CV1 = ConstantExpr::getIntegerCast(CV1, NewVT, /*isSigned=*/!Zext);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 8097 EVT NewVT = getVectorTyFromPredicateVector(VT); local 8115 return DAG.getNode(ISD::BITCAST, dl, NewVT, PredAsVector); 8146 EVT NewVT = PredAsVector.getValueType(); local 8149 SDValue Shuffled = DAG.getVectorShuffle(NewVT, dl, PredAsVector, 8150 DAG.getUNDEF(NewVT), ShuffleMask); 8579 EVT NewVT = NewV.getValueType(); 8581 for (unsigned i = 0, e = NewVT.getVectorNumElements(); i < e; i++, j++) { 8767 EVT NewVT = getExtensionTo64Bits(OrigTy); 8769 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 13924 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; local 13925 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops);
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