/freebsd-12-stable/sys/mips/ingenic/ |
H A D | jz4780_common.h | 35 #define WRITE4(_sc, _reg, _val) \ macro
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H A D | jz4780_intr.c | 92 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro 111 WRITE4(sc, JZ_ICMCR0, (1u << irq)); 113 WRITE4(sc, JZ_ICMCR1, (1u << (irq - 32))); 120 WRITE4(sc, JZ_ICMSR0, (1u << irq)); 122 WRITE4(sc, JZ_ICMSR1, (1u << (irq - 32))); 177 WRITE4(sc, JZ_ICMR0, 0xFFFFFFFF); 178 WRITE4(sc, JZ_ICMR1, 0xFFFFFFFF);
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/freebsd-12-stable/sys/arm/freescale/vybrid/ |
H A D | vf_dcu4.c | 232 WRITE4(sc, DCU_INT_STATUS, reg); 297 WRITE4(sc, DCU_DISP_SIZE, reg); 302 WRITE4(sc, DCU_HSYN_PARA, reg); 307 WRITE4(sc, DCU_VSYN_PARA, reg); 309 WRITE4(sc, DCU_BGND, 0); 310 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); 313 WRITE4(sc, DCU_SYNPOL, reg); 319 WRITE4(sc, DCU_THRESHOLD, reg); 322 WRITE4(sc, DCU_INT_MASK, 0xffffffff); 326 WRITE4(s [all...] |
H A D | vf_anadig.c | 143 WRITE4(sc, pll_ctrl, reg); 151 WRITE4(sc, pll_ctrl, reg); 171 WRITE4(sc, ANADIG_PLL4_CTRL, reg); 172 WRITE4(sc, ANADIG_PLL4_NUM, mfn); 173 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); 211 WRITE4(sc, ANADIG_REG_3P0, reg); 216 WRITE4(sc, USB_MISC(0), reg); 220 WRITE4(sc, USB_MISC(1), reg);
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H A D | vf_spi.c | 169 WRITE4(sc, SPI_MCR, reg); 173 WRITE4(sc, SPI_RSER, reg); 177 WRITE4(sc, SPI_MCR, reg); 195 WRITE4(sc, SPI_CTAR0, reg); 200 WRITE4(sc, SPI_CTAR0, reg); 225 WRITE4(sc, SPI_PUSHR, wreg); 236 WRITE4(sc, SPI_SR, reg);
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H A D | vf_adc.c | 177 WRITE4(sc, ADC_HC0, reg); 214 WRITE4(sc, ADC_CFG, reg); 219 WRITE4(sc, ADC_GC, reg); 224 WRITE4(sc, ADC_HC0, reg);
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H A D | vf_common.h | 33 #define WRITE4(_sc, _reg, _val) \ macro
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/freebsd-12-stable/sys/arm/freescale/imx/ |
H A D | imx_gpt.c | 54 #define WRITE4(_sc, _r, _v) \ macro 59 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 61 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 195 WRITE4(sc, IMX_GPT_CR, 0); 196 WRITE4(sc, IMX_GPT_IR, 0); 206 WRITE4(sc, IMX_GPT_CR, ctlreg); 216 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 229 WRITE4(sc, IMX_GPT_PR, prescale); 232 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 235 WRITE4(s [all...] |
H A D | imx6_sdma.c | 67 #define WRITE4(_sc, _reg, _val) \ macro 94 WRITE4(sc, SDMAARM_INTR, pending); 112 WRITE4(sc, SDMAARM_HSTART, (1 << i)); 137 WRITE4(sc, SDMAARM_HSTART, (1 << chn)); 149 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn)); 216 WRITE4(sc, SDMAARM_EVTOVR, reg); 224 WRITE4(sc, SDMAARM_HOSTOVR, reg); 232 WRITE4(sc, SDMAARM_DSPOVR, reg); 260 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 261 WRITE4(s [all...] |
H A D | imx6_audmux.c | 57 #define WRITE4(_sc, _reg, _val) \ macro 108 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg); 112 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
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/freebsd-12-stable/sys/dev/flash/ |
H A D | cqspi.c | 85 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro 161 WRITE4(sc, CQSPI_IRQSTAT, pending); 262 WRITE4(sc, CQSPI_FLASHCMDADDR, addr); 266 WRITE4(sc, CQSPI_FLASHCMD, reg); 269 WRITE4(sc, CQSPI_FLASHCMD, reg); 284 WRITE4(sc, CQSPI_FLASHCMD, reg); 286 WRITE4(sc, CQSPI_FLASHCMD, reg); 315 WRITE4(sc, CQSPI_FLASHCMD, reg); 318 WRITE4(sc, CQSPI_FLASHCMD, reg); 433 WRITE4(s [all...] |
/freebsd-12-stable/sys/arm/altera/socfpga/ |
H A D | socfpga_a10_manager.c | 120 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); 123 WRITE4(sc, FPGAMGR_DCLKCNT, npulses); 129 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); 179 WRITE4(sc, IMGCFG_CTRL_02, reg); 183 WRITE4(sc, IMGCFG_CTRL_02, reg); 188 WRITE4(sc, IMGCFG_CTRL_01, reg); 192 WRITE4(sc, IMGCFG_CTRL_00, reg); 197 WRITE4(sc, IMGCFG_CTRL_01, reg); 202 WRITE4(sc, IMGCFG_CTRL_02, reg); 212 WRITE4(s [all...] |
H A D | socfpga_common.h | 36 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
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H A D | socfpga_manager.c | 227 WRITE4(sc, FPGAMGR_CTRL, reg); 232 WRITE4(sc, FPGAMGR_CTRL, reg); 237 WRITE4(sc, FPGAMGR_CTRL, reg); 248 WRITE4(sc, FPGAMGR_CTRL, reg); 256 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS); 261 WRITE4(sc, FPGAMGR_CTRL, reg); 273 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); 276 WRITE4(sc, FPGAMGR_DCLKCNT, npulses); 282 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); 313 WRITE4(s [all...] |
/freebsd-12-stable/sys/arm/samsung/exynos/ |
H A D | exynos5_usb_phy.c | 180 WRITE4(sc, USB_DRD_PHYREG0, 0); 187 WRITE4(sc, USB_DRD_PHYPARAM0, reg); 188 WRITE4(sc, USB_DRD_PHYRESUME, 0); 192 WRITE4(sc, USB_DRD_LINKSYSTEM, reg); 197 WRITE4(sc, USB_DRD_PHYPARAM1, reg); 201 WRITE4(sc, USB_DRD_PHYUTMICLKSEL, reg); 206 WRITE4(sc, USB_DRD_PHYTEST, reg); 208 WRITE4(sc, USB_DRD_PHYUTMI, PHYUTMI_OTGDISABLE); 221 WRITE4(sc, USB_DRD_PHYCLKRST, reg); 224 WRITE4(s [all...] |
H A D | exynos5_spi.c | 130 WRITE4(sc, FB_CLK_SEL, FB_CLK_180); 134 WRITE4(sc, CH_CFG, reg); 155 WRITE4(sc, CH_CFG, reg); 157 WRITE4(sc, CH_CFG, reg); 162 WRITE4(sc, CS_REG, reg); 186 WRITE4(sc, CS_REG, reg);
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H A D | exynos5_xhci.c | 166 WRITE4(esc, GCTL, GCTL_CORESOFTRESET); 167 WRITE4(esc, GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 168 WRITE4(esc, GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 174 WRITE4(esc, GUSB3PIPECTL(0), reg); 178 WRITE4(esc, GUSB2PHYCFG(0), reg); 182 WRITE4(esc, GCTL, reg); 196 WRITE4(esc, GCTL, reg); 202 WRITE4(esc, GCTL, reg);
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H A D | exynos5_pmu.c | 113 WRITE4(sc, EXYNOS5_PWR_USBHOST_PHY, PHY_POWER_ON); 130 WRITE4(sc, EXYNOS5_USBDRD_PHY_CTRL, PHY_POWER_ON); 137 WRITE4(sc, EXYNOS5420_USBDRD1_PHY_CTRL, PHY_POWER_ON);
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H A D | exynos5_common.h | 31 #define WRITE4(_sc, _reg, _val) \ macro
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/freebsd-12-stable/sys/dev/mmc/host/ |
H A D | dwmmc_samsung.c | 49 #define WRITE4(_sc, _reg, _val) \ macro 105 WRITE4(sc, EMMCP_MPSBEGIN0, 0); 106 WRITE4(sc, EMMCP_SEND0, 0); 107 WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT |
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H A D | dwmmc.c | 77 #define WRITE4(_sc, _reg, _val) \ macro 187 WRITE4(sc, SDMMC_CTRL, reg); 387 WRITE4(sc, SDMMC_RINTSTS, reg); 402 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 404 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); 667 WRITE4(sc, SDMMC_PWREN, (0 << slot)); 669 WRITE4(sc, SDMMC_PWREN, (1 << slot)); 693 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); 696 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); 697 WRITE4(s [all...] |
/freebsd-12-stable/sys/dev/xilinx/ |
H A D | axi_quad_spi.c | 69 #define WRITE4(_sc, _reg, _val) \ macro 143 WRITE4(sc, SPI_SRR, SRR_RESET); 148 WRITE4(sc, SPI_CR, reg); 149 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ 152 WRITE4(sc, SPI_CR, reg); 166 WRITE4(sc, SPI_DTR, out_buf[i]); 201 WRITE4(sc, SPI_SSR, reg); 212 WRITE4(sc, SPI_SSR, reg);
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/freebsd-12-stable/sys/dev/altera/pio/ |
H A D | pio.c | 63 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro 128 WRITE4(sc, PIO_OUTSET, bit); 130 WRITE4(sc, PIO_OUTCLR, bit); 142 WRITE4(sc, PIO_INT_MASK, mask); 143 WRITE4(sc, PIO_DIR, dir);
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/freebsd-12-stable/sys/arm64/rockchip/clk/ |
H A D | rk_clk_pll.c | 59 #define WRITE4(_clk, off, val) \ macro 95 WRITE4(clk, sc->gate_offset, val); 221 WRITE4(clk, sc->mode_reg, reg); 228 WRITE4(clk, sc->base_offset, reg); 238 WRITE4(clk, sc->base_offset + 0x4, reg); 245 WRITE4(clk, sc->base_offset + 0x8, reg); 260 WRITE4(clk, sc->mode_reg, reg); 464 WRITE4(clk, sc->base_offset + 0xC, reg); 469 WRITE4(clk, sc->base_offset, reg); 477 WRITE4(cl [all...] |
/freebsd-12-stable/sys/mips/mediatek/ |
H A D | mtk_intr_gic.c | 107 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val)) macro 127 WRITE4(sc, MTK_INTENA, (1u << (irq))); 134 WRITE4(sc, MTK_INTDIS, (1u << (irq))); 190 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); 193 WRITE4(sc, MTK_INTTRIG, 0x00000000); 196 WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF); 202 WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0)); 203 WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0));
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