/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const { 80 Cond.push_back(MachineOperand::CreateImm(Opc)); 83 Cond.push_back(Inst->getOperand(i)); 89 SmallVectorImpl<MachineOperand> &Cond, 92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); 99 DebugLoc DL, ArrayRef<MachineOperand> Cond) const { 100 unsigned Opc = Cond[0].getImm(); 104 for (unsigned i = 1; i < Cond.size(); ++i) { 105 if (Cond[i].isReg()) 106 MIB.addReg(Cond[ 86 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 115 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument 177 AnalyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, SmallVectorImpl<MachineInstr *> &BranchInstrs) const argument [all...] |
H A D | MipsInstrInfo.h | 56 SmallVectorImpl<MachineOperand> &Cond, 62 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 66 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 70 SmallVectorImpl<MachineOperand> &Cond, 139 SmallVectorImpl<MachineOperand> &Cond) const; 142 ArrayRef<MachineOperand> Cond) const;
|
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyInstrInfo.cpp | 66 SmallVectorImpl<MachineOperand> &Cond, 80 Cond.push_back(MachineOperand::CreateImm(true)); 81 Cond.push_back(MI.getOperand(0)); 91 Cond.push_back(MachineOperand::CreateImm(false)); 92 Cond.push_back(MI.getOperand(0)); 135 ArrayRef<MachineOperand> Cond, 137 if (Cond.empty()) { 145 assert(Cond.size() == 2 && "Expected a flag and a successor block"); 147 if (Cond[0].getImm()) { 149 .addOperand(Cond[ 63 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool ) const argument 132 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument [all...] |
H A D | WebAssemblyInstrInfo.h | 43 SmallVectorImpl<MachineOperand> &Cond, 47 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 50 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
H A D | WebAssemblyLowerBrUnless.cpp | 69 unsigned Cond = MI->getOperand(0).getReg(); local 73 if (MFI.isVRegStackified(Cond)) { 74 assert(MRI.hasOneDef(Cond)); 75 MachineInstr *Def = MRI.getVRegDef(Cond); 116 .addReg(Cond) 118 Cond = Tmp; 126 .addReg(Cond)
|
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 55 SmallVectorImpl<MachineOperand> &Cond, 59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 82 SmallVectorImpl<MachineOperand> &Cond) const override;
|
H A D | XCoreInstrInfo.cpp | 196 SmallVectorImpl<MachineOperand> &Cond, 224 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 225 Cond.push_back(LastInst->getOperand(0)); 246 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 247 Cond.push_back(SecondLastInst->getOperand(0)); 279 ArrayRef<MachineOperand> Cond, 283 assert((Cond.size() == 2 || Cond.size() == 0) && 287 if (Cond.empty()) { 292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[ 194 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 277 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.h | 76 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 80 SmallVectorImpl<MachineOperand> &Cond, 85 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
H A D | MSP430InstrInfo.cpp | 128 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 129 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 131 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 155 Cond[0].setImm(CC); 173 SmallVectorImpl<MachineOperand> &Cond, 208 Cond.clear(); 232 if (Cond.empty()) { 235 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 241 assert(Cond.size() == 1); 249 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[ 170 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument [all...] |
H A D | MSP430BranchSelector.cpp | 152 SmallVector<MachineOperand, 1> Cond; local 153 Cond.push_back(I->getOperand(1)); 156 TII->ReverseBranchCondition(Cond); 158 .addImm(4).addOperand(Cond[0]);
|
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.h | 70 SmallVectorImpl<MachineOperand> &Cond, 76 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 80 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
H A D | SparcInstrInfo.cpp | 137 SmallVectorImpl<MachineOperand> &Cond) { 138 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm())); 145 SmallVectorImpl<MachineOperand> &Cond, 166 parseCondBranch(LastInst, TBB, Cond); 200 parseCondBranch(SecondLastInst, TBB, Cond); 228 ArrayRef<MachineOperand> Cond, 231 assert((Cond.size() == 1 || Cond.size() == 0) && 234 if (Cond.empty()) { 241 unsigned CC = Cond[ 136 parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl<MachineOperand> &Cond) argument 142 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 226 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ConstraintManager.h | 68 DefinedSVal Cond, 75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { argument 76 ProgramStateRef StTrue = assume(State, Cond, true); 78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary 86 assert(assume(State, Cond, false) && "System is over constrained."); 91 ProgramStateRef StFalse = assume(State, Cond, false); 114 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary
|
/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 150 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { 167 Cond.push_back(LastInst->getOperand(0)); 185 Cond.push_back(SecondLastInst->getOperand(0)); 231 ArrayRef<MachineOperand> Cond, DebugLoc DL) const { 234 assert((Cond.size() == 1 || Cond.size() == 0) && 239 if (Cond.empty()) // Unconditional branch 242 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) 248 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); 148 AnalyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 229 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument
|
H A D | NVPTXInstrInfo.h | 64 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; 68 ArrayRef<MachineOperand> Cond, DebugLoc DL) const override;
|
/freebsd-11.0-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ |
H A D | SimpleConstraintManager.cpp | 69 DefinedSVal Cond, 72 if (Optional<Loc> LV = Cond.getAs<Loc>()) { 81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); 84 return assume(state, Cond.castAs<NonLoc>(), Assumption); 115 NonLoc Cond, 120 if (!canReasonAbout(Cond)) { 122 SymbolRef sym = Cond.getAsSymExpr(); 126 switch (Cond.getSubKind()) { 131 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); 182 bool b = Cond 68 assume(ProgramStateRef state, DefinedSVal Cond, bool Assumption) argument 114 assumeAux(ProgramStateRef state, NonLoc Cond, bool Assumption) argument [all...] |
H A D | SimpleConstraintManager.h | 36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond, 39 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption); 109 NonLoc Cond,
|
/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/ |
H A D | BPFInstrInfo.h | 49 SmallVectorImpl<MachineOperand> &Cond, 54 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
H A D | BPFInstrInfo.cpp | 81 SmallVectorImpl<MachineOperand> &Cond, 111 Cond.clear(); 136 ArrayRef<MachineOperand> Cond, 141 if (Cond.empty()) { 78 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 133 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument
|
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 1249 ISD::CondCode Cond, bool foldBooleans, 1254 switch (Cond) { 1270 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); 1287 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1289 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1292 Cond = ISD::SETNE; 1296 Cond = ISD::SETEQ; 1300 Zero, Cond); 1317 if ((Cond 1248 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 84 SmallVectorImpl<MachineOperand> &Cond, 103 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 178 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 191 ArrayRef<MachineOperand> Cond) const override; 341 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const; 369 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const; 375 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg, 397 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
|
/freebsd-11.0-release/contrib/llvm/tools/clang/lib/Sema/ |
H A D | ScopeInfo.cpp | 168 if (const ConditionalOperator *Cond = dyn_cast<ConditionalOperator>(E)) { 169 markSafeWeakUse(Cond->getTrueExpr()); 170 markSafeWeakUse(Cond->getFalseExpr()); 174 if (const BinaryConditionalOperator *Cond = 176 markSafeWeakUse(Cond->getCommon()); 177 markSafeWeakUse(Cond->getFalseExpr());
|
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.h | 139 SmallVectorImpl<MachineOperand> &Cond, 143 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 146 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 147 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 150 DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, 197 ArrayRef<MachineOperand> Cond) const;
|
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 447 SmallVectorImpl<MachineOperand> &Cond, 474 Cond.push_back(LastInst->getOperand(0)); 475 Cond.push_back(LastInst->getOperand(1)); 482 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); 483 Cond.push_back(LastInst->getOperand(0)); 490 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); 491 Cond.push_back(LastInst->getOperand(0)); 500 Cond.push_back(MachineOperand::CreateImm(1)); 501 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 511 Cond 445 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 637 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, DebugLoc DL) const argument 683 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument 723 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, unsigned DestReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument [all...] |
H A D | PPCInstrInfo.h | 170 SmallVectorImpl<MachineOperand> &Cond, 174 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 178 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 181 DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, 202 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|