/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/powerpc/boot/ |
H A D | cuboot-c2k.c | 26 static u8 *bridge_base; variable 53 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); 58 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); 60 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 77 mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0, 111 mv64x60_config_cpu2pci_window(bridge_base, bus, 117 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), 126 mem_size = mv64x60_get_mem_size(bridge_base); 142 if (bridge_base != 0) { 143 temp = in_le32((u32 *)(bridge_base [all...] |
H A D | mv64x60.c | 181 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset) argument 183 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), 185 return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data)); 188 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset, argument 191 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), 193 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val); 280 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, argument 286 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f); 287 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf); 288 out_le32((u32 *)(bridge_base 411 mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, u8 bus, u32 mem_size, u32 acc_bits) argument 495 mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, u32 pci_base_lo, u32 cpu_base, u32 size, struct mv64x60_cpu2pci_win *offset_tbl) argument 514 mv64x60_get_mem_size(u8 *bridge_base) argument [all...] |
H A D | mv64x60.h | 48 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, 50 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, 53 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, 55 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, 57 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, 60 u32 mv64x60_get_mem_size(u8 *bridge_base);
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H A D | prpmc2800.c | 38 static u8 *bridge_base; variable 342 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); 343 mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size, 362 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); 364 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 390 mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi, 395 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 408 mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base); 478 if (bridge_base != 0) { 479 temp = in_le32((u32 *)(bridge_base [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/boot/ |
H A D | cuboot-c2k.c | 26 static u8 *bridge_base; variable 53 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); 58 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); 60 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 77 mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0, 111 mv64x60_config_cpu2pci_window(bridge_base, bus, 117 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), 126 mem_size = mv64x60_get_mem_size(bridge_base); 142 if (bridge_base != 0) { 143 temp = in_le32((u32 *)(bridge_base [all...] |
H A D | mv64x60.c | 181 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset) argument 183 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), 185 return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data)); 188 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset, argument 191 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), 193 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val); 280 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, argument 286 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f); 287 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf); 288 out_le32((u32 *)(bridge_base 411 mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, u8 bus, u32 mem_size, u32 acc_bits) argument 495 mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, u32 pci_base_lo, u32 cpu_base, u32 size, struct mv64x60_cpu2pci_win *offset_tbl) argument 514 mv64x60_get_mem_size(u8 *bridge_base) argument [all...] |
H A D | mv64x60.h | 48 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, 50 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, 53 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, 55 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, 57 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, 60 u32 mv64x60_get_mem_size(u8 *bridge_base);
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H A D | prpmc2800.c | 38 static u8 *bridge_base; variable 342 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); 343 mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size, 362 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); 364 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 390 mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi, 395 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 408 mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base); 478 if (bridge_base != 0) { 479 temp = in_le32((u32 *)(bridge_base [all...] |