Lines Matching refs:bridge_base
181 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset)
183 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
185 return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));
188 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset,
191 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
193 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val);
280 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
286 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f);
287 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf);
288 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff);
293 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
299 base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo))
302 size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size))
306 out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base);
307 out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size);
308 out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base);
309 out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size);
310 out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base);
311 out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size);
314 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot);
315 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot);
316 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot);
317 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot);
318 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot);
319 out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot);
320 out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot);
321 out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot);
322 out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot);
325 out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE),
328 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables);
329 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables);
330 out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables);
411 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
419 out_le32((u32 *)(bridge_base + bar_enable), enables);
422 out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0);
431 i = in_le32((u32 *)(bridge_base + offset));
432 out_le32((u32 *)(bridge_base + offset), i & ~0x1);
437 mv64x60_cfg_write(bridge_base, hose, bus,
440 mv64x60_cfg_write(bridge_base, hose, bus,
443 out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size);
446 out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0);
447 out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits);
448 out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size);
451 i = (u32)bridge_base;
454 mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
456 mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
460 out_le32((u32 *)(bridge_base + bar_enable), enables);
495 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
501 out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base);
504 out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi),
506 out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo),
510 out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);
514 u32 mv64x60_get_mem_size(u8 *bridge_base)
519 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
523 v = in_le32((u32*)(bridge_base