Lines Matching refs:bridge_base
38 static u8 *bridge_base;
342 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
343 mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size,
362 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
364 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
390 mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi,
395 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
408 mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base);
478 if (bridge_base != 0) {
479 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
481 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
483 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
485 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
487 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
489 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
491 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
493 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
495 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
497 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
499 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
501 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
503 out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
553 bridge_base = mv64x60_get_bridge_base();