Searched hist:239676 (Results 1 - 8 of 8) sorted by relevance
/freebsd-10.2-release/share/man/man4/ | ||
H A D | altera_jtag_uart.4 | 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
H A D | Makefile | diff 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
/freebsd-10.2-release/sys/dev/altera/jtag_uart/ | ||
H A D | altera_jtag_uart.h | 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
H A D | altera_jtag_uart_nexus.c | 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
H A D | altera_jtag_uart_cons.c | 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
H A D | altera_jtag_uart_fdt.c | 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
H A D | altera_jtag_uart_tty.c | 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
/freebsd-10.2-release/sys/mips/beri/ | ||
H A D | files.beri | diff 239676 Sat Aug 25 11:41:45 MDT 2012 rwatson Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core, which presents a UART-like interface over the Avalon bus that can be addressed over JTAG. This IP core proves extremely useful, allowing us to connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard and soft cores. As interrupts are optionally configured for this soft core, we support both interrupt-driven and polled modes of operation, which must be selected using device.hints. UART instances appear in /dev as ttyu0, ttyu1, etc. However, it also contains a number of quirks, which make it difficult to tell when JTAG is connected, and some buffering issues. We work around these as best we can, using various heuristics. While the majority of this device driver is not only not BERI-specific, but also not MIPS-specific, for now add its defines in the BERI files list, as the console-level parts are aware of where the first JTAG UART is mapped on Avalon, and contain MIPS-specific address translation, to use before Newbus and device.hints are available. Sponsored by: DARPA, AFRL |
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