Searched refs:val (Results 1 - 25 of 10961) sorted by path

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/linux-master/arch/alpha/include/asm/
H A Dmc146818rtc.h23 #define CMOS_WRITE(val, addr) ({ \
25 outb_p((val),RTC_PORT(1)); \
H A Dvga.h17 static inline void scr_writew(u16 val, volatile u16 *addr) argument
20 __raw_writew(val, (volatile u16 __iomem *) addr);
22 *addr = val;
H A Dword-at-a-time.h21 /* Return nonzero if val has a zero */
22 static inline unsigned long has_zero(unsigned long val, unsigned long *bits, const struct word_at_a_time *c) argument
24 unsigned long zero_locations = __kernel_cmpbge(0, val);
29 static inline unsigned long prep_zero_mask(unsigned long val, unsigned long bits, const struct word_at_a_time *c) argument
H A Dxchg.h18 ____xchg(_u8, volatile char *m, unsigned long val) argument
34 : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
35 : "r" ((long)m), "1" (val) : "memory");
41 ____xchg(_u16, volatile short *m, unsigned long val) argument
57 : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
58 : "r" ((long)m), "1" (val) : "memory");
64 ____xchg(_u32, volatile int *m, unsigned long val) argument
76 : "=&r" (val), "=&r" (dummy), "=m" (*m)
77 : "rI" (val), "m" (*m) : "memory");
79 return val;
83 ____xchg(_u64, volatile long *m, unsigned long val) argument
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/linux-master/arch/alpha/include/uapi/asm/
H A Dcompiler.h14 # define __kernel_insbl(val, shift) __builtin_alpha_insbl(val, shift)
15 # define __kernel_inswl(val, shift) __builtin_alpha_inswl(val, shift)
16 # define __kernel_insql(val, shift) __builtin_alpha_insql(val, shift)
17 # define __kernel_inslh(val, shift) __builtin_alpha_inslh(val, shift)
18 # define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shif
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/linux-master/arch/arc/include/asm/
H A Ddisasm.h110 void set_reg(int reg, long val, struct pt_regs *regs,
/linux-master/arch/arc/lib/
H A Dmemcpy-archs-unaligned.S24 mov r3, r0 ; don;t clobber ret val
H A Dmemcpy-archs.S40 mov r3, r0 ; don;t clobber ret val
/linux-master/arch/arm/common/
H A DbL_switcher_dummy_if.c21 unsigned char val[3]; local
30 if (copy_from_user(val, buf, 3))
34 if (val[0] < '0' || val[0] > '9' ||
35 val[1] != ',' ||
36 val[2] < '0' || val[2] > '1')
39 cpu = val[0] - '0';
40 cluster = val[2] - '0';
H A Dkrait-l2-accessors.c12 void krait_set_l2_indirect_reg(u32 addr, u32 val) argument
23 asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
32 u32 val; local
42 asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
46 return val;
/linux-master/arch/arm/include/asm/
H A Dcti.h88 unsigned long val; local
90 val = __raw_readl(base + CTIINEN + trig_in * 4);
91 val |= BIT(chan);
92 __raw_writel(val, base + CTIINEN + trig_in * 4);
94 val = __raw_readl(base + CTIOUTEN + trig_out * 4);
95 val |= BIT(chan);
96 __raw_writel(val, base + CTIOUTEN + trig_out * 4);
130 unsigned long val; local
132 val = __raw_readl(base + CTIINTACK);
133 val |
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H A Dkrait-l2-accessors.h6 extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
H A Dmc146818rtc.h26 #define CMOS_WRITE(val, addr) ({ \
28 outb_p((val),RTC_PORT(1)); \
/linux-master/arch/arm/include/asm/hardware/
H A Dcp14.h12 #define dbg_write(val, reg) WCP14_##reg(val)
14 #define etm_write(val, reg) WCP14_##reg(val)
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR1
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H A Dioc.h20 #define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
H A Diomd.h22 #define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
23 #define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
H A Dmemc.h14 extern void memc_write(unsigned int reg, unsigned long val);
/linux-master/arch/arm/include/asm/xen/
H A Devents.h20 #define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((long long*)(ptr),\
22 counter), (val))
/linux-master/arch/arm/kernel/
H A Dsmp_scu.c77 unsigned int val; local
83 val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
84 val &= ~SCU_CPU_STATUS_MASK;
85 val |= mode;
86 writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
114 unsigned int val; local
120 val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
121 val &= SCU_CPU_STATUS_MASK;
123 return val;
/linux-master/arch/arm/mach-artpec/
H A Dboard-artpec6.c45 static void artpec6_l2c310_write_sec(unsigned long val, unsigned reg) argument
49 arm_smccc_smc(SECURE_OP_L2C_WRITEREG, reg, val, 0,
/linux-master/arch/arm/mach-footbridge/
H A Dnetwinder-hw.c46 static inline void wb977_wb(int reg, int val) argument
49 outb(val, 0x371);
52 static inline void wb977_ww(int reg, int val) argument
55 outb(val >> 8, 0x371);
57 outb(val & 255, 0x371);
/linux-master/arch/arm/mach-imx/
H A Dsystem.c90 unsigned int val; local
102 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
103 val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
108 val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
109 val |= 15;
111 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
/linux-master/arch/arm/mach-omap2/
H A Dprm44xx_54xx.h32 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
H A Dprminst44xx.c67 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) argument
72 writel_relaxed(val, _prm_bases[part].va + inst + idx);
H A Dprminst44xx.h21 extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);

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