1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *  arch/arm/include/asm/hardware/ioc.h
4 *
5 *  Copyright (C) Russell King
6 *
7 *  Use these macros to read/write the IOC.  All it does is perform the actual
8 *  read/write.
9 */
10#ifndef __ASMARM_HARDWARE_IOC_H
11#define __ASMARM_HARDWARE_IOC_H
12
13#ifndef __ASSEMBLY__
14
15/*
16 * We use __raw_base variants here so that we give the compiler the
17 * chance to keep IOC_BASE in a register.
18 */
19#define ioc_readb(off)		__raw_readb(IOC_BASE + (off))
20#define ioc_writeb(val,off)	__raw_writeb(val, IOC_BASE + (off))
21
22#endif
23
24#define IOC_CONTROL	(0x00)
25#define IOC_KARTTX	(0x04)
26#define IOC_KARTRX	(0x04)
27
28#define IOC_IRQSTATA	(0x10)
29#define IOC_IRQREQA	(0x14)
30#define IOC_IRQCLRA	(0x14)
31#define IOC_IRQMASKA	(0x18)
32
33#define IOC_IRQSTATB	(0x20)
34#define IOC_IRQREQB	(0x24)
35#define IOC_IRQMASKB	(0x28)
36
37#define IOC_FIQSTAT	(0x30)
38#define IOC_FIQREQ	(0x34)
39#define IOC_FIQMASK	(0x38)
40
41#define IOC_T0CNTL	(0x40)
42#define IOC_T0LTCHL	(0x40)
43#define IOC_T0CNTH	(0x44)
44#define IOC_T0LTCHH	(0x44)
45#define IOC_T0GO	(0x48)
46#define IOC_T0LATCH	(0x4c)
47
48#define IOC_T1CNTL	(0x50)
49#define IOC_T1LTCHL	(0x50)
50#define IOC_T1CNTH	(0x54)
51#define IOC_T1LTCHH	(0x54)
52#define IOC_T1GO	(0x58)
53#define IOC_T1LATCH	(0x5c)
54
55#define IOC_T2CNTL	(0x60)
56#define IOC_T2LTCHL	(0x60)
57#define IOC_T2CNTH	(0x64)
58#define IOC_T2LTCHH	(0x64)
59#define IOC_T2GO	(0x68)
60#define IOC_T2LATCH	(0x6c)
61
62#define IOC_T3CNTL	(0x70)
63#define IOC_T3LTCHL	(0x70)
64#define IOC_T3CNTH	(0x74)
65#define IOC_T3LTCHH	(0x74)
66#define IOC_T3GO	(0x78)
67#define IOC_T3LATCH	(0x7c)
68
69#endif
70