/linux-master/arch/m68k/fpsp040/ |
H A D | x_operr.S | 243 | This routine stores the data in d0, for the given size in d1,
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/linux-master/arch/mips/include/asm/ |
H A D | mips-r2-to-r6-emul.h | 23 u64 stores; member in struct:mips_r2_emulator_stats
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H A D | fpu_emulator.h | 27 unsigned long stores; member in struct:mips_fpu_emulator_stats
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/linux-master/arch/sparc/kernel/ |
H A D | dtlb_prot.S | 12 * [TL == 0] 1) User stores to readonly pages. 13 * [TL == 0] 2) Nucleus stores to user readonly pages. 14 * [TL > 0] 3) Nucleus stores to user readonly stack frame. 20 membar #Sync ! Synchronize stores
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/linux-master/arch/sparc/lib/ |
H A D | M7memcpy.S | 128 * between the first initializing store and the final stores. 434 ! lines from memory. Use ST_CHUNK stores to first element of each cache 437 ! Initial stores using MRU version of BIS to keep cache line in 444 ! We use STORE_MRU_ASI for the first seven stores to each cache line 452 ! the store miss buffer. Then the matching stores for all those
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H A D | M7memset.S | 32 * For small 6 or fewer bytes stores, bytes will be stored. 34 * For less than 32 bytes stores, align the address on 4 byte boundary. 41 * Using BIS stores, set the first long word of each 46 * Using BIS stores, set the first long word of each of 66 * similar to prefetching for normal stores. 71 * BIS stores must be followed by a membar #StoreStore. The benefit of 79 * store and the final stores. 167 ! Use long word stores. 179 and %o2, 63, %o3 ! %o3 = bytes left after blk stores. 187 ! initial cache-clearing stores [all...] |
/linux-master/arch/alpha/lib/ |
H A D | ev6-copy_user.S | 64 EXI( ldbu $1,0($17) ) # .. .. .. L : Keep loads separate from stores
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/linux-master/arch/arm/crypto/ |
H A D | aes-ce-core.S | 328 vst1.8 {q2}, [r4] @ overlapping stores 366 vst1.8 {q1}, [r4] @ overlapping stores 584 vst1.8 {q2}, [r4] @ overlapping stores 676 vst1.8 {q2}, [r4] @ overlapping stores
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/linux-master/arch/mips/kernel/ |
H A D | mips-r2-to-r6-emul.c | 1418 MIPS_R2_STATS(stores); 1488 MIPS_R2_STATS(stores); 1845 MIPS_R2_STATS(stores); 1963 MIPS_R2_STATS(stores); 2269 seq_printf(s, "stores\t\t%ld\t%ld\n", 2270 (unsigned long)__this_cpu_read(mipsr2emustats.stores), 2271 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores)); 2326 __this_cpu_write((mipsr2emustats).stores, 0); 2327 __this_cpu_write((mipsr2bdemustats).stores, 0);
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/linux-master/arch/mips/math-emu/ |
H A D | cp1emu.c | 1070 MIPS_FPU_EMU_INC_STATS(stores); 1104 MIPS_FPU_EMU_INC_STATS(stores); 1501 MIPS_FPU_EMU_INC_STATS(stores); 1610 MIPS_FPU_EMU_INC_STATS(stores);
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H A D | me-debugfs.c | 56 __this_cpu_write((fpuemustats).stores, 0); 212 FPU_STAT_CREATE(stores);
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/linux-master/arch/powerpc/lib/ |
H A D | memcpy_64.S | 115 ld r9,0(r4) # 3+2n loads, 2+2n stores 127 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
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/linux-master/arch/powerpc/perf/ |
H A D | power10-pmu.c | 128 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES); 144 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
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H A D | power8-pmu.c | 146 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
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H A D | power9-pmu.c | 175 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
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/linux-master/arch/x86/crypto/ |
H A D | aesni-intel_asm.S | 553 # Reads DLEN bytes starting at DPTR and stores in XMMDst
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H A D | aesni-intel_avx-x86_64.S | 681 # Reads DLEN bytes starting at DPTR and stores in XMMDst
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/linux-master/arch/x86/events/intel/ |
H A D | core.c | 375 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 2126 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 5394 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 5482 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 5785 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
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/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | cwsr_trap_handler_gfx10.asm | 1312 // If TRAPSTS.XNACK_ERROR=1 then TCP stores will fail.
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H A D | cwsr_trap_handler_gfx9.asm | 47 var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 971 // If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail.
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/linux-master/fs/xfs/scrub/ |
H A D | trace.h | 1115 __field(unsigned long long, stores) 1127 __entry->stores = si->stores; 1137 "xfino 0x%lx loads %llu stores %llu compares %llu heapsorts %llu stack_depth %u/%u error %d", 1144 __entry->stores,
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H A D | xfarray.c | 375 # define xfarray_sort_bump_stores(si) do { (si)->stores++; } while (0)
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H A D | xfarray.h | 139 uint64_t stores; member in struct:xfarray_sortinfo
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/linux-master/tools/perf/util/ |
H A D | parse-events.l | 172 lc_op_result (load|loads|read|store|stores|write|prefetch|prefetches|speculative-read|speculative-load|refs|Reference|ops|access|misses|miss)
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/linux-master/tools/testing/selftests/kvm/x86_64/ |
H A D | pmu_event_filter_test.c | 57 uint64_t stores; member in struct:__anon1666 447 const uint64_t stores = rdmsr(msr_base + 1); local 458 pmc_results.stores = rdmsr(msr_base + 1) - stores; 530 * For each test, the guest enables 3 PMU counters (loads, stores, 531 * loads + stores). The filter is then set in KVM with the masked events 552 .msg = "Only allow stores.", 561 .msg = "Only allow loads + stores.", 571 .msg = "Only allow loads and stores.", 582 .msg = "Only allow loads and loads + stores [all...] |