/linux-master/arch/mips/pci/ |
H A D | fixup-malta.c | 70 unsigned char reg_val; local 84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val); 85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) 88 pci_irq[PCIA+i] = piixirqmap[reg_val & 98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val); 99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | 109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, ®_val); 110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; 111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); 124 unsigned char reg_val; local [all...] |
/linux-master/drivers/media/usb/as102/ |
H A D | as10x_cmd.h | 288 struct as10x_register_value reg_val; member in struct:as10x_fw_context::__anon169 299 struct as10x_register_value reg_val; member in struct:as10x_fw_context::__anon170 315 struct as10x_register_value reg_val; member in struct:as10x_set_register::__anon171 341 struct as10x_register_value reg_val; member in struct:as10x_get_register::__anon174
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H A D | as10x_cmd_cfg.c | 63 *pvalue = le32_to_cpu((__force __le32)prsp->body.context.rsp.reg_val.u.value32); 94 /* pcmd->body.context.req.reg_val.mode initialization is not required */ 95 pcmd->body.context.req.reg_val.u.value32 = (__force u32)cpu_to_le32(value);
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/linux-master/drivers/media/usb/dvb-usb-v2/ |
H A D | af9035.h | 25 struct reg_val { struct
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/linux-master/drivers/net/ethernet/samsung/sxgbe/ |
H A D | sxgbe_dma.c | 23 u32 reg_val; local 25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); 33 reg_val |= SXGBE_DMA_AXI_UNDEF_BURST; 36 reg_val |= (burst_map << SXGBE_DMA_BLENMAP_LSHIFT); 38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); 47 u32 reg_val; local 50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); 53 reg_val |= SXGBE_DMA_PBL_X8MODE; 54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); 56 reg_val [all...] |
H A D | sxgbe_mtl.c | 23 u32 reg_val; local 25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); 26 reg_val &= ETS_RST; 31 reg_val &= ETS_WRR; 34 reg_val |= ETS_WFQ; 37 reg_val |= ETS_DWRR; 40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); 44 reg_val &= RAA_SP; 47 reg_val |= RAA_WSP; 50 writel(reg_val, ioadd 64 u32 fifo_bits, reg_val; local 76 u32 fifo_bits, reg_val; local 87 u32 reg_val; local 96 u32 reg_val; local 106 u32 reg_val; local 117 u32 reg_val; local 127 u32 reg_val; local 138 u32 reg_val; local 148 u32 reg_val; local 158 u32 reg_val; local 168 u32 reg_val; local 180 u32 reg_val; local 211 u32 reg_val; local [all...] |
/linux-master/drivers/thermal/intel/ |
H A D | intel_bxt_pmic_thermal.c | 160 u8 reg_val, mask, irq_stat; local 181 reg_val = (u8)ret; 201 regmap_write(regmap, reg, reg_val & mask);
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/linux-master/drivers/watchdog/ |
H A D | da9052_wdt.c | 34 u8 reg_val; member in struct:__anon28 84 da9052_wdt_maps[i].reg_val);
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H A D | da9055_wdt.c | 37 u8 reg_val; member in struct:__anon9932 68 da9055_wdt_maps[i].reg_val <<
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/linux-master/include/linux/mfd/da9052/ |
H A D | da9052.h | 186 unsigned char reg_val) 190 ret = regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val); 184 da9052_reg_update(struct da9052 *da9052, unsigned char reg, unsigned char bit_mask, unsigned char reg_val) argument
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/linux-master/include/linux/mfd/da9055/ |
H A D | core.h | 69 unsigned char reg_val) 71 return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val); 67 da9055_reg_update(struct da9055 *da9055, unsigned char reg, unsigned char bit_mask, unsigned char reg_val) argument
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/linux-master/arch/arm/mach-qcom/ |
H A D | platsmp.c | 84 u32 reg_val; local 103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; 104 writel(reg_val, reg + APCS_CPU_PWR_CTL); 111 reg_val &= ~CORE_MEM_CLAMP; 112 writel(reg_val, reg + APCS_CPU_PWR_CTL); 113 reg_val |= L2DT_SLP; 114 writel(reg_val, reg + APCS_CPU_PWR_CTL); 117 reg_val = (reg_val | BIT(17)) & ~CLAMP; 118 writel(reg_val, re 219 unsigned reg_val; local [all...] |
/linux-master/arch/arm/plat-orion/ |
H A D | gpio.c | 496 u32 reg_val; local 500 reg_val = irq_reg_readl(gc, ct->regs.mask); 501 reg_val |= mask; 502 irq_reg_writel(gc, reg_val, ct->regs.mask); 511 u32 reg_val; local 514 reg_val = irq_reg_readl(gc, ct->regs.mask); 515 reg_val &= ~mask; 516 irq_reg_writel(gc, reg_val, ct->regs.mask);
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/linux-master/arch/mips/include/asm/ |
H A D | mips-cps.h | 75 uint##sz##_t reg_val = read_##unit##_##name(); \ 76 reg_val &= ~mask; \ 77 reg_val |= val; \ 78 write_##unit##_##name(reg_val); \
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/linux-master/arch/mips/kernel/ |
H A D | traps.c | 1836 unsigned int reg_val; local 1841 reg_val = read_c0_cacheerr(); 1842 printk("c0_cacheerr == %08x\n", reg_val); 1845 reg_val & (1<<30) ? "secondary" : "primary", 1846 reg_val & (1<<31) ? "data" : "insn"); 1850 reg_val & (1<<29) ? "ED " : "", 1851 reg_val & (1<<28) ? "ET " : "", 1852 reg_val & (1<<27) ? "ES " : "", 1853 reg_val & (1<<26) ? "EE " : "", 1854 reg_val 1884 unsigned int reg_val; local [all...] |
/linux-master/arch/powerpc/platforms/powernv/ |
H A D | opal-fadump.h | 83 __be64 reg_val; member in struct:hdat_fadump_reg_entry 88 u64 reg_val) 92 regs->gpr[reg_num] = reg_val; 98 regs->ctr = reg_val; 101 regs->link = reg_val; 104 regs->xer = reg_val; 107 regs->dar = reg_val; 110 regs->dsisr = reg_val; 113 regs->nip = reg_val; 116 regs->msr = reg_val; 86 opal_fadump_set_regval_regnum(struct pt_regs *regs, u32 reg_type, u32 reg_num, u64 reg_val) argument [all...] |
/linux-master/arch/powerpc/platforms/pseries/ |
H A D | rtas-fadump.c | 257 static void __init rtas_fadump_set_regval(struct pt_regs *regs, u64 reg_id, u64 reg_val) argument 263 regs->gpr[i] = (unsigned long)reg_val; 265 regs->nip = (unsigned long)reg_val; 267 regs->msr = (unsigned long)reg_val; 269 regs->ctr = (unsigned long)reg_val; 271 regs->link = (unsigned long)reg_val; 273 regs->xer = (unsigned long)reg_val; 275 regs->ccr = (unsigned long)reg_val; 277 regs->dar = (unsigned long)reg_val; 279 regs->dsisr = (unsigned long)reg_val; [all...] |
/linux-master/arch/riscv/include/asm/ |
H A D | kvm_vcpu_sbi.h | 74 unsigned long *reg_val); 76 unsigned long reg_val);
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/linux-master/arch/riscv/kvm/ |
H A D | vcpu_fp.c | 87 void *reg_val; local 94 reg_val = &cntx->fp.f.fcsr; 97 reg_val = &cntx->fp.f.f[reg_num]; 105 reg_val = &cntx->fp.d.fcsr; 110 reg_val = &cntx->fp.d.f[reg_num]; 116 if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) 132 void *reg_val; local 139 reg_val = &cntx->fp.f.fcsr; 142 reg_val = &cntx->fp.f.f[reg_num]; 150 reg_val [all...] |
H A D | vcpu_onereg.c | 191 unsigned long reg_val; local 198 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; 203 reg_val = riscv_cbom_block_size; 208 reg_val = riscv_cboz_block_size; 211 reg_val = vcpu->arch.mvendorid; 214 reg_val = vcpu->arch.marchid; 217 reg_val = vcpu->arch.mimpid; 220 reg_val = satp_mode >> SATP_MODE_SHIFT; 226 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 240 unsigned long i, isa_ext, reg_val; local 345 unsigned long reg_val; local 378 unsigned long reg_val; local 423 kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument 445 kvm_riscv_vcpu_smstateen_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument 482 unsigned long reg_val, reg_subtype; local 524 unsigned long reg_val, reg_subtype; local 557 riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument 578 riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument 616 riscv_vcpu_get_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument 639 riscv_vcpu_set_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val, bool enable) argument 668 unsigned long reg_val, reg_subtype; local 707 unsigned long reg_val, reg_subtype; local [all...] |
H A D | vcpu_sbi.c | 173 unsigned long reg_val) 178 if (reg_val != 1 && reg_val != 0) 185 scontext->ext_status[sext->ext_idx] = (reg_val) ? 194 unsigned long *reg_val) 203 *reg_val = scontext->ext_status[sext->ext_idx] == 211 unsigned long reg_val, bool enable) 218 for_each_set_bit(i, ®_val, BITS_PER_LONG) { 231 unsigned long *reg_val) 246 *reg_val | 171 riscv_vcpu_set_sbi_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument 192 riscv_vcpu_get_sbi_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument 209 riscv_vcpu_set_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val, bool enable) argument 229 riscv_vcpu_get_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument 260 unsigned long reg_val, reg_subtype; local 297 unsigned long reg_val, reg_subtype; local 336 unsigned long reg_subtype, reg_val; local 365 unsigned long reg_subtype, reg_val; local [all...] |
H A D | vcpu_sbi_sta.c | 163 unsigned long *reg_val) 167 *reg_val = (unsigned long)vcpu->arch.sta.shmem; 171 *reg_val = upper_32_bits(vcpu->arch.sta.shmem); 173 *reg_val = 0; 184 unsigned long reg_val) 191 vcpu->arch.sta.shmem = reg_val; 194 vcpu->arch.sta.shmem = reg_val; 201 vcpu->arch.sta.shmem = ((gpa_t)reg_val << 32); 203 } else if (reg_val != 0) { 161 kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument 182 kvm_riscv_vcpu_set_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
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H A D | vcpu_timer.c | 168 u64 reg_val; local 177 reg_val = riscv_timebase; 180 reg_val = kvm_riscv_current_cycles(gt); 183 reg_val = t->next_cycles; 186 reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON : 193 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 208 u64 reg_val; local 216 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 221 if (reg_val != riscv_timebase) 225 gt->time_delta = reg_val [all...] |
H A D | vcpu_vector.c | 182 unsigned long reg_val; local 184 if (copy_from_user(®_val, uaddr, reg_size)) 186 if (reg_val != cntx->vector.vlenb)
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/linux-master/arch/sparc/include/asm/ |
H A D | hypervisor.h | 3446 unsigned long *reg_val); 3448 unsigned long reg_val); 3456 unsigned long *reg_val); 3458 unsigned long reg_val); 3467 unsigned long *reg_val); 3469 unsigned long reg_val);
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