1/* 2 * arch/arm/plat-orion/gpio.c 3 * 4 * Marvell Orion SoC GPIO handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11#define DEBUG 12 13#include <linux/kernel.h> 14#include <linux/init.h> 15#include <linux/irq.h> 16#include <linux/irqdomain.h> 17#include <linux/module.h> 18#include <linux/spinlock.h> 19#include <linux/bitops.h> 20#include <linux/io.h> 21#include <linux/gpio/driver.h> 22#include <linux/gpio/consumer.h> 23#include <linux/leds.h> 24#include <linux/of.h> 25#include <linux/of_irq.h> 26#include <linux/of_address.h> 27#include <plat/orion-gpio.h> 28 29/* 30 * GPIO unit register offsets. 31 */ 32#define GPIO_OUT_OFF 0x0000 33#define GPIO_IO_CONF_OFF 0x0004 34#define GPIO_BLINK_EN_OFF 0x0008 35#define GPIO_IN_POL_OFF 0x000c 36#define GPIO_DATA_IN_OFF 0x0010 37#define GPIO_EDGE_CAUSE_OFF 0x0014 38#define GPIO_EDGE_MASK_OFF 0x0018 39#define GPIO_LEVEL_MASK_OFF 0x001c 40 41struct orion_gpio_chip { 42 struct gpio_chip chip; 43 spinlock_t lock; 44 void __iomem *base; 45 unsigned long valid_input; 46 unsigned long valid_output; 47 int mask_offset; 48 int secondary_irq_base; 49 struct irq_domain *domain; 50}; 51 52static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip) 53{ 54 return ochip->base + GPIO_OUT_OFF; 55} 56 57static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip) 58{ 59 return ochip->base + GPIO_IO_CONF_OFF; 60} 61 62static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip) 63{ 64 return ochip->base + GPIO_BLINK_EN_OFF; 65} 66 67static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip) 68{ 69 return ochip->base + GPIO_IN_POL_OFF; 70} 71 72static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip) 73{ 74 return ochip->base + GPIO_DATA_IN_OFF; 75} 76 77static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip) 78{ 79 return ochip->base + GPIO_EDGE_CAUSE_OFF; 80} 81 82static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip) 83{ 84 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; 85} 86 87static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip) 88{ 89 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; 90} 91 92 93static struct orion_gpio_chip orion_gpio_chips[2]; 94static int orion_gpio_chip_count; 95 96static inline void 97__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) 98{ 99 u32 u; 100 101 u = readl(GPIO_IO_CONF(ochip)); 102 if (input) 103 u |= 1 << pin; 104 else 105 u &= ~(1 << pin); 106 writel(u, GPIO_IO_CONF(ochip)); 107} 108 109static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) 110{ 111 u32 u; 112 113 u = readl(GPIO_OUT(ochip)); 114 if (high) 115 u |= 1 << pin; 116 else 117 u &= ~(1 << pin); 118 writel(u, GPIO_OUT(ochip)); 119} 120 121static inline void 122__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) 123{ 124 u32 u; 125 126 u = readl(GPIO_BLINK_EN(ochip)); 127 if (blink) 128 u |= 1 << pin; 129 else 130 u &= ~(1 << pin); 131 writel(u, GPIO_BLINK_EN(ochip)); 132} 133 134static inline int 135orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) 136{ 137 if (pin >= ochip->chip.ngpio) 138 goto err_out; 139 140 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input)) 141 goto err_out; 142 143 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output)) 144 goto err_out; 145 146 return 1; 147 148err_out: 149 pr_debug("%s: invalid GPIO %d\n", __func__, pin); 150 return false; 151} 152 153/* 154 * GPIO primitives. 155 */ 156static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) 157{ 158 struct orion_gpio_chip *ochip = gpiochip_get_data(chip); 159 160 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) || 161 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) 162 return 0; 163 164 return -EINVAL; 165} 166 167static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 168{ 169 struct orion_gpio_chip *ochip = gpiochip_get_data(chip); 170 unsigned long flags; 171 172 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK)) 173 return -EINVAL; 174 175 spin_lock_irqsave(&ochip->lock, flags); 176 __set_direction(ochip, pin, 1); 177 spin_unlock_irqrestore(&ochip->lock, flags); 178 179 return 0; 180} 181 182static int orion_gpio_get(struct gpio_chip *chip, unsigned pin) 183{ 184 struct orion_gpio_chip *ochip = gpiochip_get_data(chip); 185 int val; 186 187 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { 188 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); 189 } else { 190 val = readl(GPIO_OUT(ochip)); 191 } 192 193 return (val >> pin) & 1; 194} 195 196static int 197orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) 198{ 199 struct orion_gpio_chip *ochip = gpiochip_get_data(chip); 200 unsigned long flags; 201 202 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) 203 return -EINVAL; 204 205 spin_lock_irqsave(&ochip->lock, flags); 206 __set_blinking(ochip, pin, 0); 207 __set_level(ochip, pin, value); 208 __set_direction(ochip, pin, 0); 209 spin_unlock_irqrestore(&ochip->lock, flags); 210 211 return 0; 212} 213 214static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 215{ 216 struct orion_gpio_chip *ochip = gpiochip_get_data(chip); 217 unsigned long flags; 218 219 spin_lock_irqsave(&ochip->lock, flags); 220 __set_level(ochip, pin, value); 221 spin_unlock_irqrestore(&ochip->lock, flags); 222} 223 224static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 225{ 226 struct orion_gpio_chip *ochip = gpiochip_get_data(chip); 227 228 return irq_create_mapping(ochip->domain, 229 ochip->secondary_irq_base + pin); 230} 231 232/* 233 * Orion-specific GPIO API extensions. 234 */ 235static struct orion_gpio_chip *orion_gpio_chip_find(int pin) 236{ 237 int i; 238 239 for (i = 0; i < orion_gpio_chip_count; i++) { 240 struct orion_gpio_chip *ochip = orion_gpio_chips + i; 241 struct gpio_chip *chip = &ochip->chip; 242 243 if (pin >= chip->base && pin < chip->base + chip->ngpio) 244 return ochip; 245 } 246 247 return NULL; 248} 249 250void __init orion_gpio_set_unused(unsigned pin) 251{ 252 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 253 254 if (ochip == NULL) 255 return; 256 257 pin -= ochip->chip.base; 258 259 /* Configure as output, drive low. */ 260 __set_level(ochip, pin, 0); 261 __set_direction(ochip, pin, 0); 262} 263 264void __init orion_gpio_set_valid(unsigned pin, int mode) 265{ 266 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 267 268 if (ochip == NULL) 269 return; 270 271 pin -= ochip->chip.base; 272 273 if (mode == 1) 274 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; 275 276 if (mode & GPIO_INPUT_OK) 277 __set_bit(pin, &ochip->valid_input); 278 else 279 __clear_bit(pin, &ochip->valid_input); 280 281 if (mode & GPIO_OUTPUT_OK) 282 __set_bit(pin, &ochip->valid_output); 283 else 284 __clear_bit(pin, &ochip->valid_output); 285} 286 287void orion_gpio_set_blink(unsigned pin, int blink) 288{ 289 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 290 unsigned long flags; 291 292 if (ochip == NULL) 293 return; 294 295 spin_lock_irqsave(&ochip->lock, flags); 296 __set_level(ochip, pin & 31, 0); 297 __set_blinking(ochip, pin & 31, blink); 298 spin_unlock_irqrestore(&ochip->lock, flags); 299} 300EXPORT_SYMBOL(orion_gpio_set_blink); 301 302#define ORION_BLINK_HALF_PERIOD 100 /* ms */ 303 304int orion_gpio_led_blink_set(struct gpio_desc *desc, int state, 305 unsigned long *delay_on, unsigned long *delay_off) 306{ 307 unsigned gpio = desc_to_gpio(desc); 308 309 if (delay_on && delay_off && !*delay_on && !*delay_off) 310 *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; 311 312 switch (state) { 313 case GPIO_LED_NO_BLINK_LOW: 314 case GPIO_LED_NO_BLINK_HIGH: 315 orion_gpio_set_blink(gpio, 0); 316 gpiod_set_raw_value(desc, state); 317 break; 318 case GPIO_LED_BLINK: 319 orion_gpio_set_blink(gpio, 1); 320 } 321 return 0; 322} 323EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set); 324 325 326/***************************************************************************** 327 * Orion GPIO IRQ 328 * 329 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 330 * value of the line or the opposite value. 331 * 332 * Level IRQ handlers: DATA_IN is used directly as cause register. 333 * Interrupt are masked by LEVEL_MASK registers. 334 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 335 * Interrupt are masked by EDGE_MASK registers. 336 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 337 * the polarity to catch the next line transaction. 338 * This is a race condition that might not perfectly 339 * work on some use cases. 340 * 341 * Every eight GPIO lines are grouped (OR'ed) before going up to main 342 * cause register. 343 * 344 * EDGE cause mask 345 * data-in /--------| |-----| |----\ 346 * -----| |----- ---- to main cause reg 347 * X \----------------| |----/ 348 * polarity LEVEL mask 349 * 350 ****************************************************************************/ 351 352static int gpio_irq_set_type(struct irq_data *d, u32 type) 353{ 354 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 355 struct irq_chip_type *ct = irq_data_get_chip_type(d); 356 struct orion_gpio_chip *ochip = gc->private; 357 int pin; 358 u32 u; 359 360 pin = d->hwirq - ochip->secondary_irq_base; 361 362 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); 363 if (!u) { 364 return -EINVAL; 365 } 366 367 type &= IRQ_TYPE_SENSE_MASK; 368 if (type == IRQ_TYPE_NONE) 369 return -EINVAL; 370 371 /* Check if we need to change chip and handler */ 372 if (!(ct->type & type)) 373 if (irq_setup_alt_chip(d, type)) 374 return -EINVAL; 375 376 /* 377 * Configure interrupt polarity. 378 */ 379 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { 380 u = readl(GPIO_IN_POL(ochip)); 381 u &= ~(1 << pin); 382 writel(u, GPIO_IN_POL(ochip)); 383 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { 384 u = readl(GPIO_IN_POL(ochip)); 385 u |= 1 << pin; 386 writel(u, GPIO_IN_POL(ochip)); 387 } else if (type == IRQ_TYPE_EDGE_BOTH) { 388 u32 v; 389 390 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); 391 392 /* 393 * set initial polarity based on current input level 394 */ 395 u = readl(GPIO_IN_POL(ochip)); 396 if (v & (1 << pin)) 397 u |= 1 << pin; /* falling */ 398 else 399 u &= ~(1 << pin); /* rising */ 400 writel(u, GPIO_IN_POL(ochip)); 401 } 402 return 0; 403} 404 405static void gpio_irq_handler(struct irq_desc *desc) 406{ 407 struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc); 408 u32 cause, type; 409 int i; 410 411 if (ochip == NULL) 412 return; 413 414 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); 415 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); 416 417 for (i = 0; i < ochip->chip.ngpio; i++) { 418 int irq; 419 420 irq = ochip->secondary_irq_base + i; 421 422 if (!(cause & (1 << i))) 423 continue; 424 425 type = irq_get_trigger_type(irq); 426 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 427 /* Swap polarity (race with GPIO line) */ 428 u32 polarity; 429 430 polarity = readl(GPIO_IN_POL(ochip)); 431 polarity ^= 1 << i; 432 writel(polarity, GPIO_IN_POL(ochip)); 433 } 434 generic_handle_irq(irq); 435 } 436} 437 438#ifdef CONFIG_DEBUG_FS 439#include <linux/seq_file.h> 440 441static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 442{ 443 444 struct orion_gpio_chip *ochip = gpiochip_get_data(chip); 445 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 446 const char *label; 447 int i; 448 449 out = readl_relaxed(GPIO_OUT(ochip)); 450 io_conf = readl_relaxed(GPIO_IO_CONF(ochip)); 451 blink = readl_relaxed(GPIO_BLINK_EN(ochip)); 452 in_pol = readl_relaxed(GPIO_IN_POL(ochip)); 453 data_in = readl_relaxed(GPIO_DATA_IN(ochip)); 454 cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip)); 455 edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); 456 lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); 457 458 for_each_requested_gpio(chip, i, label) { 459 u32 msk; 460 bool is_out; 461 462 msk = 1 << i; 463 is_out = !(io_conf & msk); 464 465 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 466 467 if (is_out) { 468 seq_printf(s, " out %s %s\n", 469 out & msk ? "hi" : "lo", 470 blink & msk ? "(blink )" : ""); 471 continue; 472 } 473 474 seq_printf(s, " in %s (act %s) - IRQ", 475 (data_in ^ in_pol) & msk ? "hi" : "lo", 476 in_pol & msk ? "lo" : "hi"); 477 if (!((edg_msk | lvl_msk) & msk)) { 478 seq_puts(s, " disabled\n"); 479 continue; 480 } 481 if (edg_msk & msk) 482 seq_puts(s, " edge "); 483 if (lvl_msk & msk) 484 seq_puts(s, " level"); 485 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 486 } 487} 488#else 489#define orion_gpio_dbg_show NULL 490#endif 491 492static void orion_gpio_unmask_irq(struct irq_data *d) 493{ 494 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 495 struct irq_chip_type *ct = irq_data_get_chip_type(d); 496 u32 reg_val; 497 u32 mask = d->mask; 498 499 irq_gc_lock(gc); 500 reg_val = irq_reg_readl(gc, ct->regs.mask); 501 reg_val |= mask; 502 irq_reg_writel(gc, reg_val, ct->regs.mask); 503 irq_gc_unlock(gc); 504} 505 506static void orion_gpio_mask_irq(struct irq_data *d) 507{ 508 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 509 struct irq_chip_type *ct = irq_data_get_chip_type(d); 510 u32 mask = d->mask; 511 u32 reg_val; 512 513 irq_gc_lock(gc); 514 reg_val = irq_reg_readl(gc, ct->regs.mask); 515 reg_val &= ~mask; 516 irq_reg_writel(gc, reg_val, ct->regs.mask); 517 irq_gc_unlock(gc); 518} 519 520void __init orion_gpio_init(int gpio_base, int ngpio, 521 void __iomem *base, int mask_offset, 522 int secondary_irq_base, 523 int irqs[4]) 524{ 525 struct orion_gpio_chip *ochip; 526 struct irq_chip_generic *gc; 527 struct irq_chip_type *ct; 528 char gc_label[16]; 529 int i; 530 531 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) 532 return; 533 534 snprintf(gc_label, sizeof(gc_label), "orion_gpio%d", 535 orion_gpio_chip_count); 536 537 ochip = orion_gpio_chips + orion_gpio_chip_count; 538 ochip->chip.label = kstrdup(gc_label, GFP_KERNEL); 539 ochip->chip.request = orion_gpio_request; 540 ochip->chip.direction_input = orion_gpio_direction_input; 541 ochip->chip.get = orion_gpio_get; 542 ochip->chip.direction_output = orion_gpio_direction_output; 543 ochip->chip.set = orion_gpio_set; 544 ochip->chip.to_irq = orion_gpio_to_irq; 545 ochip->chip.base = gpio_base; 546 ochip->chip.ngpio = ngpio; 547 ochip->chip.can_sleep = 0; 548 ochip->chip.dbg_show = orion_gpio_dbg_show; 549 550 spin_lock_init(&ochip->lock); 551 ochip->base = (void __iomem *)base; 552 ochip->valid_input = 0; 553 ochip->valid_output = 0; 554 ochip->mask_offset = mask_offset; 555 ochip->secondary_irq_base = secondary_irq_base; 556 557 gpiochip_add_data(&ochip->chip, ochip); 558 559 /* 560 * Mask and clear GPIO interrupts. 561 */ 562 writel(0, GPIO_EDGE_CAUSE(ochip)); 563 writel(0, GPIO_EDGE_MASK(ochip)); 564 writel(0, GPIO_LEVEL_MASK(ochip)); 565 566 /* Setup the interrupt handlers. Each chip can have up to 4 567 * interrupt handlers, with each handler dealing with 8 GPIO 568 * pins. */ 569 570 for (i = 0; i < 4; i++) { 571 if (irqs[i]) { 572 irq_set_chained_handler_and_data(irqs[i], 573 gpio_irq_handler, 574 ochip); 575 } 576 } 577 578 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, 579 secondary_irq_base, 580 ochip->base, handle_level_irq); 581 gc->private = ochip; 582 ct = gc->chip_types; 583 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; 584 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 585 ct->chip.irq_mask = orion_gpio_mask_irq; 586 ct->chip.irq_unmask = orion_gpio_unmask_irq; 587 ct->chip.irq_set_type = gpio_irq_set_type; 588 ct->chip.name = ochip->chip.label; 589 590 ct++; 591 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; 592 ct->regs.ack = GPIO_EDGE_CAUSE_OFF; 593 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 594 ct->chip.irq_ack = irq_gc_ack_clr_bit; 595 ct->chip.irq_mask = orion_gpio_mask_irq; 596 ct->chip.irq_unmask = orion_gpio_unmask_irq; 597 ct->chip.irq_set_type = gpio_irq_set_type; 598 ct->handler = handle_edge_irq; 599 ct->chip.name = ochip->chip.label; 600 601 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, 602 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 603 604 /* Setup irq domain on top of the generic chip. */ 605 ochip->domain = irq_domain_add_legacy(NULL, 606 ochip->chip.ngpio, 607 ochip->secondary_irq_base, 608 ochip->secondary_irq_base, 609 &irq_domain_simple_ops, 610 ochip); 611 if (!ochip->domain) 612 panic("%s: couldn't allocate irq domain (DT).\n", 613 ochip->chip.label); 614 615 orion_gpio_chip_count++; 616} 617