Searched refs:reg (Results 1 - 25 of 313) sorted by last modified time

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/haiku/src/add-ons/kernel/drivers/audio/emuxki/
H A Dmulti.c57 value = emuxki_codec_read(&dev->config, info->reg);
84 value = emuxki_codec_read(&dev->config, info->reg);
91 value = emuxki_codec_read(&dev->config, info->reg);
115 value = emuxki_codec_read(&dev->config, info->reg);
143 emuxki_codec_write(&dev->config, info->reg, value);
147 value = emuxki_codec_read(&dev->config, info->reg);
150 if (info->reg == AC97_SURROUND_VOLUME) {
157 emuxki_codec_write(&dev->config, info->reg, value);
161 value = emuxki_codec_read(&dev->config, info->reg);
165 emuxki_codec_write(&dev->config, info->reg, valu
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/haiku/src/add-ons/kernel/drivers/audio/ac97/geode/
H A Dgeode_multi.cpp195 value = ac97_reg_cached_read(controller->ac97, info->reg);
222 value = ac97_reg_cached_read(controller->ac97, info->reg);
229 value = ac97_reg_cached_read(controller->ac97, info->reg);
253 value = ac97_reg_cached_read(controller->ac97, info->reg);
281 ac97_reg_cached_write(controller->ac97, info->reg, value);
285 value = ac97_reg_cached_read(controller->ac97, info->reg);
288 if (info->reg == AC97_SURR_VOLUME) {
295 ac97_reg_cached_write(controller->ac97, info->reg, value);
299 value = ac97_reg_cached_read(controller->ac97, info->reg);
303 ac97_reg_cached_write(controller->ac97, info->reg, valu
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H A Ddriver.h68 uint8 Read8(uint32 reg) argument
70 return gPci->read_io_8(nabmbar + reg);
73 uint16 Read16(uint32 reg) argument
75 return gPci->read_io_16(nabmbar + reg);
78 uint32 Read32(uint32 reg) argument
80 return gPci->read_io_32(nabmbar + reg);
83 void Write8(uint32 reg, uint8 value) argument
85 gPci->write_io_8(nabmbar + reg, value);
88 void Write16(uint32 reg, uint16 value) argument
90 gPci->write_io_16(nabmbar + reg, valu
93 Write32(uint32 reg, uint32 value) argument
135 Read8(uint32 reg) argument
140 Read16(uint32 reg) argument
145 Read32(uint32 reg) argument
150 Write8(uint32 reg, uint8 value) argument
155 Write16(uint32 reg, uint16 value) argument
160 Write32(uint32 reg, uint32 value) argument
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/haiku/src/add-ons/kernel/drivers/audio/ac97/es1370/
H A Dmulti.c39 value = es1370_codec_read(&dev->config, info->reg);
66 value = es1370_codec_read(&dev->config, info->reg);
73 value = es1370_codec_read(&dev->config, info->reg);
97 value = es1370_codec_read(&dev->config, info->reg);
125 es1370_codec_write(&dev->config, info->reg, value);
129 value = es1370_codec_read(&dev->config, info->reg);
132 if (info->reg == AC97_SURR_VOLUME) {
139 es1370_codec_write(&dev->config, info->reg, value);
143 value = es1370_codec_read(&dev->config, info->reg);
147 es1370_codec_write(&dev->config, info->reg, valu
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H A Des1370.c193 uint32 reg = 0, cnt = 0; local
195 reg = ES1370_REG_ADC_FRAMECNT;
197 reg = ES1370_REG_DAC2_FRAMECNT;
199 es1370_reg_write_32(&card->config, ES1370_REG_MEMPAGE, reg >> 8);
200 cnt = es1370_reg_read_32(&card->config, reg & 0xff) >> 16;
/haiku/src/add-ons/kernel/drivers/audio/ac97/auvia/
H A Dmulti.c56 value = auvia_codec_read(&dev->config, info->reg);
83 value = auvia_codec_read(&dev->config, info->reg);
90 value = auvia_codec_read(&dev->config, info->reg);
114 value = auvia_codec_read(&dev->config, info->reg);
142 auvia_codec_write(&dev->config, info->reg, value);
146 value = auvia_codec_read(&dev->config, info->reg);
149 if (info->reg == AC97_SURR_VOLUME) {
156 auvia_codec_write(&dev->config, info->reg, value);
160 value = auvia_codec_read(&dev->config, info->reg);
164 auvia_codec_write(&dev->config, info->reg, valu
[all...]
/haiku/src/add-ons/kernel/drivers/audio/ac97/auich/
H A Dmulti.c61 value = auich_codec_read(&dev->config, info->reg);
88 value = auich_codec_read(&dev->config, info->reg);
95 value = auich_codec_read(&dev->config, info->reg);
120 value = auich_codec_read(&dev->config, info->reg);
148 auich_codec_write(&dev->config, info->reg, value);
152 value = auich_codec_read(&dev->config, info->reg);
155 if (info->reg == AC97_SURR_VOLUME) {
162 auich_codec_write(&dev->config, info->reg, value);
166 value = auich_codec_read(&dev->config, info->reg);
170 auich_codec_write(&dev->config, info->reg, valu
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/haiku/src/system/kernel/platform/atari_m68k/
H A Dplatform.cpp106 uint8 ReadReg(uint32 reg) { return in8(fBase + reg); }; argument
107 void WriteReg(uint32 reg, uint8 v) { out8(v, fBase + reg); }; argument
126 uint8 ReadReg(uint32 reg);
127 void WriteReg(uint32 reg, uint8 v) { out8((uint8)reg,fBase+1); out8(v,fBase+3); }; argument
156 virtual uint8 ReadRTCReg(uint8 reg);
157 virtual void WriteRTCReg(uint8 reg, uint8 val);
213 uint32 reg local
227 uint32 reg = Base() + ((irq > 8) ? (MFP_IERA) : (MFP_IERB)); local
241 uint32 reg = Base() + ((irq > 8) ? (MFP_ISRA) : (MFP_ISRB)); local
271 ReadReg(uint32 reg) argument
602 ReadRTCReg(uint8 reg) argument
614 WriteRTCReg(uint8 reg, uint8 val) argument
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/haiku/src/add-ons/kernel/drivers/network/wlan/idualwifi7260/dev/pci/
H A Dif_iwm.c1140 iwm_poll_bit(struct iwm_softc *sc, int reg, uint32_t bits, uint32_t mask, argument
1144 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
1201 iwm_set_bits_mask_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits, argument
1207 val = iwm_read_prph(sc, reg) & mask;
1209 iwm_write_prph(sc, reg, val);
1217 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) argument
1219 return iwm_set_bits_mask_prph(sc, reg, bits, ~0);
1223 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) argument
1225 return iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
10812 printf("%s: 0x%08X | isr status reg\
11739 pcireg_t reg, memtype; local
12211 pcireg_t reg; local
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/haiku/src/add-ons/kernel/drivers/network/wlan/iaxwifi200/dev/pci/
H A Dif_iwx.c1748 iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask, argument
1752 if ((IWX_READ(sc, reg) & mask) == (bits & mask)) {
1808 iwx_set_bits_mask_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits, argument
1814 val = iwx_read_prph(sc, reg) & mask;
1816 iwx_write_prph(sc, reg, val);
1824 iwx_set_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits) argument
1826 return iwx_set_bits_mask_prph(sc, reg, bits, ~0);
1830 iwx_clear_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits) argument
1832 return iwx_set_bits_mask_prph(sc, reg, 0, ~bits);
9564 printf("%s: 0x%08X | isr status reg\
11012 pcireg_t reg, memtype; local
11498 pcireg_t reg; local
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H A Dif_iwxreg.h2499 * @write_ptr_reg: the addr of the reg of the write pointer
2500 * @wrap_count: the addr of the reg of the wrap_count
2501 * @base_shift: shift right of the base addr reg
2502 * @end_shift: shift right of the end addr reg
4527 * reg change
7888 #define IWX_READ(sc, reg) \
7889 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
7891 #define IWX_WRITE(sc, reg, val) \
7892 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
7894 #define IWX_WRITE_1(sc, reg, va
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/haiku/src/add-ons/kernel/drivers/audio/hda/
H A Dhda_controller.cpp190 wait_for_bits(base_type base, uint32 reg, uint32 mask, bool set, argument
201 value = base->Read8(reg);
204 value = base->Read16(reg);
207 value = base->Read32(reg);
220 update_pci_register(hda_controller* controller, uint8 reg, uint32 mask, argument
224 controller->pci_info.device, controller->pci_info.function, reg, size);
227 reg, size, (originalValue & mask) | value);
233 controller->pci_info.device, controller->pci_info.function, reg, size);
/haiku/src/add-ons/kernel/busses/virtio/virtio_pci/
H A Dvirtio_pci.cpp85 uint32 reg[8]; member in union:regs
91 v->reg[i] = bus->pci->read_pci_config(bus->device, capabilityOffset + i * 4, 4);
103 v->reg[i] = bus->pci->read_pci_config(bus->device, capabilityOffset + i * 4, 4);
/haiku/src/add-ons/kernel/busses/usb/
H A Dxhci.h201 inline void WriteOpReg(uint32 reg, uint32 value);
202 inline uint32 ReadOpReg(uint32 reg);
203 inline status_t WaitOpBits(uint32 reg, uint32 mask, uint32 expected);
206 inline uint32 ReadCapReg32(uint32 reg);
207 inline void WriteCapReg32(uint32 reg, uint32 value);
210 inline uint32 ReadRunReg32(uint32 reg);
211 inline void WriteRunReg32(uint32 reg, uint32 value);
214 inline uint32 ReadDoorReg32(uint32 reg);
215 inline void WriteDoorReg32(uint32 reg, uint32 value);
H A Dxhci.cpp3195 XHCI::WriteOpReg(uint32 reg, uint32 value) argument
3197 *(volatile uint32 *)(fRegisters + fOperationalRegisterOffset + reg) = value;
3202 XHCI::ReadOpReg(uint32 reg) argument
3204 return *(volatile uint32 *)(fRegisters + fOperationalRegisterOffset + reg);
3209 XHCI::WaitOpBits(uint32 reg, uint32 mask, uint32 expected) argument
3212 uint32 value = ReadOpReg(reg);
3215 value = ReadOpReg(reg);
3217 TRACE("delay waiting on reg 0x%" B_PRIX32 " match 0x%" B_PRIX32
3218 " (0x%" B_PRIX32 ")\n", reg, expected, mask);
3220 TRACE_ERROR("timeout waiting on reg
3232 ReadCapReg32(uint32 reg) argument
3239 WriteCapReg32(uint32 reg, uint32 value) argument
3246 ReadRunReg32(uint32 reg) argument
3253 WriteRunReg32(uint32 reg, uint32 value) argument
3260 ReadDoorReg32(uint32 reg) argument
3267 WriteDoorReg32(uint32 reg, uint32 value) argument
[all...]
H A Duhci.h202 inline void WriteReg8(uint32 reg, uint8 value);
203 inline void WriteReg16(uint32 reg, uint16 value);
204 inline void WriteReg32(uint32 reg, uint32 value);
205 inline uint8 ReadReg8(uint32 reg);
206 inline uint16 ReadReg16(uint32 reg);
207 inline uint32 ReadReg32(uint32 reg);
H A Duhci.cpp778 TRACE("usbcmd reg 0x%04x, usbsts reg 0x%04x\n",
2483 UHCI::WriteReg8(uint32 reg, uint8 value) argument
2485 fPci->write_io_8(fDevice, fRegisterBase + reg, value);
2490 UHCI::WriteReg16(uint32 reg, uint16 value) argument
2492 fPci->write_io_16(fDevice, fRegisterBase + reg, value);
2497 UHCI::WriteReg32(uint32 reg, uint32 value) argument
2499 fPci->write_io_32(fDevice, fRegisterBase + reg, value);
2504 UHCI::ReadReg8(uint32 reg) argument
2506 return fPci->read_io_8(fDevice, fRegisterBase + reg);
2511 ReadReg16(uint32 reg) argument
2518 ReadReg32(uint32 reg) argument
[all...]
H A Dohci.cpp2634 OHCI::_WriteReg(uint32 reg, uint32 value) argument
2636 *(volatile uint32 *)(fOperationalRegisters + reg) = value;
2641 OHCI::_ReadReg(uint32 reg) argument
2643 return *(volatile uint32 *)(fOperationalRegisters + reg);
H A Dohci.h176 inline void _WriteReg(uint32 reg, uint32 value);
177 inline uint32 _ReadReg(uint32 reg);
H A Dehci.h194 inline void WriteOpReg(uint32 reg, uint32 value);
195 inline uint32 ReadOpReg(uint32 reg);
198 inline uint8 ReadCapReg8(uint32 reg);
199 inline uint16 ReadCapReg16(uint32 reg);
200 inline uint32 ReadCapReg32(uint32 reg);
H A Dehci.cpp3049 EHCI::WriteOpReg(uint32 reg, uint32 value) argument
3051 *(volatile uint32 *)(fOperationalRegisters + reg) = value;
3056 EHCI::ReadOpReg(uint32 reg) argument
3058 return *(volatile uint32 *)(fOperationalRegisters + reg);
3063 EHCI::ReadCapReg8(uint32 reg) argument
3065 return *(volatile uint8 *)(fCapabilityRegisters + reg);
3070 EHCI::ReadCapReg16(uint32 reg) argument
3072 return *(volatile uint16 *)(fCapabilityRegisters + reg);
3077 EHCI::ReadCapReg32(uint32 reg) argument
3079 return *(volatile uint32 *)(fCapabilityRegisters + reg);
[all...]
/haiku/src/add-ons/kernel/busses/i2c/pch/
H A Dpch_i2c.cpp453 uint32 reg = read32(bus->registers + PCH_IC_COMP_VERSION); local
454 if (reg >= PCH_IC_COMP_VERSION_MIN)
461 uint32 reg = read32(bus->registers + PCH_IC_COMP_PARAM1); local
462 uint8 rx_fifo_depth = PCH_IC_COMP_PARAM1_RX(reg);
463 uint8 tx_fifo_depth = PCH_IC_COMP_PARAM1_TX(reg);
/haiku/src/add-ons/accelerants/radeon_hd/
H A Dbios.cpp68 uint32 reg; local
72 reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
76 if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
80 reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
92 if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
96 reg = Read32(OUT, AVIVO_D1CRTC_CONTROL)
98 if ((reg & AVIVO_CRTC_EN) != 0) {
103 reg = Read32(OUT, RADEON_CRTC_GEN_CNTL)
105 if ((reg & RADEON_CRTC_EN) != 0)
111 reg
[all...]
/haiku/src/add-ons/kernel/bus_managers/acpi/
H A DACPICAHaiku.cpp889 * reg Device Register
899 AcpiOsReadPciConfiguration(ACPI_PCI_ID *pciId, UINT32 reg, UINT64 *value, argument
910 pciId->Bus, pciId->Device, pciId->Function, reg, width / 8);
927 * reg Device Register
937 AcpiOsWritePciConfiguration(ACPI_PCI_ID *pciId, UINT32 reg, argument
943 pciId->Bus, pciId->Device, pciId->Function, reg, width / 8, value);
/haiku/src/kits/debugger/dwarf/
H A DDwarfFile.cpp2426 TRACE_CFI(" reg %" B_PRIu32 "\n", i);
2579 B_PRId32 ", return address reg: %" B_PRIu32 "\n", length,
2630 TRACE_CFI(" DW_CFA_offset: reg: %" B_PRIu32 ", offset: "
2712 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2715 TRACE_CFI(" DW_CFA_offset_extended: reg: %" B_PRIu32 ", "
2716 "offset: %" B_PRIu64 "\n", reg, offset);
2718 if (CfaRule* rule = context.RegisterRule(reg)) {
2726 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2729 reg);
2731 context.RestoreRegisterRule(reg);
2736 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2746 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2786 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2797 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2838 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2852 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2866 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2893 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2907 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2921 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
2971 uint32 reg = dataReader.ReadUnsignedLEB128(0); local
[all...]

Completed in 312 milliseconds

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