Searched refs:mul_u32_u32 (Results 1 - 25 of 48) sorted by path

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/linux-master/arch/x86/include/asm/
H A Ddiv64.h63 static inline u64 mul_u32_u32(u32 a, u32 b) function
72 #define mul_u32_u32 mul_u32_u32 macro
/linux-master/drivers/acpi/
H A Dacpi_lpit.c108 lpit_native->counter_frequency : mul_u32_u32(tsc_khz, 1000U);
/linux-master/drivers/cpuidle/
H A Ddriver.c191 s->exit_latency_ns = mul_u32_u32(s->exit_latency, NSEC_PER_USEC);
/linux-master/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c4202 return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
4261 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
H A Ddrm_dp_mst_topology.c3602 ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
4771 return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
/linux-master/drivers/gpu/drm/
H A Ddrm_modes.c1303 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);
H A Ddrm_rect.c65 tmp = mul_u32_u32(src, dst - *clip);
/linux-master/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c468 ret = mul_u32_u32(pixel_rate, cpp * latency);
H A Dintel_atomic_plane.c162 return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
H A Dintel_audio.c455 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
456 mul_u32_u32(link_clk, cdclk));
458 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
459 mul_u32_u32(link_clk * lanes * 16, fec_coeff));
460 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
461 mul_u32_u32(64 * pixel_clk, 1000000));
H A Dintel_backlight.c50 target_val = mul_u32_u32(source_val - source_min,
H A Dintel_bw.c745 return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
H A Dintel_color.c200 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
789 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(val, (1 << 16) - 1),
H A Dintel_cx0_phy.c2153 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
2454 tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
H A Dintel_display.c2542 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
3911 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
H A Dintel_dp.c412 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
728 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
H A Dintel_dp_mst.c84 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,
86 mul_u32_u32(adjusted_mode->crtc_clock, 1030000));
140 m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
417 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
H A Dintel_dpll.c366 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
946 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
H A Dintel_dpll_mgr.c3086 tmp = mul_u32_u32(dco_khz, 47 * 32);
3090 tmp = mul_u32_u32(dco_khz, 1000);
H A Dintel_fb.c1131 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]),
1680 if (mul_u32_u32(max_size, tile_size) > intel_bo_to_drm_bo(obj)->size) {
1683 mul_u32_u32(max_size, tile_size), intel_bo_to_drm_bo(obj)->size);
H A Dintel_fixed.h79 tmp = mul_u32_u32(val, mul.val);
91 tmp = mul_u32_u32(val.val, mul.val);
122 tmp = mul_u32_u32(val, mul.val);
H A Dintel_snps_phy.c1947 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
H A Dintel_sprite.c582 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w),
937 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale),
H A Dintel_vblank.c167 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
/linux-master/drivers/gpu/drm/i915/gem/
H A Di915_gem_create.c203 args->size = mul_u32_u32(args->pitch, args->height);

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