/linux-master/arch/x86/include/asm/ |
H A D | div64.h | 63 static inline u64 mul_u32_u32(u32 a, u32 b) function 72 #define mul_u32_u32 mul_u32_u32 macro
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/linux-master/drivers/acpi/ |
H A D | acpi_lpit.c | 108 lpit_native->counter_frequency : mul_u32_u32(tsc_khz, 1000U);
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/linux-master/drivers/cpuidle/ |
H A D | driver.c | 191 s->exit_latency_ns = mul_u32_u32(s->exit_latency, NSEC_PER_USEC);
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/linux-master/drivers/gpu/drm/display/ |
H A D | drm_dp_helper.c | 4202 return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count, 4261 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
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H A D | drm_dp_mst_topology.c | 3602 ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count, 4771 return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
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/linux-master/drivers/gpu/drm/ |
H A D | drm_modes.c | 1303 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);
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H A D | drm_rect.c | 65 tmp = mul_u32_u32(src, dst - *clip);
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | i9xx_wm.c | 468 ret = mul_u32_u32(pixel_rate, cpp * latency);
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H A D | intel_atomic_plane.c | 162 return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
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H A D | intel_audio.c | 455 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 456 mul_u32_u32(link_clk, cdclk)); 458 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 459 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 460 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 461 mul_u32_u32(64 * pixel_clk, 1000000));
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H A D | intel_backlight.c | 50 target_val = mul_u32_u32(source_val - source_min,
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H A D | intel_bw.c | 745 return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
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H A D | intel_color.c | 200 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30; 789 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(val, (1 << 16) - 1),
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H A D | intel_cx0_phy.c | 2153 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); 2454 tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
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H A D | intel_display.c | 2542 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 3911 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
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H A D | intel_dp.c | 412 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 728 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
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H A D | intel_dp_mst.c | 84 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, 86 mul_u32_u32(adjusted_mode->crtc_clock, 1030000)); 140 m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n); 417 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
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H A D | intel_dpll.c | 366 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22); 946 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
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H A D | intel_dpll_mgr.c | 3086 tmp = mul_u32_u32(dco_khz, 47 * 32); 3090 tmp = mul_u32_u32(dco_khz, 1000);
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H A D | intel_fb.c | 1131 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]), 1680 if (mul_u32_u32(max_size, tile_size) > intel_bo_to_drm_bo(obj)->size) { 1683 mul_u32_u32(max_size, tile_size), intel_bo_to_drm_bo(obj)->size);
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H A D | intel_fixed.h | 79 tmp = mul_u32_u32(val, mul.val); 91 tmp = mul_u32_u32(val.val, mul.val); 122 tmp = mul_u32_u32(val, mul.val);
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H A D | intel_snps_phy.c | 1947 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
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H A D | intel_sprite.c | 582 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w), 937 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale),
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H A D | intel_vblank.c | 167 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
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/linux-master/drivers/gpu/drm/i915/gem/ |
H A D | i915_gem_create.c | 203 args->size = mul_u32_u32(args->pitch, args->height);
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