Searched refs:dm (Results 1 - 25 of 85) sorted by last modified time

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/haiku/src/add-ons/accelerants/virtio/
H A Daccelerant_protos.h29 status_t virtio_gpu_get_mode_list(display_mode *dm);
35 status_t virtio_gpu_get_pixel_clock_limits(display_mode *dm, uint32 *low,
/haiku/src/add-ons/accelerants/framebuffer/
H A Daccelerant_protos.h29 status_t framebuffer_get_mode_list(display_mode *dm);
34 status_t framebuffer_get_pixel_clock_limits(display_mode *dm, uint32 *low,
/haiku/headers/private/graphics/nvidia/
H A DDriverInterface.h322 display_mode dm; /* current display mode configuration: head1 */ member in struct:__anon21
/haiku/src/add-ons/accelerants/vesa/
H A Daccelerant_protos.h28 status_t vesa_get_mode_list(display_mode *dm);
35 status_t vesa_get_pixel_clock_limits(display_mode *dm, uint32 *low,
66 uint32 vesa_overlay_count(const display_mode *dm);
67 const uint32 *vesa_overlay_supported_spaces(const display_mode *dm);
72 status_t vesa_get_overlay_constraints(const display_mode *dm,
/haiku/src/add-ons/accelerants/via/
H A DProposeDisplayMode.c515 status_t GET_MODE_LIST(display_mode *dm) argument
519 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
H A DSetDisplayMode.c305 si->dm = target;
347 if (si->dm.flags & DUALHEAD_BITS)
350 switch(si->dm.space)
361 LOG(8,("SET:Invalid DH colour depth 0x%08x, should never happen\n", si->dm.space));
367 switch(si->dm.space)
387 switch (si->dm.flags & DUALHEAD_BITS)
391 if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)
395 if ((si->dm.timing.h_display + h_display_start) > si->dm
[all...]
/haiku/src/add-ons/accelerants/skeleton/
H A DProposeDisplayMode.c513 status_t GET_MODE_LIST(display_mode *dm) argument
517 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
/haiku/src/add-ons/accelerants/nvidia/
H A DProposeDisplayMode.c180 SET_DISPLAY_MODE(&si->dm);
572 GET_MODE_LIST(display_mode *dm) argument
576 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
H A DInitAccelerant.c206 si->dm.flags = TV_PRIMARY;
/haiku/src/add-ons/accelerants/neomagic/
H A DProposeDisplayMode.c332 status_t GET_MODE_LIST(display_mode *dm) argument
336 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
H A DOverlay.c15 uint32 OVERLAY_COUNT(const display_mode *dm) argument
22 if (dm == NULL)
30 const uint32 *OVERLAY_SUPPORTED_SPACES(const display_mode *dm) argument
37 if (dm == NULL)
44 if (dm->timing.flags & B_TIMING_INTERLACED)
183 (si->fbc.bytes_per_row * si->dm.virtual_height)); /* size in bytes of screen(s) */
352 (const display_mode *dm, const overlay_buffer *ob, overlay_constraints *oc)
359 if ((dm == NULL) || (ob == NULL) || (oc == NULL))
405 if (dm->virtual_width > 2048)
411 oc->window.width.max = dm
351 GET_OVERLAY_CONSTRAINTS(const display_mode *dm, const overlay_buffer *ob, overlay_constraints *oc) argument
[all...]
/haiku/src/add-ons/accelerants/matrox/
H A DProposeDisplayMode.c464 status_t GET_MODE_LIST(display_mode *dm) argument
468 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
/haiku/src/add-ons/accelerants/radeon_hd/
H A Daccelerant_protos.h32 status_t radeon_get_mode_list(display_mode* dm);
/haiku/src/add-ons/accelerants/intel_extreme/
H A Daccelerant_protos.h33 status_t intel_get_mode_list(display_mode* dm);
/haiku/src/system/libroot/posix/glibc/math/
H A Dk_casinhf.c100 float dm = f / dp; local
101 float r1 = sqrtf ((dm + rx2) / 2.0f);
161 float dm = f / dp; local
166 = log1pf (rx2 + dm + 2.0f * (rx * r1 + ix * r2)) / 2.0f;
H A Dk_casinhl.c107 long double dm = f / dp; local
108 long double r1 = sqrtl ((dm + rx2) / 2.0L);
168 long double dm = f / dp; local
173 = log1pl (rx2 + dm + 2.0L * (rx * r1 + ix * r2)) / 2.0L;
H A Dk_casinh.c100 double dm = f / dp; local
101 double r1 = sqrt ((dm + rx2) / 2.0);
159 double dm = f / dp; local
164 = log1p (rx2 + dm + 2.0 * (rx * r1 + ix * r2)) / 2.0;
/haiku/src/add-ons/accelerants/neomagic/engine/
H A Dnm_bes.c13 * si->dm.h_display_start and si->dm.v_display_start determine where the new
37 crtc_hstart = si->dm.h_display_start;
39 crtc_hend = crtc_hstart + si->dm.timing.h_display;
40 crtc_vstart = si->dm.v_display_start;
42 crtc_vend = crtc_vstart + si->dm.timing.v_display;
/haiku/src/add-ons/kernel/drivers/graphics/et6x00/
H A Ddriver.c676 ET6000DisplayMode *dm = (ET6000DisplayMode *)buf; local
677 if(dm->magic == ET6000_PRIVATE_DATA_MAGIC) {
678 result = et6000ProposeMode(&dm->mode, dm->memSize);
683 ET6000DisplayMode *dm = (ET6000DisplayMode *)buf; local
684 if(dm->magic == ET6000_PRIVATE_DATA_MAGIC) {
685 result = et6000SetMode(&dm->mode, dm->pciConfigSpace);
/haiku/src/add-ons/accelerants/radeon/
H A Doverlay_management.c29 uint32 OVERLAY_COUNT( const display_mode *dm )
33 (void) dm;
40 // dm - display mode where overlay is to be used
41 const uint32 *OVERLAY_SUPPORTED_SPACES( const display_mode *dm )
45 (void) dm;
224 status_t GET_OVERLAY_CONSTRAINTS( const display_mode *dm, const overlay_buffer *ob, argument
231 if( dm == NULL || ob == NULL || oc == NULL )
275 oc->window.width.max = dm->virtual_width;
277 oc->window.height.max = dm->virtual_height;
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_crtc2.c47 switch(si->dm.space)
66 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel;
69 if (si->dm.space != B_RGB32_LITTLE)
750 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
H A Dnv_crtc.c47 switch(si->dm.space)
66 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel;
69 if (si->dm.space != B_RGB32_LITTLE)
770 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
983 if (yhigh < (si->dm.timing.v_display - 16))
1000 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
H A Dnv_acc_dma.c526 switch(si->dm.space)
935 ACCW(NV11_CRTC_LO, si->dm.timing.v_display - 1);
936 ACCW(NV11_CRTC_HI, si->dm.timing.v_display + 1);
1104 switch(si->dm.space)
1739 switch(si->dm.space)
1773 if (si->dm.space == B_RGB15_LITTLE)
1871 if (si->dm.space == B_RGB15_LITTLE)
1938 if (si->dm.space == B_RGB15_LITTLE)
2052 if (si->dm.space == B_RGB15_LITTLE)
/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_crtc.c460 tpixclk = 1000000 / si->dm.timing.pixel_clock;
476 refresh = ((si->dm.timing.pixel_clock * 1000) /
477 ((uint32)si->dm.timing.h_total * (uint32)si->dm.timing.v_total));
487 if ((si->dm.timing.v_display > 768) && (hiprilvl > 3)) hiprilvl = 3;
488 if ((si->dm.timing.v_display > 864) && (hiprilvl > 2) && (refresh >= 76.0)) hiprilvl = 2;
489 if ((si->dm.timing.v_display > 1024) && (hiprilvl > 2)) hiprilvl = 2;
587 if ((si->ps.card_type < G100) && (si->dm.timing.h_total > 2048))
/haiku/headers/os/add-ons/graphics/
H A DAccelerant.h297 typedef status_t (*get_pixel_clock_limits)(display_mode* dm, uint32* low,

Completed in 158 milliseconds

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