/linux-master/arch/arm/boot/compressed/ |
H A D | head-sharpsl.S | 131 bic r3, r3, #0x11 @ SET NCE 132 orr r3, r3, #0x0a @ SET CLR + FLWP 137 orr r3, r3, #4 @ SET ALE
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/linux-master/arch/m68k/fpsp040/ |
H A D | satan.S | 274 |--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE 282 oril #0x04000000,XFRAC(%a6) | ...SET 6-TH BIT TO 1
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H A D | ssin.S | 170 |--SET ADJN TO 0 176 |--SET ADJN TO 1 533 |--SET ADJN TO 4
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/linux-master/arch/m68k/ifpsp060/src/ |
H A D | fplsp.S | 5016 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0 5022 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1 5236 #--SET ADJN TO 4 6275 #--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE 6282 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1
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H A D | fpsp.S | 5122 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0 5128 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1 5342 #--SET ADJN TO 4 6381 #--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE 6388 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1
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/linux-master/arch/mips/mm/ |
H A D | uasm-micromips.c | 199 if (ip->fields & SET)
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H A D | uasm-mips.c | 88 [insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 91 [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 139 [insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, 140 [insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET}, 147 [insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, 148 [insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET}, 265 if (ip->fields & SET)
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H A D | uasm.c | 26 SET = 0x200, enumerator in enum:fields
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/linux-master/drivers/clk/mxs/ |
H A D | clk-imx23.c | 49 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); 70 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
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H A D | clk-imx28.c | 74 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); 84 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); 87 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
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H A D | clk-pll.c | 36 writel_relaxed(1 << pll->power, pll->base + SET); 63 writel_relaxed(1 << 31, pll->base + SET);
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H A D | clk-ref.c | 44 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
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H A D | clk.h | 14 #define SET 0x4 macro
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | ctxnv50.c | 196 cp_set (ctx, UNK01, SET); 202 cp_bra (ctx, UNK0B, SET, cp_prepare_exit); 207 cp_set (ctx, UNK1D, SET); 211 cp_set (ctx, UNK01, SET); 216 cp_set (ctx, UNK03, SET); 226 cp_set (ctx, UNK20, SET);
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/linux-master/drivers/gpu/drm/sti/ |
H A D | sti_awg_utils.c | 17 SET, enumerator in enum:opcode 67 * pixel. So we transform SKIP into SET 69 opcode = SET; 97 case SET: 138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, 148 ret |= awg_generate_instr(SET, val, 0, 0, fwparams);
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/linux-master/drivers/scsi/ |
H A D | script_asm.pl | 669 # Handle SET and CLEAR instructions. Note that we should also do something 671 } elsif (/^\s*(SET|CLEAR)\s+(.*)/i) { 674 $code[$address] = ($set =~ /SET/i) ? 0x58_00_00_00 : 774 SELECT SET, or WAIT
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/linux-master/include/video/ |
H A D | gbe.h | 85 #define SET(v, f, msb, lsb) \ macro 91 SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
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/linux-master/arch/arm64/net/ |
H A D | bpf_jit.h | 125 * ST{ADD,CLR,SET,EOR} is simply encoded as an alias for 126 * LDD{ADD,CLR,SET,EOR} with XZR as the destination register. 136 #define A64_STSET(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, SET) 146 #define A64_LDSETAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SET)
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/linux-master/drivers/accel/ivpu/ |
H A D | ivpu_hw_37xx.c | 851 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET);
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H A D | ivpu_hw_40xx.c | 1006 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
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/linux-master/drivers/clk/imx/ |
H A D | clk-pfd.c | 22 * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc. 32 #define SET 0x4 macro 49 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); 101 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
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/linux-master/drivers/gpu/drm/imx/dcss/ |
H A D | dcss-dev.h | 15 #define SET 0x04 macro 21 #define dcss_set(v, c) writel((v), (c) + SET)
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/linux-master/drivers/gpu/drm/xe/tests/ |
H A D | xe_rtp_test.c | 65 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0))) 69 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1))) 84 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0))) 88 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1))) 103 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0))) 107 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1))) 122 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0))) 126 XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0))) 141 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0))) 180 XE_RTP_ACTIONS(SET(REGULAR_REG [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_tuning.c | 21 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS)) 25 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS)) 46 XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN)) 55 XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE)) 85 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
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H A D | xe_wa.c | 104 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 109 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 120 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 124 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 131 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 135 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 143 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 144 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 145 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 146 SET(XEHP_VEBX_MOD_CTR [all...] |