1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2022 Intel Corporation 4 */ 5 6#include "xe_wa.h" 7 8#include <drm/drm_managed.h> 9#include <kunit/visibility.h> 10#include <linux/compiler_types.h> 11 12#include <generated/xe_wa_oob.h> 13 14#include "regs/xe_engine_regs.h" 15#include "regs/xe_gt_regs.h" 16#include "regs/xe_regs.h" 17#include "xe_device_types.h" 18#include "xe_force_wake.h" 19#include "xe_gt.h" 20#include "xe_hw_engine_types.h" 21#include "xe_mmio.h" 22#include "xe_platform_types.h" 23#include "xe_rtp.h" 24#include "xe_step.h" 25 26/** 27 * DOC: Hardware workarounds 28 * 29 * Hardware workarounds are register programming documented to be executed in 30 * the driver that fall outside of the normal programming sequences for a 31 * platform. There are some basic categories of workarounds, depending on 32 * how/when they are applied: 33 * 34 * - LRC workarounds: workarounds that touch registers that are 35 * saved/restored to/from the HW context image. The list is emitted (via Load 36 * Register Immediate commands) once when initializing the device and saved in 37 * the default context. That default context is then used on every context 38 * creation to have a "primed golden context", i.e. a context image that 39 * already contains the changes needed to all the registers. 40 * 41 * - Engine workarounds: the list of these WAs is applied whenever the specific 42 * engine is reset. It's also possible that a set of engine classes share a 43 * common power domain and they are reset together. This happens on some 44 * platforms with render and compute engines. In this case (at least) one of 45 * them need to keeep the workaround programming: the approach taken in the 46 * driver is to tie those workarounds to the first compute/render engine that 47 * is registered. When executing with GuC submission, engine resets are 48 * outside of kernel driver control, hence the list of registers involved in 49 * written once, on engine initialization, and then passed to GuC, that 50 * saves/restores their values before/after the reset takes place. See 51 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference. 52 * 53 * - GT workarounds: the list of these WAs is applied whenever these registers 54 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 55 * 56 * - Register whitelist: some workarounds need to be implemented in userspace, 57 * but need to touch privileged registers. The whitelist in the kernel 58 * instructs the hardware to allow the access to happen. From the kernel side, 59 * this is just a special case of a MMIO workaround (as we write the list of 60 * these to/be-whitelisted registers to some special HW registers). 61 * 62 * - Workaround batchbuffers: buffers that get executed automatically by the 63 * hardware on every HW context restore. These buffers are created and 64 * programmed in the default context so the hardware always go through those 65 * programming sequences when switching contexts. The support for workaround 66 * batchbuffers is enabled these hardware mechanisms: 67 * 68 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 69 * context, pointing the hardware to jump to that location when that offset 70 * is reached in the context restore. Workaround batchbuffer in the driver 71 * currently uses this mechanism for all platforms. 72 * 73 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 74 * pointing the hardware to a buffer to continue executing after the 75 * engine registers are restored in a context restore sequence. This is 76 * currently not used in the driver. 77 * 78 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 79 * a central place. Those are peppered around the rest of the code, as needed. 80 * Workarounds related to the display IP are the main example. 81 * 82 * .. [1] Technically, some registers are powercontext saved & restored, so they 83 * survive a suspend/resume. In practice, writing them again is not too 84 * costly and simplifies things, so it's the approach taken in the driver. 85 * 86 * .. note:: 87 * Hardware workarounds in xe work the same way as in i915, with the 88 * difference of how they are maintained in the code. In xe it uses the 89 * xe_rtp infrastructure so the workarounds can be kept in tables, following 90 * a more declarative approach rather than procedural. 91 */ 92 93#undef XE_REG_MCR 94#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 95 96__diag_push(); 97__diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 98 99static const struct xe_rtp_entry_sr gt_was[] = { 100 { XE_RTP_NAME("14011060649"), 101 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 102 ENGINE_CLASS(VIDEO_DECODE), 103 FUNC(xe_rtp_match_even_instance)), 104 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 105 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 106 }, 107 { XE_RTP_NAME("14011059788"), 108 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 109 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 110 }, 111 { XE_RTP_NAME("14015795083"), 112 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 113 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 114 }, 115 116 /* DG1 */ 117 118 { XE_RTP_NAME("1409420604"), 119 XE_RTP_RULES(PLATFORM(DG1)), 120 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 121 }, 122 { XE_RTP_NAME("1408615072"), 123 XE_RTP_RULES(PLATFORM(DG1)), 124 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 125 }, 126 127 /* DG2 */ 128 129 { XE_RTP_NAME("22010523718"), 130 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 131 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 132 }, 133 { XE_RTP_NAME("14011006942"), 134 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 135 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 136 }, 137 { XE_RTP_NAME("14014830051"), 138 XE_RTP_RULES(PLATFORM(DG2)), 139 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 140 }, 141 { XE_RTP_NAME("18018781329"), 142 XE_RTP_RULES(PLATFORM(DG2)), 143 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 144 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 145 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 146 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 147 }, 148 { XE_RTP_NAME("1509235366"), 149 XE_RTP_RULES(PLATFORM(DG2)), 150 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 151 INVALIDATION_BROADCAST_MODE_DIS | 152 GLOBAL_INVALIDATION_MODE)) 153 }, 154 155 /* PVC */ 156 157 { XE_RTP_NAME("18018781329"), 158 XE_RTP_RULES(PLATFORM(PVC)), 159 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 160 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 161 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 162 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 163 }, 164 { XE_RTP_NAME("16016694945"), 165 XE_RTP_RULES(PLATFORM(PVC)), 166 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 167 }, 168 169 /* Xe_LPG */ 170 171 { XE_RTP_NAME("14015795083"), 172 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 173 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 174 }, 175 { XE_RTP_NAME("14018575942"), 176 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)), 177 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 178 }, 179 { XE_RTP_NAME("22016670082"), 180 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)), 181 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 182 }, 183 184 /* Xe_LPM+ */ 185 186 { XE_RTP_NAME("16021867713"), 187 XE_RTP_RULES(MEDIA_VERSION(1300), 188 ENGINE_CLASS(VIDEO_DECODE)), 189 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 190 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 191 }, 192 { XE_RTP_NAME("22016670082"), 193 XE_RTP_RULES(MEDIA_VERSION(1300)), 194 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 195 }, 196 197 /* Xe2_LPG */ 198 199 { XE_RTP_NAME("16020975621"), 200 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 201 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 202 }, 203 { XE_RTP_NAME("14018157293"), 204 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 205 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 206 SET(XEHPC_L3CLOS_MASK(1), ~0), 207 SET(XEHPC_L3CLOS_MASK(2), ~0), 208 SET(XEHPC_L3CLOS_MASK(3), ~0)) 209 }, 210 211 /* Xe2_LPM */ 212 213 { XE_RTP_NAME("14017421178"), 214 XE_RTP_RULES(MEDIA_VERSION(2000), 215 ENGINE_CLASS(VIDEO_DECODE)), 216 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 217 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 218 }, 219 { XE_RTP_NAME("16021867713"), 220 XE_RTP_RULES(MEDIA_VERSION(2000), 221 ENGINE_CLASS(VIDEO_DECODE)), 222 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 223 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 224 }, 225 { XE_RTP_NAME("14019449301"), 226 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 227 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 228 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 229 }, 230 231 {} 232}; 233 234static const struct xe_rtp_entry_sr engine_was[] = { 235 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 236 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 237 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 238 FF_TESSELATION_DOP_GATE_DISABLE)) 239 }, 240 { XE_RTP_NAME("1409804808"), 241 XE_RTP_RULES(GRAPHICS_VERSION(1200), 242 ENGINE_CLASS(RENDER), 243 IS_INTEGRATED), 244 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 245 }, 246 { XE_RTP_NAME("14010229206, 1409085225"), 247 XE_RTP_RULES(GRAPHICS_VERSION(1200), 248 ENGINE_CLASS(RENDER), 249 IS_INTEGRATED), 250 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 251 }, 252 { XE_RTP_NAME("1606931601"), 253 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 254 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 255 }, 256 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 257 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 258 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 259 FF_DOP_CLOCK_GATE_DISABLE)) 260 }, 261 { XE_RTP_NAME("1406941453"), 262 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 263 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 264 }, 265 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 266 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 267 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 268 FFSC_PERCTX_PREEMPT_CTRL)) 269 }, 270 271 /* TGL */ 272 273 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 274 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 275 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 276 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 277 RC_SEMA_IDLE_MSG_DISABLE)) 278 }, 279 280 /* RKL */ 281 282 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 283 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 284 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 285 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 286 RC_SEMA_IDLE_MSG_DISABLE)) 287 }, 288 289 /* ADL-P */ 290 291 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 292 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 293 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 294 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 295 RC_SEMA_IDLE_MSG_DISABLE)) 296 }, 297 298 /* DG2 */ 299 300 { XE_RTP_NAME("22013037850"), 301 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 302 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 303 DISABLE_128B_EVICTION_COMMAND_UDW)) 304 }, 305 { XE_RTP_NAME("22014226127"), 306 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 307 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 308 }, 309 { XE_RTP_NAME("18017747507"), 310 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 311 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 312 POLYGON_TRIFAN_LINELOOP_DISABLE)) 313 }, 314 { XE_RTP_NAME("22012826095, 22013059131"), 315 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 316 FUNC(xe_rtp_match_first_render_or_compute)), 317 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 318 MAXREQS_PER_BANK, 319 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 320 }, 321 { XE_RTP_NAME("22013059131"), 322 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 323 FUNC(xe_rtp_match_first_render_or_compute)), 324 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 325 }, 326 { XE_RTP_NAME("14015227452"), 327 XE_RTP_RULES(PLATFORM(DG2), 328 FUNC(xe_rtp_match_first_render_or_compute)), 329 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 330 }, 331 { XE_RTP_NAME("16015675438"), 332 XE_RTP_RULES(PLATFORM(DG2), 333 FUNC(xe_rtp_match_first_render_or_compute)), 334 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE), 335 PERF_FIX_BALANCING_CFE_DISABLE)) 336 }, 337 { XE_RTP_NAME("18028616096"), 338 XE_RTP_RULES(PLATFORM(DG2), 339 FUNC(xe_rtp_match_first_render_or_compute)), 340 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 341 }, 342 { XE_RTP_NAME("22015475538"), 343 XE_RTP_RULES(PLATFORM(DG2), 344 FUNC(xe_rtp_match_first_render_or_compute)), 345 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 346 }, 347 { XE_RTP_NAME("22012654132"), 348 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 349 FUNC(xe_rtp_match_first_render_or_compute)), 350 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 351 /* 352 * Register can't be read back for verification on 353 * DG2 due to Wa_14012342262 354 */ 355 .read_mask = 0)) 356 }, 357 { XE_RTP_NAME("1509727124"), 358 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 359 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 360 }, 361 { XE_RTP_NAME("22012856258"), 362 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 363 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 364 }, 365 { XE_RTP_NAME("22010960976, 14013347512"), 366 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 367 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 368 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 369 }, 370 { XE_RTP_NAME("14015150844"), 371 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 372 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 373 XE_RTP_NOCHECK)) 374 }, 375 376 /* PVC */ 377 378 { XE_RTP_NAME("22014226127"), 379 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 380 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 381 }, 382 { XE_RTP_NAME("14015227452"), 383 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 384 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 385 }, 386 { XE_RTP_NAME("16015675438"), 387 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 388 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE), 389 PERF_FIX_BALANCING_CFE_DISABLE)) 390 }, 391 { XE_RTP_NAME("14014999345"), 392 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 393 GRAPHICS_STEP(B0, C0)), 394 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 395 }, 396 397 /* Xe_LPG */ 398 399 { XE_RTP_NAME("14017856879"), 400 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 401 FUNC(xe_rtp_match_first_render_or_compute)), 402 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 403 }, 404 { XE_RTP_NAME("14015150844"), 405 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 406 FUNC(xe_rtp_match_first_render_or_compute)), 407 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 408 XE_RTP_NOCHECK)) 409 }, 410 411 /* Xe2_LPG */ 412 413 { XE_RTP_NAME("18032247524"), 414 XE_RTP_RULES(GRAPHICS_VERSION(2004), 415 FUNC(xe_rtp_match_first_render_or_compute)), 416 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 417 }, 418 { XE_RTP_NAME("16018712365"), 419 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 420 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 421 }, 422 { XE_RTP_NAME("14018957109"), 423 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 424 FUNC(xe_rtp_match_first_render_or_compute)), 425 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 426 }, 427 { XE_RTP_NAME("16021540221"), 428 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 429 FUNC(xe_rtp_match_first_render_or_compute)), 430 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 431 }, 432 { XE_RTP_NAME("14019322943"), 433 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 434 FUNC(xe_rtp_match_first_render_or_compute)), 435 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 436 }, 437 { XE_RTP_NAME("14018471104"), 438 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 439 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 440 }, 441 { XE_RTP_NAME("16018737384"), 442 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 443 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 444 }, 445 /* 446 * These two workarounds are the same, just applying to different 447 * engines. Although Wa_18032095049 (for the RCS) isn't required on 448 * all steppings, disabling these reports has no impact for our 449 * driver or the GuC, so we go ahead and treat it the same as 450 * Wa_16021639441 which does apply to all steppings. 451 */ 452 { XE_RTP_NAME("18032095049, 16021639441"), 453 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 454 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 455 GHWSP_CSB_REPORT_DIS | 456 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 457 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 458 }, 459 { XE_RTP_NAME("16018610683"), 460 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 461 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 462 }, 463 {} 464}; 465 466static const struct xe_rtp_entry_sr lrc_was[] = { 467 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 468 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 469 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 470 DISABLE_CPS_AWARE_COLOR_PIPE)) 471 }, 472 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 473 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 474 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 475 PREEMPT_GPGPU_LEVEL_MASK, 476 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 477 }, 478 { XE_RTP_NAME("1806527549"), 479 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 480 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 481 }, 482 { XE_RTP_NAME("1606376872"), 483 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 484 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 485 }, 486 487 /* DG1 */ 488 489 { XE_RTP_NAME("1409044764"), 490 XE_RTP_RULES(PLATFORM(DG1)), 491 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 492 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 493 }, 494 { XE_RTP_NAME("22010493298"), 495 XE_RTP_RULES(PLATFORM(DG1)), 496 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 497 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 498 }, 499 500 /* DG2 */ 501 502 { XE_RTP_NAME("16013271637"), 503 XE_RTP_RULES(PLATFORM(DG2)), 504 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 505 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 506 }, 507 { XE_RTP_NAME("14014947963"), 508 XE_RTP_RULES(PLATFORM(DG2)), 509 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 510 PREEMPTION_VERTEX_COUNT, 511 0x4000)) 512 }, 513 { XE_RTP_NAME("18018764978"), 514 XE_RTP_RULES(PLATFORM(DG2)), 515 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 516 SCOREBOARD_STALL_FLUSH_CONTROL)) 517 }, 518 { XE_RTP_NAME("18019271663"), 519 XE_RTP_RULES(PLATFORM(DG2)), 520 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 521 }, 522 { XE_RTP_NAME("14019877138"), 523 XE_RTP_RULES(PLATFORM(DG2)), 524 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 525 }, 526 527 /* PVC */ 528 529 { XE_RTP_NAME("16017236439"), 530 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 531 FUNC(xe_rtp_match_even_instance)), 532 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 533 BCS_SWCTRL_DISABLE_256B, 534 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 535 }, 536 537 /* Xe_LPG */ 538 539 { XE_RTP_NAME("18019271663"), 540 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)), 541 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 542 }, 543 { XE_RTP_NAME("14019877138"), 544 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)), 545 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 546 }, 547 548 /* Xe2_LPG */ 549 550 { XE_RTP_NAME("16020518922"), 551 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 552 ENGINE_CLASS(RENDER)), 553 XE_RTP_ACTIONS(SET(FF_MODE, 554 DIS_TE_AUTOSTRIP | 555 DIS_MESH_PARTIAL_AUTOSTRIP | 556 DIS_MESH_AUTOSTRIP), 557 SET(VFLSKPD, 558 DIS_PARTIAL_AUTOSTRIP | 559 DIS_AUTOSTRIP)) 560 }, 561 { XE_RTP_NAME("14019386621"), 562 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 563 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 564 }, 565 { XE_RTP_NAME("14019877138"), 566 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 567 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 568 }, 569 { XE_RTP_NAME("14020013138"), 570 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 571 ENGINE_CLASS(RENDER)), 572 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 573 }, 574 { XE_RTP_NAME("14019988906"), 575 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 576 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 577 }, 578 { XE_RTP_NAME("16020183090"), 579 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 580 ENGINE_CLASS(RENDER)), 581 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 582 }, 583 584 {} 585}; 586 587static __maybe_unused const struct xe_rtp_entry oob_was[] = { 588#include <generated/xe_wa_oob.c> 589 {} 590}; 591 592static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 593 594__diag_pop(); 595 596/** 597 * xe_wa_process_oob - process OOB workaround table 598 * @gt: GT instance to process workarounds for 599 * 600 * Process OOB workaround table for this platform, marking in @gt the 601 * workarounds that are active. 602 */ 603void xe_wa_process_oob(struct xe_gt *gt) 604{ 605 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 606 607 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 608 ARRAY_SIZE(oob_was)); 609 xe_rtp_process(&ctx, oob_was); 610} 611 612/** 613 * xe_wa_process_gt - process GT workaround table 614 * @gt: GT instance to process workarounds for 615 * 616 * Process GT workaround table for this platform, saving in @gt all the 617 * workarounds that need to be applied at the GT level. 618 */ 619void xe_wa_process_gt(struct xe_gt *gt) 620{ 621 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 622 623 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 624 ARRAY_SIZE(gt_was)); 625 xe_rtp_process_to_sr(&ctx, gt_was, >->reg_sr); 626} 627EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 628 629/** 630 * xe_wa_process_engine - process engine workaround table 631 * @hwe: engine instance to process workarounds for 632 * 633 * Process engine workaround table for this platform, saving in @hwe all the 634 * workarounds that need to be applied at the engine level that match this 635 * engine. 636 */ 637void xe_wa_process_engine(struct xe_hw_engine *hwe) 638{ 639 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 640 641 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 642 ARRAY_SIZE(engine_was)); 643 xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr); 644} 645 646/** 647 * xe_wa_process_lrc - process context workaround table 648 * @hwe: engine instance to process workarounds for 649 * 650 * Process context workaround table for this platform, saving in @hwe all the 651 * workarounds that need to be applied on context restore. These are workarounds 652 * touching registers that are part of the HW context image. 653 */ 654void xe_wa_process_lrc(struct xe_hw_engine *hwe) 655{ 656 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 657 658 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 659 ARRAY_SIZE(lrc_was)); 660 xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc); 661} 662 663/** 664 * xe_wa_init - initialize gt with workaround bookkeeping 665 * @gt: GT instance to initialize 666 * 667 * Returns 0 for success, negative error code otherwise. 668 */ 669int xe_wa_init(struct xe_gt *gt) 670{ 671 struct xe_device *xe = gt_to_xe(gt); 672 size_t n_oob, n_lrc, n_engine, n_gt, total; 673 unsigned long *p; 674 675 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 676 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 677 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 678 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 679 total = n_gt + n_engine + n_lrc + n_oob; 680 681 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 682 if (!p) 683 return -ENOMEM; 684 685 gt->wa_active.gt = p; 686 p += n_gt; 687 gt->wa_active.engine = p; 688 p += n_engine; 689 gt->wa_active.lrc = p; 690 p += n_lrc; 691 gt->wa_active.oob = p; 692 693 return 0; 694} 695 696void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p) 697{ 698 size_t idx; 699 700 drm_printf(p, "GT Workarounds\n"); 701 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 702 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 703 704 drm_printf(p, "\nEngine Workarounds\n"); 705 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 706 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 707 708 drm_printf(p, "\nLRC Workarounds\n"); 709 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 710 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 711 712 drm_printf(p, "\nOOB Workarounds\n"); 713 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 714 if (oob_was[idx].name) 715 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 716} 717 718/* 719 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 720 * adding anything to this function; most workarounds should be implemented 721 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 722 * which are relatively rare. Since the registers these workarounds target are 723 * outside the GT, they should only need to be applied once at device 724 * probe/resume; they will not lose their values on any kind of GT or engine 725 * reset. 726 * 727 * TODO: We may want to move this over to xe_rtp in the future once we have 728 * enough workarounds to justify the work. 729 */ 730void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 731{ 732 struct xe_gt *mmio = tile->primary_gt; 733 734 if (XE_WA(mmio, 22010954014)) 735 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 736} 737